CN100595643C - Liquid crystal display device and driving method thereof - Google Patents

Liquid crystal display device and driving method thereof Download PDF

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Publication number
CN100595643C
CN100595643C CN200610152409A CN200610152409A CN100595643C CN 100595643 C CN100595643 C CN 100595643C CN 200610152409 A CN200610152409 A CN 200610152409A CN 200610152409 A CN200610152409 A CN 200610152409A CN 100595643 C CN100595643 C CN 100595643C
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liquid crystal
lamp
data
crystal panel
driver
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CN1991458A (en
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安智煐
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LG Display Co Ltd
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LG Display Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G09G2330/045—Protection against panel overheating

Abstract

A liquid crystal display device includes a liquid crystal panel having first data lines crossing gate lines on a first region of the liquid crystal panel and second data lines crossing the gate lineson a second region of the liquid crystal panel; a data converter for converting a first video data having a first frame frequency into a second video data having a second frame frequency, which is higher than the first frame frequency; a backlight unit having a first lamp group with at least two lamps for respectively irradiating light onto sub-regions of the first region and a second lamp group with at least two lamps respectively irradiating light on sub-regions of the second region; and a driver for driving the gate lines, the first data lines and the second data lines in accordance with the second video data and for driving the first and second lamp groups at the second frame frequency so that the lamps of the first lamp group are sequentially turned on and off in synchronization withthe lamps of the second lamp group.

Description

Liquid crystal display device and driving method thereof
The present invention requires to enjoy the korean patent application that the application number that proposed on Dec 29th, 2005 is No.2005-0132789 and the application number that proposed on August 25th, 2006 is the rights and interests of the korean patent application of No.10-2006-0080887, at this in conjunction with its full content as a reference.
Technical field
The present invention relates to liquid crystal display device, and relate in particular to a kind of liquid crystal display device and driving method thereof.The present invention is suitable for extensive use.More especially embodiment is suitable for preventing image retention and/or image blurring.
Background technology
Along with the continuous development of information society, the requirement of various display devices is also improved constantly.In order to satisfy these requirements, begun the flat-panel display device that research and development such as liquid crystal display device (LCD), Plasmia indicating panel (PDP) and electroluminescence show (ELD).Especially, LCD is in light weight, thin and have a low-power consumption.Simultaneously, LCD can also provide high image quality.Because LCD has these advantages, LCD is replaced C RT.For example, display device, the graphoscope of TV, the display device of other type are made in the LCD widespread use.
LCD utilizes the optical anisotropy and the polarization characteristic display image of liquid crystal.Because liquid crystal molecule is elongated, so liquid crystal molecule can be arranged with predetermined direction.And, can be by apply the molecular orientation direction of electric field controls liquid crystal molecule to liquid crystal molecule.When controlling the molecular orientation direction of liquid crystal, thereby liquid crystal arrangement makes polarized state of light change along the chain of liquid crystal molecule.Thereby, by the molecular orientation direction of control liquid crystal molecule, displays image information.
Fig. 1 is the synoptic diagram of prior art LCD.As shown in Figure 1, prior art LCD comprises gate driver 4 and the data driver 6, the time schedule controller 8 that is used for control gate driver 4 and data driver 6 that are used for liquid crystal panel for displaying images 2, are used to drive liquid crystal panel 2, is used to produce the back light unit 10 that will shine the light with predetermined luminance on the display panels 2.
In display panels 2, many grid line GL1 to GLn and many data line DL1 to DLm arrangement intersected with each other.Thin film transistor (TFT) (TFT) forms as on-off element at the cross section of grid line GL1 to GLn and data line DL1 to DLm.The sweep signal that TFT response is applied by corresponding grid line GL will be will be switched to the liquid crystal cells Clc that is connected to public pressure wire Vcom by the data voltage that corresponding data line DL provides.
Gate driver 4 applies sweep signal to grid line GL1 to GLn in response to the grid-control system signal that results from time schedule controller 8.Sweep signal is applied to the pulse that grid line GL1 to GLn and each sweep signal have the grid high voltage VGH of translation one by one.The width of the pulse of high voltage VGH equals the width in horizontal-drive signal cycle.In response to sweep signal, grid line GL1 to GLn sequentially enables once in each cycle of each vertical synchronizing signal.
Data driver 6 in response to data controlling signal to convert delegation red (R), green (G), blue (B) pixel data to analog data voltage.Data driver 6 periodically applies data line voltage to data line DL1 to DLm according to horizontal-drive signal.
Time schedule controller 8 adopts vertical/horizontal synchronizing signal (Vsync/Hsync), data enable signal (DE) and clock signal generation grid-control system signal, data controlling signal and the backlight control signal that produces from the external system (not shown) such as the TV signal decoding module of the graphics card of computer system or television receiver.In addition, time schedule controller 8 receives one from the system (not shown) and contains and be useful on each pixel, i.e. the video data of the R in each frame, G, B pixel data, and provide to data driver 6 with line by line the mode pixel data with input.
Back light unit 10 comprises lamp (not shown), optical sheet and is used to drive the lamp driver of lamp.The lamp response produces the light that has the light of predetermined luminance and this generation is provided to liquid crystal panel 2 by the lamp drive signal that lamp driver provides.Lamp driver produces the lamp driving voltage that is used to drive lamp by the voltage (Vdd) that is provided by the power supply (not shown) is provided.Lamp driving voltage provides to lamp according to the lamp control signal that is produced by time schedule controller 8.
Time schedule controller 8 produces grid-control system signal, data controlling signal and backlight control signal.When grid-control system signal was applied to gate driver 4, gate driver 4 provided the sweep signal of the order translation pulse with grid high voltage VGH to grid line GL1 to GLn.The grid high voltage VGH of sweep signal sequentially enables grid line GL1 to GLn.Be connected to the TFT conducting of the grid line GL that enables, thereby transfer to corresponding liquid crystal unit Clc corresponding to the data voltage on the data line DL of this TFT.Therefore, when sweep signal when grid high voltage VGH is converted to grid low-voltage VGL, TFT ends, thus data line DL is not connected with corresponding liquid crystal unit Clc.Liquid crystal cells Clc keeps the data voltage that charges into during the recurrence interval, apply another pulse of grid high voltage VGH in next frame.Drive liquid crystal panel 2 by this process, thus on liquid crystal panel 2 display image.
Keep a frame though offer the data voltage of liquid crystal cells, the sequential in the lamp of back light unit 10 and the frame is irrespectively opened.When showing dynamic image, this maintenance LCD can not tackle image change fast, and moves blooming.Therefore, in LCD, produce unclear image or the image retention that makes the picture quality variation.
In addition, in the LCD of prior art, apply to liquid crystal cells after the data voltage liquid crystal molecule in the liquid crystal cells need the schedule time along and the corresponding direction orientation of the data voltage that applies (hereinafter referred to as the saturated cycle of orientation).During the saturated cycle of orientation, liquid crystal cells is the display pixel data correctly, thereby make generation motion blur phenomenon and more serious image quality decrease.
Summary of the invention
Therefore, the present invention relates to a kind of LCD and driving method thereof, it can be eliminated basically because the limitation of prior art and one or more problem that shortcoming causes.
The object of the present invention is to provide a kind of by preventing that motion blur from improving the LCD of picture quality.
Another object of the present invention is to provide a kind of and can improve the LCD driving method of picture quality by preventing motion blur.
Another object of the present invention is to provide a kind of and can improve the LCD of picture quality by preventing image retention.
Another object of the present invention is to provide a kind of and can improve the LCD driving method of picture quality by preventing image retention.
Attendant advantages of the present invention, purpose and feature will be illustrated in the description of back, by following description, will make it apparent for a person skilled in the art, perhaps can be familiar with by putting into practice the present invention.These purposes of the present invention and other advantage can realize by the structure of specifically noting in instructions and claim and the accompanying drawing and obtain.
In order to realize these purposes and other advantage, and according to purpose of the present invention, as concrete and broad description at this, a kind of liquid crystal display device is provided, comprise: liquid crystal panel, second data line that has first data line that intersects in the first area of liquid crystal panel with grid line and intersect at the second area of liquid crystal panel with grid line; Data converter is used for first video data with first frame rate is converted to second video data with second frame rate that is higher than first frame rate; Back light unit has and comprises and be used for respectively in the first lamp group of at least two lamps of irradiates light on the subregion of first area and comprise the second lamp group that is used at least two lamps of irradiates light on the subregion at second area respectively; And driver, be used for according to the second video data driven grid line, first data line and second data line and be used for driving the first and second lamp groups, thereby the lamp of the lamp of the first lamp group and the second lamp group is synchronously by the order opening and closing with second frame rate.
On the other hand, a kind of liquid crystal display device comprises: liquid crystal panel has grid line intersected with each other and data line; Back light unit has and comprises and be used for subregion in the first lamp group of at least two lamps of the first lamp group of two lamps of irradiates light on the first area of liquid crystal panel with comprise the second lamp group of at least two lamps that are used for irradiates light on the second area of subregion at liquid crystal panel; And driver, be used for according to video data driven grid line with first frame rate and data line and be used to control the first and second lamp groups being driven simultaneously, thereby the lamp of the lamp of the first lamp group and the second lamp group is synchronously by the order opening and closing at second frame rate that is higher than first frame rate.
On the other hand, a kind of liquid crystal display device comprises: liquid crystal panel, second data line that has first data line that intersects in the first area of liquid crystal panel with grid line and intersect at the second area of liquid crystal panel with grid line; Back light unit has and comprises and be used for respectively in the first lamp group of at least two lamps of irradiates light on the subregion of first area and comprise the second lamp group that is used at least two lamps of irradiates light on the subregion at second area respectively; And driver, be used for driven grid line and data line the data voltage of video data is write the liquid crystal cells of first area and the liquid crystal cells of second area simultaneously in line by line mode at each frame, and be used to drive the first and second lamp groups, thereby at least two lamps of at least two lamps of the first lamp group and the second lamp group are synchronously opened in proper order or are closed.
On the other hand, a kind of liquid crystal display device comprises: liquid crystal panel, second data line that has first data line that intersects with grid line in the first area of liquid crystal panel and intersect at the second area of liquid crystal panel and grid line; Back light unit has and comprises and be used for respectively in the first lamp group of at least two lamps of irradiates light on the subregion of first area and comprise the second lamp group that is used at least two lamps of irradiates light on the subregion at second area respectively; And driver, be used to operate grid line and data line the data voltage of video data is write the liquid crystal cells of first area and the liquid crystal cells of second area simultaneously in line by line mode at each frame, and be used to drive the first and second lamp groups, thereby the lamp of the first and second lamp groups writes at data voltage and is unlocked behind the liquid crystal cells of corresponding subregion or closes when the saturated period expires of orientation.
On the other hand, a kind of liquid crystal display device comprises: liquid crystal panel has grid line intersected with each other and data line; Back light unit has and comprises and be used for subregion in the first lamp group of two lamps of irradiates light on the first area of liquid crystal panel with comprise the second lamp group of two lamps that are used for irradiates light on the second area of subregion at liquid crystal panel; And driver, be used for driven grid line and data line the data voltage of video data sequentially being write the liquid crystal cells of liquid crystal panel in mode line by line, and be used to drive the first and second lamp groups to be opened in proper order or to close synchronously with one another at each frame.
On the other hand, a kind of driving method of liquid crystal display device, this liquid crystal display device has liquid crystal panel, this liquid crystal panel has with grid line first data line that intersects on the first area of liquid crystal panel and with the second area of grid line at liquid crystal panel on second data line that intersects, this method comprises that first video data that conversion has first frame rate is second video data with second frame rate that is higher than first frame rate; According to the second video data driven grid line, first and second data lines; And control the first and second lamp groups with the opening and closing simultaneously of second frame rate, the first lamp group has at least two lamps and the second lamp group that are used for the first area and has at least two lamps that are used for second area.
On the other hand, a kind of driving method of liquid crystal display device, this liquid crystal display device have grid line and data line liquid crystal panel intersected with each other, and this method comprises according to video data driven grid line and data line with first frame rate; And control the first and second lamp groups with second frame rate that is higher than first frame rate by the while opening and closing, the first lamp group has at least two lamps of the first area that is used for liquid crystal panel and at least two lamps that the second lamp group has the second area that is used for liquid crystal panel.
On the other hand, a kind of control method of liquid crystal display device, this liquid crystal display device has liquid crystal panel, at least two of the first area of corresponding liquid crystal panel first lamps partly, and at least two second lamps of the second area of corresponding liquid crystal panel partly, wherein this liquid crystal panel has first data line that intersects in the first area with grid line and second data line that intersects at second area with grid line, and this method comprises that driven grid line and data line are to write the liquid crystal cells of first area and the liquid crystal cells of second area to the data voltage of video data simultaneously with row-by-row system; And make the opening and closing simultaneously together of first lamp and second lamp.
On the other hand, a kind of control method of liquid crystal display device, this liquid crystal display device has liquid crystal panel, at least two first lamps of the first area of the corresponding liquid crystal panel of part, and at least two second lamps of the second area of corresponding liquid crystal panel partly, wherein this liquid crystal panel has first data line that intersects in the first area with grid line and second data line that intersects at second area with grid line, and this method comprises that driven grid line and data line are to write the liquid crystal cells of first area and the liquid crystal cells of second area to the data voltage of video data simultaneously with row-by-row system; And drive first and second lamps, thereby the lamp of first and second lamps is unlocked simultaneously when the saturated period expires of orientation after data voltage writes liquid crystal cells on the liquid crystal panel or closes.
Should be understood that, all be exemplary and indicative to general introduction of the present invention and following detailed explanation above, and be intended to provide of the present invention further explanation claimed.
Description of drawings
Included be used to provide the present invention is further explained and the embodiments of the present invention of having introduced the description of drawings that constitutes the application's part, and be used from explanation principle of the present invention with instructions one.In the accompanying drawings:
Fig. 1 is the synoptic diagram of prior art LCD;
Figure 2 shows that the synoptic diagram of the LCD of first embodiment of the invention;
Fig. 3 is the sequential chart of each several part among Fig. 2;
Fig. 4 is the synoptic diagram according to second embodiment of the invention LCD;
Fig. 5 is the sequential chart of each several part among Fig. 4;
Fig. 6 is the synoptic diagram according to third embodiment of the invention LOG type LCD;
Fig. 7 is the synoptic diagram according to four embodiment of the invention LCD;
Fig. 8 is the synoptic diagram according to fifth embodiment of the invention LCD;
Fig. 9 A and Fig. 9 B are depicted as among Fig. 8 each several part according to the sequential chart of first drive pattern; And
Figure 10 A and Figure 10 B be among Fig. 8 each several part according to the sequential chart of second drive pattern.
Embodiment
Below in detail with reference to preferred implementation of the present invention, embodiment shown in the drawings.As far as possible, in whole accompanying drawing, use same Reference numeral for identical or similar parts.
The synoptic diagram of the LCD of Fig. 2 first embodiment of the invention.As shown in Figure 2, LCD comprises the gate driver 104 that is used for liquid crystal panel for displaying images 102, is used to drive more than 102 grid line GL1-GL2k of liquid crystal panel, the second data driver 106B that is used to drive the first data driver 106A of many upper data lines UDL1-UDLm that form on the display panels 102 and is used to drive many lower data lines LDL1-LDLm that form on the display panels 102.
The top A that upper data lines UDL1-UDLm is arranged in liquid crystal panel 102 upward and with a k bar grid line GL1-GLk who vertically arranges intersects.The lower part B that lower data lines LDL1-LDLm is arranged in liquid crystal panel 102 upward and with the 2nd k bar grid line GL (the k+1)-GL2k that vertically arranges intersects.Be formed on the infall of grid line GL1-GL2k and upper data lines UDL1-UDLm and lower data lines LDL1-LDLm as the TFT of on-off element.In response to the sweep signal that is applied to corresponding grid line GL, TFT will be switched to the pixel cell Clc that is connected to concentric line Vcom by the data voltage that corresponding data line UDL and LDL provide.Data voltage and the reference voltage of the liquid crystal cells Clc of liquid crystal panel 102 transmission and data line UDL and LDL, i.e. common electric voltage Vcom, the electric potential difference light that is directly proportional or is inversely proportional to.
Gate driver 104 response grid-control system signals produce the sweep signal that is used for grid line GL1-GL2k.Sweep signal from gate driver 104 is sequentially driven once a k bar grid line GL1 to GLk in the semiperiod of a vertical synchronizing signal, and the 2nd k bar grid line GL (k+1) is sequentially driven once in the semiperiod of a vertical synchronizing signal to GL2k.For example, in the time of the first grid line GL1 in enabling liquid crystal panel 102 top A (that is, the one-period of a horizontal-drive signal), enable the first grid line GL (k+1) among the liquid crystal panel 102 lower part B.In another embodiment, in the horizontal-drive signal cycle of the last item grid line GLk in enabling liquid crystal panel 102 top A, also enable the last item grid line GL2k among the liquid crystal panel 102 lower part B.Thereby, be applied in k the sweep signal of a k bar grid line GL1 to GLk who on liquid crystal panel 102 top A, arranges the pulse after each translation with grid high voltage VGH.Equally, each has the pulse after the translation of grid high voltage VGH to the 2nd k sweep signal of GL2k to be applied to the 2nd k bar grid line GL (k+1) that arranges on liquid crystal panel 102 lower part B.Provide to the sweep signal of a k bar grid line GL1-GLk who in liquid crystal panel 102 top A, arranges and have and the identical waveform of sweep signal that the 2nd k bar grid line GL (the k+1)-GL2k that arranges to the liquid crystal panel 102 lower part B is provided.The width of the pulse of the grid high voltage VGH that contains in the sweep signal equals the cycle of a horizontal-drive signal.
In each cycle of horizontal-drive signal, R, G, B pixel data that the first data driver 106A response data control signal will be equivalent to delegation convert analog data voltage to, and provide the upper data lines UDL1-UDLm that arranges to liquid crystal panel 102 top A with this data line voltage.That is to say, as long as it is one of any to enable the grid line GL1-GLk that arranges at liquid crystal panel 102 top A, promptly in each cycle of a horizontal-drive signal, first data driver 106A output data line voltage.When one of pulse enable grid line GL1-GLk of grid high voltage VGH, be connected to the TFT conducting of the grid line after enabling, thereby transfer to corresponding liquid crystal unit Clc from the data voltage of respective upper data line UDL.When sweep signal when grid high voltage VGH becomes grid low-voltage VGL, the TFT of conducting ends, thus corresponding liquid crystal unit Clc is not electrically connected with corresponding upper data lines UDL.The data voltage that is provided by corresponding data line UDL is provided Clc at TFT conduction period liquid crystal cells, and the data voltage that charges into remains to corresponding TFT conducting once more.
Similarly, in each cycle of horizontal-drive signal, the second data driver 106B converts analog data voltage in response to R, G, the B pixel data that data controlling signal will be equivalent to delegation, and provides the lower data lines LDL1-LDLm that arranges to liquid crystal panel 102 lower part B with data line voltage.As long as it is one of any to enable grid line GL (k+1)-GL2k of arranging at liquid crystal panel 102 lower part B, promptly in each cycle of a horizontal-drive signal, second data driver 106B output data line voltage.When one of pulse enable grid line GL (k+1)-GL2k of grid high voltage VGH, be connected to the TFT conducting of the grid line after enabling, thereby transfer to corresponding liquid crystal unit Clc from the data voltage of respective lower data line LDL.When sweep signal when grid high voltage VGH becomes grid low-voltage VGL, the TFT of conducting ends, thus corresponding liquid crystal unit Clc is not electrically connected with corresponding lower data lines LDL.The data voltage that is provided by corresponding data line LDL is provided Clc at TFT conduction period liquid crystal cells, and the data voltage that charges into remains to corresponding TFT conducting once more.
The gate driver 104 and the first and second data driver 106A and the semiperiod in per frame period of 106B are the semiperiod of vertical synchronizing signal to write data voltage once to the liquid crystal cells of liquid crystal panel 102.
With reference to Fig. 2, LCD comprises the time schedule controller 108 that is used for control gate driver 104, the first and second data driver 106A and 106B, be used to change the video data that will offer time schedule controller 108 frame rate data converter 110 and be used for back light unit 112 to liquid crystal panel 102 irradiates lights.Time schedule controller 108 uses the vertical/horizontal synchronizing signal (Vsync/Hsync), data enable signal (DE) and the clock signal that are produced by the external system (not shown) such as the TV signal decoding module of the graphics card of computer system or television receiver to produce grid-control system signal and data controlling signal.In response to grid-control system signal, the k bar grid line GL1-GLk that gate driver 104 enables to arrange on liquid crystal panel 102 top A sequentially drove once with the semiperiod in a vertical synchronizing signal, and the 2nd k bar GL (the k+1)-GL2k that forces to arrange at liquid crystal panel 102 lower part B is synchronously to drive in proper order with a k bar grid line GL1-GLk.The response data control signal, the first data driver 106A provides data line voltage to upper data lines UDL1-UDLm when one of any enabling a k bar grid line GL1-GLk, and the second data driver 106B provides data line voltage to lower data lines LDL1-LDLm when one of any enabling the 2nd k bar grid line GL (k+1)-GL2k.
In addition, time schedule controller 108 will be arranged in R, G, B pixel data line by line by R, G, the B pixel data that external system provides, and the R of delegation, G, B pixel data are offered first and second data driver 106 and the 106B.Therefore, the first and second data driver 106A and 106B convert the R of delegation, G, B pixel data to analog data voltage.Offer upper and lower data line UDL1-UDLm and LDL1-LDLm simultaneously by the data line voltage after the first data driver 106A conversion with by the data line voltage after the second data driver 106B conversion.
Data converter 110 will be offered the frame rate based on the pixel data of frame of time schedule controller 108 by external system.The frame rate that the pixel data based on frame that offers data converter 110 by external system has first integer (for example, 60Hz), have (for example, 120Hz) from the pixel data based on frame of data converter 110 output corresponding to the frame rate of second integer of the multiple of first integer.In other words, data converter 110 will be from the frame rate frequency multiplication of the pixel data of external system twice at least.Data converter 110 produces interpolating pixel data based on frame by the pixel data based on frame from external system output, and will based on the interpolating pixel data ordering of frame between based on the raw pixel data of frame producing new pixel data, and new pixel data is provided to time schedule controller 108.Time schedule controller 108 control gate drivers 104, first and second data driver 106A and the 106B, thus drive liquid crystal panel 102 with the frame rate (for example 120Hz) of twice primitive frame frequency (for example 60Hz) at least.
Back light unit 112 is included in first to the 8th lamp 113A to 113H that liquid crystal panel 102 lower horizontal are arranged.First to fourth lamp 113A to 113D is arranged as corresponding with liquid crystal panel 102 top A, and that the 5th to the 8th lamp 113E to 113H is arranged as is corresponding with liquid crystal panel 102 lower part B.First to fourth lamp 113A to 113D to the top A of liquid crystal panel 102 by being divided into first to fourth subregion A1 to the A4 irradiates light that four parts limit.For example, the subregion A1 irradiates light of first lamp 113A the top in liquid crystal panel 102 top A, and the 4th lamp 113D subregion A4 irradiates light of below in liquid crystal panel 102 top A.Similarly, the 5th to the 8th lamp 113E to 113H to liquid crystal panel 102 lower part B by being divided into four sub regions B1 to the B4 irradiates lights that four parts limit.For example, the subregion B1 irradiates light of the 5th lamp 113E the top in liquid crystal panel 102 lower part B, and the 8th lamp 113H subregion B4 irradiates light of below in liquid crystal panel 102 lower part B.
Back light unit 112 comprises the first to fourth lamp driver 115A to 115D that is connected to time schedule controller 108 jointly.Each opening and closing simultaneously (perhaps close and open) is used for one of a plurality of lamps of liquid crystal panel 102 top A and is used for one of a plurality of lamps of liquid crystal panel 102 lower part B among the first to fourth lamp driver 115A to 115D.Response is by the lamp control signal of time schedule controller 108 outputs, and first to fourth lamp driver 115A to 115D once is used for the first to fourth lamp 113A to 113D of liquid crystal panel 102 top A with the mode order opening and closing of opening cycle translation predetermined space in the semiperiod of a vertical synchronizing signal.Translation cycle between the unlatching cycle of first to fourth lamp 113A to 113D can be at least with the subregion A1 to A4 of the corresponding liquid crystal panel 102 of lamp 113A to 113D on cycle of liquid crystal cells Clc charging data voltage.Simultaneously, opening and closing once with the first to fourth lamp 113A to 113D that is used for liquid crystal panel 102 top A (more particularly, before or afterwards) for first to fourth lamp driver 115A to 115D will be used for liquid crystal panel 102 lower part B in the semiperiod of a vertical synchronizing signal the 5th to the 8th lamp 113E to 113H.Therefore, thus the 5th to the 8th lamp 113E to 113H also sequentially open to open cycle translation predetermined space.In other words, the unlatching cycle of the lamp 113A to 113D of the subregion A1-A4 of liquid crystal panel 102 or B1 to B4 or 113E to 113H can be different.Thereby the lamp driving voltage that is produced by first to fourth lamp driver 115A to 115D has one of at least the duty factor different with other.
Response is by the lamp control signal of time schedule controller 108 output, the first lamp driver 115A the semiperiod of field cycle or vertical synchronizing signal close and open the first lamp 113A of the top subregion A1 that is used for liquid crystal panel 102 top A simultaneously and be used for liquid crystal panel 102 lower part B the top subregion B1 the 5th lamp 113E once.The first lamp driver 115A is in cycle (the high voltage cycle of DW113AE among Fig. 3) of the liquid crystal cells Clc of the top subregion A1 of data voltage charging liquid crystal panel 102 top A and lower part B and B1 or at high voltage before the cycle and comprise that afterwards the cycle (the low-voltage cycle of LE113AE among Fig. 3) of predetermined space closes the first and the 5th lamp 113A and 113E.On the other hand, in the cycle (the low-voltage cycle of DW113AE among Fig. 3) that the liquid crystal cells Clc of liquid crystal panel 102 the top subregion A1 and B1 keeps the data voltage that charges into, the first lamp driver 115A opens the first and the 5th lamp 113A and the 113E schedule time (the high voltage cycle of LE113AE among Fig. 3).
Response is from the lamp control signal of time schedule controller 108 outputs, and the second lamp driver 115B closes and open second lamp 113B that is used for the liquid crystal panel 102 top A second the top subregion A2 and the 6th lamp 113F that is used for the liquid crystal panel 102 lower part B second the top subregion B2 once simultaneously in the semiperiod of field cycle or vertical synchronizing signal.The second lamp driver 115B in cycle (the high voltage cycle of DW113BF among Fig. 3) of data voltage charging liquid crystal cells Clc in the second the top subregion A2 of liquid crystal panel 102 top A and lower part B and B2 or before comprising the data voltage charge cycle and the cycle (the low-voltage cycle of LE113BF among Fig. 3) of predetermined time interval afterwards close the second and the 6th lamp 113B and 113F.On the other hand, keep the cycle of the data voltage that charges at the liquid crystal cells Clc of the second the top subregion A2 of the top of liquid crystal panel 102 A and lower part B and B2, the second lamp driver 115B opens the second and the 6th lamp 113B and 113F in this cycle (the high voltage cycle of the LE113BF of Fig. 3).
Response is from the lamp control signal of time schedule controller 108 output, the 3rd lamp driver 115C the semiperiod of field cycle or vertical synchronizing signal close simultaneously and open be used for liquid crystal panel 102 top A second below subregion A3 the 3rd lamp 113C and be used for liquid crystal panel 102 lower part B second below subregion B3 the 7th lamp 113G once.The 3rd lamp driver 115C data voltage charging liquid crystal panel 102 top A and lower part B second below among subregion A3 and the B3 liquid crystal cells Clc cycle (the high voltage cycle of DW113CG among Fig. 3) or comprise the data voltage charge cycle before and cycle (the low-voltage cycle of LE113CG among Fig. 3) of afterwards predetermined time interval close the 3rd and the 7th lamp 113C and 113G.On the other hand, liquid crystal panel 102 second below the liquid crystal cells Clc of subregion A3 and B3 cycle of keeping the data voltage that charges into, the 3rd lamp driver 115C opens the 3rd and the 7th lamp 113C and 113G keeps the schedule time (the high voltage cycle of the LE113CG of Fig. 3).
Response is from the lamp control signal of time schedule controller 108 output, the 4th lamp driver 115D the semiperiod of field cycle or vertical synchronizing signal close simultaneously and open be used for liquid crystal panel 102 top A below subregion A4 the 4th lamp 113D and be used for liquid crystal panel 102 lower part B below subregion B4 the 8th lamp 113H once.The 4th lamp driver 115D data voltage charging liquid crystal panel 102 top A and lower part B below among subregion A4 and the B4 liquid crystal cells Clc cycle (the high voltage cycle of DW113DH among Fig. 3) or comprise the data voltage charge cycle before and cycle (the low-voltage cycle of LE113DH among Fig. 3) of afterwards predetermined time interval close the 4th and the 8th lamp 113D and 113H.On the other hand, liquid crystal panel 102 below the liquid crystal cells Clc of subregion A4 and B4 cycle (the low-voltage cycle of DW113DH among Fig. 3) of keeping the data voltage that charges into, the 4th lamp driver 115D opens the 4th and the 8th lamp 113D and 113H keeps the schedule time (the high voltage cycle of the LE113DH of Fig. 3).
From the sequential chart of Fig. 3 as can be seen, time schedule controller 108 control first to fourth lamp driver 115A to 115D are so that be used for the first to fourth lamp 113A to 113D and the 5th to the 8th lamp 113F to the 113H opening and closing sequentially together that are used for liquid crystal panel 102 lower part B of liquid crystal panel 102 top A, thereby the frame period after each conversion is synchronous, and data voltage is written in the liquid crystal cells Clc among liquid crystal panel 102 top A and the liquid crystal panel 102 lower part B simultaneously simultaneously.On the other hand, video data and black level data alternately show once with the frame rate (second frame rate, for example 120Hz) of frame rate (for example first frame rate of 60Hz) twice with the video data that produces from external system on liquid crystal panel 102.Therefore, according to the LCD of embodiment of the present invention can be on liquid crystal panel display video data apace.Thereby, when showing motion picture, can not move blooming.In addition, provide the charging data voltage can also prevent unsharp image or image retention simultaneously to two parts liquid crystal panel, thereby image can occur apace.Therefore, according to embodiment of the present invention, LCD can show higher-quality image.
In addition, owing to a plurality of lamps that are used for a plurality of subregions in liquid crystal panel 102 tops and a plurality of lamps that are used for a plurality of subregions in liquid crystal panel lower part can be by single lamp driver opening and closing, so can simplify the circuit that is used to drive lamp.
Figure 4 shows that synoptic diagram according to the LCD of second embodiment of the invention.With reference to Fig. 4, LCD comprises: be used to drive many left grid line LGL1-LGL2k of the left half that is arranged on liquid crystal panel 202 first grid driver 204A, be used to drive the second gate driver 204B of many right grid line RGL1-RGL2k of the right half that is arranged on liquid crystal panel 202 and the data driver 206 that is used to drive many data line DL1-DL2j that are arranged on the liquid crystal panel.
Left side grid line LGL1-LGL2k is arranged in the left half C of liquid crystal panel 202 and intersects with a j bar data line DL1-DLj that along continuous straight runs is arranged.Right grid line RGL1-RGL2k is arranged in the right half D of liquid crystal panel 202 and intersects with the 2nd j bar data line DL (j+1)-DL2j that along continuous straight runs is arranged.Be formed on the infall of data line DL1-DL2j and left and right grid line LGL1-LGL2k, RGL1-RGL2k as the TFT of on-off element.The sweep signal that TFT response is provided by corresponding grid line GL will be will be offered the liquid crystal cells Clc that is connected to public pressure wire Vcom by the data voltage that the corresponding data line provides.Data voltage and the reference voltage of the liquid crystal cells Clc of liquid crystal panel 202 transmission and data line DL, i.e. common electric voltage Vcom, the electric potential difference light that is directly proportional or is inversely proportional to.
In each cycle, i.e. in each frame period, first grid driver 204A response grid-control system signal produces the sweep signal that is used for left grid line LGL1-LGL2k in a vertical synchronizing signal.Sweep signal from first grid driver 204A sequentially enables a 2k bar grid line LGL1 to LGL2k once in the cycle of a vertical synchronizing signal.The 2k bar left side grid line LGL1-LGL2k that the left half C that the pulse of the one a 2k sweep signal after as the translation of grid high voltage VGH offers specially at liquid crystal panel 202 arranges.The width that is included in the pulse of the grid high voltage VGH in the sweep signal equals the cycle of a horizontal-drive signal.
In each cycle, i.e. in each frame period, second gate driver 204B response grid-control system signal produces the sweep signal that is used for right grid line RGL1-RGL2k in a vertical synchronizing signal.Sweep signal from the second gate driver 204B sequentially enables the 2nd 2k bar grid line RGL1 to RGL2k once in the cycle of a vertical synchronizing signal.The 2nd a 2k sweep signal that is produced by the second gate driver 204B has and the identical waveform of a 2k sweep signal that is produced by first grid driver 204A.Therefore, the right grid line RGL1-RGL2k that is arranged on the right half D of liquid crystal panel 202 sequentially enables with the left grid line LGL of the left half that is arranged on liquid crystal panel 202 or forbids.
Data driver 206 converts R, G, the B pixel data of suitable delegation to analog data voltage at each periodic response data controlling signal of horizontal-drive signal, and data line voltage is offered the data line DL1-DL2j that is arranged in liquid crystal panel 202.When order enables 2k to a left side and right grid line LGL1-LGL2k and RGL1-RGL2k in couples, promptly in each cycle of a horizontal-drive signal, data driver 206 output data line voltages.If the pulse enable 2k by grid high voltage VGH is among a left side and right grid line LGL1-LGL2k and the RGL1-RGL2k during a pair of grid line, be connected to the TFT conducting of this left side that enables and right grid line LGL and RGL, thereby transfer to corresponding liquid crystal unit Clc from the data voltage of corresponding data line DL.When a pair of sweep signal when grid high voltage VGH changes to grid low-voltage VGL, the TFT of conducting ends, thus corresponding liquid crystal unit Clc is not electrically connected with corresponding data line DL.Liquid crystal cells Clc charges into the data voltage that is provided by corresponding data line DL at the turn-on cycle of TFT, and the data voltage that charges into is retained to corresponding TFT conducting once more.
The gate driver 104 and the first and second data driver 106A and 106B i.e. the cycle of every vertical synchronizing signal, write data voltage once to the liquid crystal cells Clc of liquid crystal panel 102 in the frame period.
With reference to Fig. 4, LCD comprises the time schedule controller 208 that is used to control the first and second gate driver 204A and 204B, data driver 206 and is used for back light unit 210 to liquid crystal panel 202 irradiates lights.Time schedule controller 208 uses the vertical/horizontal synchronizing signal (Vsync/Hsync), data enable signal (DE) and the clock signal that are produced by the external system (not shown) such as the TV signal decoding module of the graphics card of computer system or television receiver to produce the data controlling signal that is used to control the grid-control system signal of the first and second gate driver 204A and 204B and is used for data driver 206.In response to the grid-control system signal that produces from time schedule controller 208, the first and second gate driver 204A and 204B make the 2k that on liquid crystal panel 202 left half C and right half D, arranges to grid line LGL1-LGL2k and RGL1-RGL2k in the cycle of a vertical synchronizing signal, promptly the frame period sequentially drives once.2k is any in to grid line LGL1-LGL2k and RGL1-RGL2k to provide data line voltage with row-by-row system to data line DL1-DL2j when a pair of enabling for response data control signal, data driver 206.
In addition, time schedule controller 208 is provided by R, G, the B pixel data that is provided line by line by external system, and in each cycle of horizontal-drive signal the R of delegation, G, B pixel data is offered data driver 206.Data driver 206 converts the R of delegation, G, B pixel data to analog data voltage.Offer data line DL1-DL2j simultaneously by the data line voltage after data driver 206 conversions.
Back light unit 210 is included in first to the 8th lamp 213A to 213H that liquid crystal panel 202 lower horizontal are arranged.First to fourth lamp 213A to 213D is arranged as corresponding with liquid crystal panel 202 top A, and that the 5th to the 8th lamp 213E to 213H is arranged as is corresponding with liquid crystal panel 202 lower part B.First to fourth lamp 213A to 213D is divided into four parts and first to fourth subregion A1 to the A4 irradiates light that limits to the top A with liquid crystal panel 202 respectively.For example, the first lamp 213A is the top subregion A1 irradiates light in liquid crystal panel 202 top A, and the 4th lamp 213D below subregion A4 irradiates light in liquid crystal panel 202 top A.Similarly, the 5th to the 8th lamp 213E to 213H respectively in liquid crystal panel 202 lower part B by being divided into four sub regions B1 to the B4 irradiates lights that four parts limit.For example, the 5th lamp 213E is the top subregion B1 irradiates light in liquid crystal panel 202 lower part B, and the 8th lamp 213H below subregion B4 irradiates light in liquid crystal panel 202 lower part B.
Back light unit 210 comprises the first to fourth lamp driver 215A to 215D that is connected to time schedule controller 208 jointly.Each opening and closing simultaneously among the first to fourth lamp driver 215A to 215D (more particularly, before or afterwards) are used for one of a plurality of lamps of liquid crystal panel 202 top A and are used for twice on one of a plurality of lamps of liquid crystal panel 202 lower part B.Response is by the lamp control signal of time schedule controller 208 output, and the first to fourth lamp 213A to 213D that first to fourth lamp driver 215A to 215D is used for liquid crystal panel 202 top A with the mode order opening and closing of opening cycle translation predetermined space in a vertical synchronizing signal cycle once.Translation cycle between the unlatching cycle of lamp can for one of the corresponding subregion of lamp 213A to 213D A1 to A4 on cycle of liquid crystal cells Clc charging data voltage.Simultaneously, first to fourth lamp driver 215A to 215D will be used for the 5th to the 8th lamp 213E to 213H of liquid crystal panel 202 lower part B with first to fourth lamp 213A to 213D opening and closing.Therefore, thereby the 5th to the 8th lamp 213E to 213H sequentially opens the semiperiod in vertical synchronizing signal, i.e. in the field cycle, open cycle translation predetermined space.In other words, the unlatching cycle of the lamp 213A to 213D of subregion A1-A4 or B1-B4 or 213E to 213H can be different.Thereby the lamp driving voltage that is produced by first to fourth lamp driver 215A to 215D has one of at least the duty factor different with other.
Response is by the lamp control signal of time schedule controller 208 outputs, the first lamp driver 215A is at the half cycle of vertical synchronizing signal, be the field cycle, opening and closing simultaneously be used for liquid crystal panel 202 top A the top subregion A1 the first lamp 213A and be used for liquid crystal panel 202 lower part B the top subregion B1 the 5th lamp 213E once.The first lamp driver 215A in cycle (the high voltage cycle of DW213A and DW213E among Fig. 5) of the liquid crystal cells Clc of the top subregion A1 of data voltage charging liquid crystal panel 202 top A and B and B1 or before being included in the data voltage charge cycle and the cycle (the low-voltage cycle of LE213AE among Fig. 5) of predetermined space afterwards close the first and the 5th lamp 213A and 213E.On the other hand, in the cycle (the low-voltage cycle of DW213A and DW213E among Fig. 5) that the liquid crystal cells Clc of liquid crystal panel 202 the top subregion A1 and B1 keeps data voltages charged, the first lamp driver 215A opens the first and the 5th lamp 213A and the 213E schedule time (the high voltage cycle of LE213AE among Fig. 5).
Response is from the lamp control signal of time schedule controller 208 outputs, the second lamp driver 215B is at the half cycle of vertical synchronizing signal, be the field cycle, close and open second lamp 213B that is used for the liquid crystal panel 202 top A second the top subregion A2 and the 6th lamp 213F that is used for the liquid crystal panel 202 lower part B second the top subregion B2 simultaneously once.The second lamp driver 215B in cycle (the high voltage cycle of DW213B and DW213F among Fig. 5) of data voltage charging liquid crystal cells Clc in the second the top subregion A2 of liquid crystal panel 202 top A and lower part B and B2 or before comprising the data voltage charge cycle and the cycle (the low-voltage cycle of LE213BF among Fig. 5) of predetermined time interval afterwards close the second and the 6th lamp 213B and 213F.On the other hand, keep at the liquid crystal cells Clc of the second the top subregion A2 of the top of liquid crystal panel 202 A and lower part B and B2 during the cycle of the data voltage that charges into, the second lamp driver 215B opens the second and the 6th lamp 213B and the 213F schedule time (the high voltage cycle of the LE213BF of Fig. 5).
Response is from the lamp control signal of time schedule controller 208 outputs, the 3rd lamp driver 215C is at the half cycle of vertical synchronizing signal, be the field cycle, close simultaneously and open be used for liquid crystal panel 202 top A second below subregion A3 the 3rd lamp 213C and be used for liquid crystal panel 202 lower part B second below subregion B3 the 7th lamp 213G once.The 3rd lamp driver 215C data voltage charging liquid crystal panel 202 top A and lower part B second below among subregion A3 and the B3 liquid crystal cells Clc cycle (the high voltage cycle of DW213C and DW213G among Fig. 5) or comprise the data voltage charge cycle before and cycle (the low-voltage cycle of LE213CG among Fig. 5) of afterwards predetermined time interval close the 3rd and the 7th lamp 213C and 213G.On the other hand, in second during the liquid crystal cells Clc of subregion A3 and B3 keeps the cycle of the data voltage that charges into below of liquid crystal panel 202, the 3rd lamp driver 215C opens the 3rd and the 7th lamp 213C and 213G keeps the schedule time (the high voltage cycle of the LE213CG of Fig. 5).
Response is from the lamp control signal of time schedule controller 208 outputs, the 4th lamp driver 215D is at the half cycle of vertical synchronizing signal, be the field cycle, close and open the 4th lamp 213D of the below subregion A4 that is used for liquid crystal panel 202 top A simultaneously and be used for liquid crystal panel 202 lower part B below subregion B4 the 8th lamp 213H once.The 4th lamp driver 215D data voltage charging liquid crystal panel 202 top A and lower part B below among subregion A4 and the B4 liquid crystal cells Clc cycle (the high voltage cycle of DW213D and DW213H among Fig. 5) or comprise the data voltage charge cycle before and cycle (the low-voltage cycle of LE213DH among Fig. 5) of afterwards predetermined time interval close the 4th and the 8th lamp 213D and 213H.On the other hand, liquid crystal panel 202 below the liquid crystal cells Clc of subregion A4 and B4 keep cycle of the data voltage that charges into during (the low-voltage cycle of DW213D and DW213H among Fig. 5), the 4th lamp driver 215D opens the 4th and the 8th lamp 213D and 213H keeps the schedule time (the high voltage cycle of the LE213DH of Fig. 5).
From the sequential chart of Fig. 5 as can be seen, first to fourth lamp driver 215A to 215D was used in the first to fourth lamp 213A to 213D of liquid crystal panel 202 top A and is used for the 5th to the 8th lamp 213E to the 213H opening and closing sequentially twice of liquid crystal panel 202 lower part B with the synchronous mode of the 5th to the 8th lamp 213F to 213H with first to fourth lamp 213A to 213D in each frame period, sequentially write delegation in the multirow liquid crystal cells simultaneously at every turn.Thereby video data and black level data alternately show twice with the frame rate (second frame rate, for example 120Hz) of frame rate (for example first frame rate of 60Hz) twice with the video data that produces from external system on liquid crystal panel 202.Therefore, according to the LCD of embodiment of the present invention can be on liquid crystal panel display video data apace.Thereby, when showing motion picture, can not move blooming.
In addition, be used for a plurality of lamps of a plurality of subregions in liquid crystal panel 202 tops and be used for a plurality of lamps of a plurality of subregions of liquid crystal panel lower part can be by single lamp driver opening and closing.Therefore can simplify the circuit that is used to drive lamp.
In the LCD according to embodiment of the present invention, the grid line that is used to enable the TFT of delegation is divided into left grid line and right grid line, thereby can drive left grid line and right grid line respectively.Therefore, can reduce the propagation delay of sweep signal on grid line.Therefore, can respond fast-changing image, thereby improve picture quality according to the LCD of embodiment of the present invention.
Figure 6 shows that according to the reach the standard grade synoptic diagram of (LOG) type LCD of the glass of third embodiment of the invention.With reference to Fig. 6, LCD comprises: be used for liquid crystal panel for displaying images 302; Be connected a plurality of data carrier bands encapsulation (TCP) 318a to 318c between liquid crystal panel 302 and the data pcb (PCB) 320, at a plurality of grid TCP316a to 316d of liquid crystal panel 302 1 sides and opposite side setting, be installed in the data-driven IC306a to 306c on the data TCP318a to 318c and be installed in a plurality of data-driven IC 304a to 304d on the grid TCP316a to 316d.Liquid crystal panel 302 comprise infrabasal plate 311, upper substrate 313 and be clipped in infrabasal plate 311 and upper substrate 313 between the liquid crystal (not shown).Infrabasal plate 311 and upper substrate 313 are transparent insulation substrate.In a plurality of grid TCP316a and 316d, the first and second grid TCP316a and 316b are arranged on a side of liquid crystal panel 302.The one LOG type signal line group 314a is arranged on infrabasal plate 311 and is installed in first and second grid drive IC 304a and the 304b on the first and second grid TCP316a and the 316b to be connected in series.In addition, the third and fourth grid TCP 316c and 316d are arranged on the opposite side of liquid crystal panel 302.The 2nd LOG type signal line group 314b is arranged on the infrabasal plate 311 third and fourth grid drive IC 304c and the 304d that is installed in to be connected in series on the third and fourth grid TCP316c and the 316d.
Liquid crystal panel 302 is included in many left grid line LGL1-LGL2k that vertically arrange on the left half C of liquid crystal panel 302 and many right grid line RGL1-RGL2k that vertically arrange on the right half D of liquid crystal panel 302.Left side grid line LGL1-LGL2k and the j bar data line DL1-DLj that left half C at liquid crystal panel 302 is provided with intersect, and right grid line RGL1-RGL2k intersects with the 2nd j bar data line DL1 (j+1)-DL2j in the right half D of liquid crystal panel 302 setting.Drive left grid line LGL1-LGL2k in proper order by the first and second grid drive IC 304a and 304b, and by the third and fourth grid drive IC 304c and 304d to drive right grid line RGL1-RGL2k in proper order with the synchronous mode of left grid line LGL1-LGL2k.During a pair of grid line in enabling left grid line LGL and right grid line RGL, the data line DL1-DL2j data voltage that all charges.Drive grid line LGL1-LGL2k and RGL1-RGL2k and the data line DL1-DL2j that is arranged on the liquid crystal panel 302 in mode same as shown in Figure 4.That is to say, drive liquid crystal panel 302, be connected to the first to fourth grid drive IC 304a to 304d and first to the 3rd data-driven IC306a to 306c of liquid crystal panel 302 in the mode identical with mode shown in Figure 4.Therefore, omit detailed description below to liquid crystal panel 302, first to fourth grid drive IC 304a to 304d and first to the 3rd data-driven IC306a to 306c.
The LOG type LCD of Fig. 6 is included in first to the 8th lamp 213A to 213H that liquid crystal panel 302 lower horizontal arrange, is installed in time schedule controller 308 and lamp driver 215 on the data PCB320.First to fourth lamp 213A to 213D is arranged as corresponding with liquid crystal panel 302 top A, and that the 5th to the 8th lamp 213E to 213H is arranged as is corresponding with liquid crystal panel 302 lower part B.First to fourth lamp 213A to 213D is respectively to being divided into the subregion irradiates light that four parts limit by the top A with liquid crystal panel 302.For example, the first lamp 213A is the top subregion A1 irradiates light in liquid crystal panel 302 top A, and the 4th lamp 213D below subregion A4 irradiates light in liquid crystal panel 302 top A.Similarly, the 5th to the 8th lamp 213E to 213H is respectively to be divided into the subregion irradiates light that four parts limit in liquid crystal panel 302 lower part B.For example, the 5th lamp 213E is the top subregion B1 irradiates light in liquid crystal panel 302 lower part B, and the 8th lamp 213H below subregion B4 irradiates light in liquid crystal panel 302 lower part B.
Response is by the lamp control signal of time schedule controller 308 outputs, lamp driver 215 is in the semiperiod of vertical synchronizing signal, be the field cycle, simultaneously and the order opening and closing lamp 213E to 213H that is used for the lamp 213A to 213D of liquid crystal panel 302 top A and is used for liquid crystal panel 302 lower part B once.First to fourth lamp 213A to 213D is with the mode orderly close-down and the unlatching of their unlatching cycle translation predetermined space.Translation cycle between the unlatching cycle of first to fourth lamp 213A to 213D is corresponding with the cycle that liquid crystal cells Clc at this subregion charges into data voltage.The the 5th to the 8th lamp 213E to 213H that is used for liquid crystal panel 302 lower part B is respectively with first to fourth lamp 213A to 213D opening and closing simultaneously.Therefore, in the semiperiod of vertical signal, i.e. in the field cycle, the 5th to the 8th lamp 213E to 213H order is opened once, thus their unlatching cycle translation predetermined space.In order to drive first to the 8th lamp 213A to 213H in the above described manner, lamp driver 215 comprises first to fourth lamp driver 215A to 215D shown in Figure 4.Because lamp driver 215 is similar to the detailed description of Fig. 4 with first to the 8th lamp 213A to 213H, so omitted detailed description about lamp driver.
From the sequential chart of Fig. 5 as can be seen, time schedule controller 308 control gate drive IC 304a to 304d and data driver 306a to 306c in every frame in the liquid crystal cells Clc of liquid crystal panel 302 each delegation sequentially write data once, and twice of control lamp driver 215 opening and closing first to the 8th lamp 213A to 213H.Because the detailed description of time schedule controller 308 and Fig. 4 is similar, so omit detailed description here about time schedule controller 308.
From the sequential chart of Fig. 5 as can be seen, the LOG type LCD of Fig. 6 is writing in the frame period of a secondary data in whole liquid crystal cells Clc of liquid crystal panel 302, is used for the first to fourth lamp 213A to 213D and the 5th to the 8th lamp 213E to 213D that is used for the lower part B of liquid crystal panel 302 of liquid crystal panel 302 top A for twice with the synchronous mode order opening and closing of first to fourth 213A to 213D and the 5th to the 8th lamp 213E to 213H.That is to say, on liquid crystal panel 302 with the frame rate (second frame rate, for example 120Hz) of the frame rate of the video data that produces by external system (as, first frame rate of 60Hz) twice alternately display video data and black level data.Therefore, the LOG type LCD according to embodiment of the present invention can respond video data apace.Thereby when showing moving image, can not move blooming.
In addition, be used for the top subregion lamp and be used for the lamp of lower part subregion by same lamp driver opening and closing.Therefore, can oversimplify the circuit that is used to drive lamp.
In the LOG type LCD according to the 3rd embodiment, the grid line that is used to enable the TFT of delegation is divided left grid line and right grid line, thereby drives left grid line and right grid line respectively.Therefore, can reduce the propagation delay time of sweep signal at grid line.Therefore, can respond fast-changing image, thereby improve picture quality according to the LOG type LCD of embodiment of the present invention.
Figure 7 shows that synoptic diagram according to the LCD of four embodiment of the invention.With reference to Fig. 7, comprise the gate driver 404 that is used to drive many grid line GL1-GL2k that are arranged on liquid crystal panel 402 according to the LCD of four embodiment of the invention; And the data driver 406 that is used to drive many data line DL1-DL2j that are arranged on liquid crystal panel 402.
Grid line GL1-GL2k is arranged on the liquid crystal panel 402 and intersects with data line DL1-DL2j that horizontal direction is arranged.TFT as on-off element is formed on data line DL1-DL2j and grid line GL1-GL2k infall.The sweep signal that response is applied by corresponding grid line GL, TFT will be switched to the liquid crystal cells Clc that is connected to public pressure wire Vcom by the data voltage that corresponding data line DL provides.The liquid crystal cells Clc of liquid crystal panel 402 sees through and the data voltage of data line DL and reference voltage are the proportional light of electric potential difference between the common electric voltage Vcom.
In each cycle of a vertical synchronizing signal, promptly in each frame period, gate driver 404 response grid-control system signals produce and provide to the sweep signal of grid line GL1-GL2k.Sweep signal from gate driver 404 is driven once 2k bar grid line GL1 to GL2k in proper order in the cycle of a vertical synchronizing signal.For this reason, 2k the sweep signal that offers on liquid crystal panel 402 the 2k bar grid line GL1-GL2k that arranges has the translation pulse of grid high voltage VGH with differing from one another.The width that is included in the pulse of the grid high voltage VGH in the sweep signal equals the signal period in level step.
In each cycle of horizontal-drive signal, data driver 406 will convert analog data voltage to the R that is equivalent to delegation, G, B pixel data in response to data controlling signal, and data line voltage is provided to the data line DL1-DL2j that is arranged on the liquid crystal panel 402.Specifically, if enable among the 2k bar grid line GL1-GL2k one of any, promptly in each cycle of a horizontal-drive signal, data driver 406 output data line voltages.When one of pulse enable grid line GL1-GL2k of grid high voltage VGH, be connected to the TFT conducting of the grid line GL after enabling, thereby transfer to corresponding liquid crystal unit Clc from the data voltage of corresponding data line DL.When sweep signal when grid high voltage VGH becomes grid low-voltage VGL, the TFT of conducting ends, thus corresponding liquid crystal unit Clc is not electrically connected with corresponding data line DL.The data voltage that is provided by corresponding data line DL is provided turn-on cycle liquid crystal cells Clc at TFT, and the data voltage that charges into remains to corresponding TFT conducting once more.
Gate driver 404 and data driver 406 be in per frame period, i.e. each cycle of vertical synchronizing signal, write data voltage once to the liquid crystal cells of liquid crystal panel 402.
With reference to Fig. 7, LCD comprises the time schedule controller 408 that is used for control gate driver 404, data driver 406 and is used for back light unit 410 to liquid crystal panel 402 irradiates lights.Time schedule controller 408 uses the vertical/horizontal synchronizing signal (Vsync/Hsync), data enable signal (DE) and the clock signal that are produced by the external system (not shown) such as the TV signal decoding module of the graphics card of computer system or television receiver to produce grid-control system signal that is used for control gate driver 404 and the data controlling signal that is used for control data driver 406.The grid-control system signal that response is produced by time schedule controller 408, gate driver 404 orders drive the 2k bar grid line GL1-GL2k that arranges on liquid crystal panel 402.The data controlling signal that response is produced by time schedule controller 408, data driver 406 provides data line voltage line by line to data line DL1-DL2j.
Time schedule controller 408 will be arranged in mode line by line by R, G, B pixel data that external system provides, and in each cycle of horizontal-drive signal the R of delegation, G, B pixel data be offered data driver 406.Therefore, data driver 406 converts the R of delegation, G, B pixel data to analog data voltage.Offer data line DL1-DL2j simultaneously by the data line voltage after data driver 406 conversions.
Similar to the back light unit 210 of Fig. 4, back light unit 410 is included in first to the 8th lamp 213A to 213H and the first to fourth lamp driver 215A to 215D that liquid crystal panel 402 lower horizontal are arranged.First to fourth lamp 213A to 213D is arranged as corresponding with liquid crystal panel 402 top A, and that the 5th to the 8th lamp 213E to 213H is arranged as is corresponding with liquid crystal panel 402 lower part B.First to fourth lamp 213A to 213D respectively to the top A of liquid crystal panel 402 by being divided into the first to fourth subregion irradiates light that four parts limit.For example, the first lamp 213A is the top subregion A1 irradiates light in liquid crystal panel 402 top A, and the 4th lamp 213D below subregion A4 irradiates light in liquid crystal panel 402 top A.Similarly, the 5th to the 8th lamp 213E to 213H respectively in liquid crystal panel 402 lower part B by being divided into the four sub regions irradiates lights that four parts limit.For example, the 5th lamp 213E is the top subregion B1 irradiates light in liquid crystal panel 402 lower part B, and the 8th lamp 213H below subregion B4 irradiates light in liquid crystal panel 402 lower part B.
Response is by the lamp control signal of time schedule controller 408 outputs, in the cycle of a vertical synchronizing signal, the 5th to the 8th lamp 213E to 213H that first to fourth lamp driver 215A to 215D will be used for the first to fourth lamp 213A to 213D of liquid crystal panel 402 top A and be used for liquid crystal panel 402 lower part B together simultaneously and twice of opening and closing sequentially.Response is by the lamp control signal of time schedule controller 408 outputs, first to fourth lamp driver 215A to 215D is in each semiperiod of vertical synchronizing signal, i.e. in half and half frame period to open one time first to fourth lamp 213A to 213D of mode opening and closing sequentially of cycle translation predetermined space.Translation cycle between the unlatching cycle of first to fourth lamp 213A to 213D can be the cycle of the charging of the liquid crystal cells Clc on one of liquid crystal panel 402 subregion A1 to A4 data voltage.Simultaneously, be used for the 5th to the 8th lamp 213E to 213H of liquid crystal panel 202 lower part B respectively with first to fourth lamp 213A to 213D opening and closing.Therefore, in the semiperiod of vertical synchronizing signal, i.e. field cycle, the 5th to the 8th lamp 213E to 213H with the unlatching cycle sequentially the mode of translation predetermined space sequentially open once.In other words, can be different between the unlatching cycle of the lamp 213A to 213D of the subregion A1-A4 of liquid crystal panel 402 or B1-B4 or 213E to 213H.Thereby the lamp driving voltage that is produced by first to fourth lamp driver 215A to 215D has one of at least the duty factor different with other.Because first to fourth lamp driver 215A to 215D is similar to the explanation to Fig. 4 to first to the 8th lamp 213A to 213H, so omit detailed description thereof.
From the sequential chart of Fig. 5 as can be seen, the LOG type LCD of Fig. 7 writes at the whole liquid crystal cells Clc to liquid crystal panel 402 during frame period of video data with twice of the synchronous mode opening and closing sequentially first to fourth lamp 213A to 213D of first to fourth lamp 213A to 213D that is used for liquid crystal panel 402 top A and the 5th to the 8th lamp 213E to 213H that is used for liquid crystal panel 402 lower part B and the 5th to the 8th lamp 213E to 213H.That is to say that video data and black level data alternately show twice with the frame rate (second frame rate, for example 120Hz) of frame rate (for example first frame rate of 60Hz) twice with the video data that produces from external system on liquid crystal panel 202.Therefore, the LOG type LCD according to embodiment of the present invention can respond video data apace.Thereby, when showing moving image, can not move blooming.In addition, alternately display video data and black level data also prevent unsharp image or image retention twice on liquid crystal panel, thus presentation video fast.Therefore, according to the LCD raising picture quality of embodiment of the present invention, it is minimum that brightness is reduced.
In addition, the lamp and the lamp that is used for liquid crystal panel lower part subregion that are used for liquid crystal panel top subregion by same data driver opening and closing.Therefore, can simplify the circuit that is used to drive lamp.
Figure 8 shows that synoptic diagram according to the LCD of fifth embodiment of the invention.LCD according to fifth embodiment of the invention is similar to LCD shown in Figure 2, and difference is not have data converter 110 but time schedule controller 108 directly receives from the video data such as system's (not shown) of the TV signal decoding module of the image card of computer system or television receiver.Different with LCD among Fig. 2, liquid crystal panel 102 that comprises among the LCD among Fig. 8 and lamp 113A to 113H are with frame rate (for example, the 60Hz) work of original video data.In addition, can optionally drive liquid crystal panel 102 and lamp 113A to 113H with first drive pattern or second drive pattern.Under first drive pattern, the LCD of Fig. 8 drives according to the sequential shown in Fig. 9 A and Fig. 9 B.Under second drive pattern, the LCD of Fig. 8 drives according to the sequential shown in Figure 10 A and Figure 10 B.For convenience, the work of LCD will be called the 6th embodiment of the present invention under second drive pattern.To describe the LCD of Fig. 8 according to drive pattern in detail below.
With reference to Fig. 9 A, gate driver 104 promptly in each cycle (1/60 second) of vertical synchronizing signal, sequentially enables the once grid line GL1-GLk on liquid crystal panel 102 top A in each frame period of video data.Gate driver 104 sequentially enables once grid line GL (the k+1)-GL2k on liquid crystal panel 102 lower part B synchronously to drive with grid line GL1-GLk.For example, gate driver 104 side by side enables two cycles of the first grid line GL1 and (k+1) bar grid line GL (k+1) horizontal-drive signal, side by side enable two cycles of the second grid line GL2 and (k+2) bar grid line GL (k+2) horizontal-drive signal, side by side enable two cycles of the 3rd grid line GL3 and (k+3) bar grid line GL (k+3) horizontal-drive signal.In this way, k bar grid line GLk and 2k bar grid line GL2k side by side are enabled last two cycles of horizontal-drive signal.That is to say that gate driver 104 is by driving k continues horizontal-drive signal to a k bar grid line GL1-GLk who is used for liquid crystal panel 102 top A and the 2nd k bar grid line GL (the k+1)-GL2k that is used for liquid crystal panel lower part B two cycles over the ground.For this reason, shown in Fig. 9 A, gate driver 104 i.e. each frame period, provides 2k sweep signal SGL1-SGL2k to 2k bar grid line GL1-GL2k respectively in each cycle of vertical synchronizing signal.2k sweep signal SGL1-SGL2k is divided into first sweep signal group SGL1-SGLk that offers a k bar grid line GL1-GLk who is used for liquid crystal panel 102 top A and second sweep signal group SGL (the k+1)-SGL2k that is used for the 2nd k bar grid line GL (k+1)-GL2k of liquid crystal panel 102 lower part B.The first sweep signal group SGL1-SGLk has its pulse grid high voltage VGH pulse identical with second sweep signal group SGL (k+1)-SGL2k with width.The pulse width of grid high voltage VGH is equivalent to two cycles of horizontal-drive signal.Along with the grid line GL on liquid crystal panel 102 top A moves down, the width of its body of pulse sequence ground translation of the grid high voltage VGH that comprises among the first sweep signal group SGL1-SGLk (for example, two of horizontal-drive signal cycles).Similarly, along with the grid line GL on liquid crystal panel 102 lower part B moves down, the width of its body of pulse sequence ground translation of the grid high voltage VGH that comprises among second sweep signal group SGL (k+1)-SGL2k (for example, two of horizontal-drive signal cycles).
The first data driver 106A response data control signal will convert analog data voltage to the R that is equivalent to delegation, G, B pixel data, and provide the upper data lines UDL1-UDLm that arranges to liquid crystal panel 102 top A with data line voltage.As long as it is one of any to enable the grid line GL1-GLk that arranges at liquid crystal panel 102 top A, first data driver 106A output data line voltage.The first data driver 106A provides two cycles that the cycle of data line voltage is equivalent to horizontal-drive signal and width to equal to enable the width of the grid high impulse of the grid line GL1-GLk that arranges on the A of the top of liquid crystal panel 102 to upper data lines UDL1-UDLm.
Similarly, the second data driver 106B will convert analog data voltage to the R that is equivalent to delegation, G, B pixel data in response to data controlling signal, and provide the lower data lines LDL1-LDLm that arranges to liquid crystal panel 102 lower part B with data line voltage.As long as it is one of any to enable grid line GL (k+1)-GL2k of arranging at liquid crystal panel 102 lower part B, the second data driver 106B just exports data line voltage.The second data driver 106B provides two cycles that the cycle of data line voltage is equivalent to horizontal-drive signal and width to equal to enable the width of the grid high impulse of the grid line GL1-GLk that arranges on the B of the lower part of liquid crystal panel 102 to lower data lines LDL1-LDLm.
Because grid line GL (k+1)-GL2k side by side is enabled with grid line GL1-GLk, so provide respectively and side by side to top data line UDL1-UDLm and lower data lines LDL1-LDLm from the data line voltage of the first data driver 106A with from the data line voltage of the second data driver 106B.Therefore, when the delegation's liquid crystal cells that is used for liquid crystal panel 102 top A charged into data voltage, the delegation's liquid crystal cells that is used for liquid crystal panel 102 lower part B charged into data voltage.That is to say that liquid crystal cells charges two cycles of data voltage horizontal-drive signal in the modes of each two row by the first and second data driver 106A and 106B and gate driver 104 on the liquid crystal panel 102.Therefore, the first subregion A1 of liquid crystal panel 102 top A and lower part B and the liquid crystal cells Clc on the B1 charge into data voltage simultaneously.Then, data voltage writes the second subregion A2 of liquid crystal panel 102 top A and lower part B and the liquid crystal cells Clc on the B2.Then, data voltage writes the 3rd subregion A3 of liquid crystal panel 102 top A and lower part B and the liquid crystal cells Clc on the B3 simultaneously.At last, data voltage writes the 4th subregion A4 of liquid crystal panel 102 top A and lower part B and the liquid crystal cells Clc on the B4 simultaneously.
When two cycles of one of the k bar grid line GL1-GLk of the pulse enable liquid crystal panel 102 top A by grid high voltage VGH horizontal-drive signal, be connected to the TFT conducting of the grid line after enabling, thereby transfer to corresponding liquid crystal unit Clc from the data voltage of upper data lines UDL.When sweep signal when grid high voltage VGH becomes grid low-voltage VGL, the TFT of conducting ends on liquid crystal panel 102 top A, thus liquid crystal cells Clc is not electrically connected with upper data lines UDL.In two cycles of horizontal-drive signal, i.e. TFT conduction period, the data voltage that is provided by upper data lines UDL is provided liquid crystal cells Clc.Then, the data voltage that charges into remains to TFT in the conducting once more of next frame cycle.
Similarly, when one of the 2nd k bar grid line GL (the k+1)-GL2k of the pulse enable liquid crystal panel 102 lower part B by grid high voltage VGH, be connected to the TFT conducting of the grid line after enabling, thereby transfer to corresponding liquid crystal unit Clc from the data voltage of lower data lines LDL.When sweep signal when grid high voltage VGH becomes grid low-voltage VGL, the TFT of conducting ends on liquid crystal panel 102 lower part B, thus liquid crystal cells Clc is not electrically connected with lower data lines UDL.In two cycles of horizontal-drive signal, i.e. TFT conduction period, the data voltage that is provided by lower data lines LDL is provided liquid crystal cells Clc.Then, the data voltage that charges into remains to TFT in the conducting once more of following frame period.
Jointly be connected to time schedule controller 108 back light unit 112 first to fourth lamp driver 115A to 115D sequentially the lamp 113A to 113D of opening and closing liquid crystal panel 102 top A subregion A1 to A4 with synchronous with the lamp 113E to 113H of liquid crystal panel 102 lower part B subregion B1 to B4.In each frame period, each lamp 113A to 113D opening and closing once.For example, the frame period is corresponding to the cycle of vertical synchronizing signal.For this reason, first to fourth lamp driver 115A to 115 control will offer the lamp driving voltage of lamp 113A to 113H.The duty factor of each lamp driving voltage (that is the ratio of opening time and shut-in time) can be different.Describe the work and the effect of first to fourth lamp driver 115 below in detail with reference to Fig. 9 B.
With reference to Fig. 9 B, waveform " DW113AE " expression is to the time cycle at the liquid crystal cells Clc write data voltage of the first subregion A1 of the top of liquid crystal panel 102 A and lower part B and B1, during DE113AE, in the liquid crystal cells Clc of the first subregion A1 of the top of liquid crystal panel 102 A and lower part B and B1 first 1/4 cycle in the frame period, it is the DWP cycle, charge into data voltage, and in all the other 3/4 cycles in frame period, keep these data that charge into.Waveform " DW113BF " expression is to the time cycle at the liquid crystal cells Clc write data voltage of the second subregion A2 of the top of liquid crystal panel 102 A and lower part B and B2, in the liquid crystal cells Clc of the second subregion A2 of the top of liquid crystal panel 102 A and lower part B and B2 second 1/4 cycle in the frame period, be the DWP cycle, charge into data voltage and in 1/4 cycle in all the other 1/2 cycles in this frame period and next frame cycle, keep these data that charge into.Waveform " DW113CG " expression is to the time cycle at the liquid crystal cells Clc write data voltage of the 3rd subregion A3 of the top of liquid crystal panel 102 A and lower part B and B3, in the liquid crystal cells Clc of the 3rd subregion A3 of the top of liquid crystal panel 102 A and lower part B and B3 the 3rd 1/4 cycle in the frame period, be the DWP cycle, charge into data voltage and in the one 1/2 cycle in all the other 1/4 cycles in this frame period and next frame cycle, keep these data that charge into.Waveform " DW113DH " expression is to the time cycle at the liquid crystal cells Clc write data voltage of the 4th subregion A4 of the top of liquid crystal panel 102 A and lower part B and B4, in the liquid crystal cells Clc of the 4th subregion A4 of the top of liquid crystal panel 102 A and lower part B and B4 the 4th 1/4 cycle in the frame period, be the DWP cycle, charge into data voltage and in 3/4 cycle in next frame cycle, keep these data that charge into.
The first lamp driving voltage LE113AE that the first lamp driver 115A provides Fig. 9 B to the first lamp 113A and the 5th lamp 113E of first subregion A1 that is used for liquid crystal panel 102 and B1 simultaneously.The first lamp driving voltage LE113AE that produces from the first lamp driver 115A has low level during the cycle DWP of the liquid crystal cells Clc on first subregion A1 that data voltage is write liquid crystal panel 102 and the B1, and on during the period L EP that the first subregion A1 and the liquid crystal cells Clc on the B1 of liquid crystal panel 102 keep data voltage high level is arranged.Can shorten the high level period LEP of the first lamp driving voltage LE113AE according to the brightness of the first subregion A1 of liquid crystal panel 102 and B1.Common response is closed in the cycle of the liquid crystal cells Clc charging data voltage of the first subregion A1 of liquid crystal panel 102 and B1 simultaneously by the first and the 5th lamp 113A of the first lamp driving voltage LE113AE of first lamp driver 115A output and 113E, and liquid crystal cells Clc keeps opening in cycle of the data voltage that charges on the first subregion A1 of liquid crystal panel 102 and B1, thereby to the first subregion A1 and the B1 irradiates light of liquid crystal panel 102.
The second lamp driving voltage LE113BF that the second lamp driver 115B provides Fig. 9 B to the second lamp 113B and the 6th lamp 113F of second subregion A2 that is used for liquid crystal panel 102 and B2 simultaneously.The second lamp driving voltage LE113BF that produces from the second lamp driver 115B has low level during the cycle DWP of the liquid crystal cells Clc on second subregion A2 that data voltage is write liquid crystal panel 102 and the B2, and has high level during the period L EP that the second subregion A2 and the liquid crystal cells Clc on the B2 of liquid crystal panel 102 keep data voltage.Can shorten the high level period LEP of the second lamp driving voltage LE113BF according to the brightness of the second subregion A2 of liquid crystal panel 102 and B2.Common response is closed in the cycle of the liquid crystal cells Clc charging data voltage of the second subregion A2 of liquid crystal panel 102 and B2 simultaneously by the second and the 6th lamp 113B of the second lamp driving voltage LE113BF of second lamp driver 115B output and 113F, and liquid crystal cells Clc keeps opening in cycle of the data voltage that charges on the second subregion A2 of liquid crystal panel 102 and B2, thereby to the second subregion A2 and the B2 irradiates light of liquid crystal panel 102.
The 3rd lamp driving voltage LE113CG that the 3rd lamp driver 115C provides Fig. 9 B to the 3rd lamp 113C and the 7th lamp 113G of the 3rd subregion A3 that is used for liquid crystal panel 102 and B3 simultaneously.The 3rd lamp driving voltage LE113CG that produces from the 3rd lamp driver 115C has low level during the cycle DWP of the liquid crystal cells Clc on the 3rd subregion A3 that data voltage is write liquid crystal panel 102 and the B3, and on during the period L EP that the 3rd subregion A3 and the liquid crystal cells Clc on the B3 of liquid crystal panel 102 keep data voltage high level is arranged.Can shorten the high level period LEP of the 3rd lamp driving voltage LE113CG according to the brightness of the 3rd subregion A3 of liquid crystal panel 102 and B3.Common response is closed in the cycle of the liquid crystal cells Clc charging data voltage of the 3rd subregion A3 of liquid crystal panel 102 and B3 simultaneously by the 3rd and the 7th lamp 113C of the 3rd lamp driving voltage LE113CG of the 3rd lamp driver 115C output and 113G, and liquid crystal cells Clc keeps opening in cycle of the data voltage that charges on the 3rd subregion A3 of liquid crystal panel 102 and B3, thereby to the 3rd subregion A3 and the B3 irradiates light of liquid crystal panel 102.
The 4th lamp driving voltage LE113DH that the 4th lamp driver 115D provides Fig. 9 B to the 4th lamp 113D and the 8th lamp 113H of the 4th regional A4 that is used for liquid crystal panel 102 and B4 simultaneously.The 4th lamp driving voltage LE113DH that produces from the 4th lamp driver 115D has low level during the cycle DWP of the liquid crystal cells Clc on the 4th subregion A4 that data voltage is write liquid crystal panel 102 and the B4, and on during the period L EP that the 4th subregion A4 and the liquid crystal cells Clc on the B4 of liquid crystal panel 102 keep data voltage high level is arranged.Can shorten the high level period LEP of the 4th lamp driving voltage LE113DH according to the brightness of the 4th subregion A4 of liquid crystal panel 102 and B4.Common response is closed in the cycle of the liquid crystal cells Clc charging data voltage of the 4th subregion A4 of liquid crystal panel 102 and B4 simultaneously by the 4th and the 8th lamp 113D of the 4th lamp driving voltage LE113DH of the 4th lamp driver 115D output and 113H, and liquid crystal cells Clc keeps opening in cycle of the data voltage that charges on the 4th subregion A4 of liquid crystal panel 102 and B4, thereby to the 4th subregion A4 and the B4 irradiates light of liquid crystal panel 102.
For driving liquid crystal panel 102 shown in Fig. 9 A and Fig. 9 B and lamp 113A to 113H, time schedule controller 108 provides grid-control system signal, provides data controlling signal to the first and second data driver 106A and 106B to gate driver 104, and provides the lamp control signal to first to fourth lamp driving governor 115A to 115D.In addition, time schedule controller 108 is allocated to two row pixel datas two cycles of the first and second data driver 106A and the lasting horizontal-drive signal of 106B.That is to say that in two cycles of horizontal synchronization week signal, time schedule controller 108 provides the one-row pixels data and provides the one-row pixels data to the second data driver 106B to the first data driver 106A.For this reason, the vertical/horizontal synchronizing signal (Vsync/Hsync), data enable signal (DE), clock signal and the video data that produce by external system (not shown) of time schedule controller 108 response such as the TV signal decoding module of the graphics card of computer system or television receiver.Time schedule controller 108 is used for the grid-control system signal of gate driver 104, the lamp control signal that is used for the data controlling signal of the first and second data driver 106A and 106B and is used for first to fourth lamp driver 115A to 115D by utilizing vertical/horizontal synchronizing signal (Vsync/Hsync), data enable signal (DE) and clock signal to produce.In addition, R, G that time schedule controller 108 will be provided by external system and B pixel data are arranged in R, G and B pixel data line by line, and in per two cycles of horizontal-drive signal the R of delegation, G and B pixel data are offered first and second data driver 106A and the 106B.Therefore, the first data driver 106A converts the R of delegation, G and B pixel data to analog data voltage in per two cycles of horizontal-drive signal.Offer upper data lines UDL1-UDLm simultaneously by the data line voltage after the first data driver 106A conversion.Synchronous with the first data driver 106A, the second data driver 106B converts the R of delegation, G and B pixel data to analog data voltage.Offer lower data lines LDL1-LDLm simultaneously by the data line voltage after the second data driver 106B conversion.
Shown in Fig. 9 B, first to fourth lamp driver 115A to 115D each frame period with the synchronous mode opening and closing sequentially of first to fourth 113A to 113D and the 5th to the 8th lamp 113E to 113H and the corresponding first to fourth lamp 113A to 113D of liquid crystal panel 102 top A and with corresponding the 5th to the 8th lamp 113E to 113H of liquid crystal panel 102 lower part B, the while, liquid crystal cells Clc write once simultaneously.Thereby alternately display video data and black level data are once on liquid crystal panel 102 in each frame period (for example 1/60 second) of the video data that is produced by external system.
Therefore, the LCD according to embodiment of the present invention can respond video data apace.Thereby, when showing moving image, can not move blooming.In addition, simultaneously the two parts to liquid crystal panel provide the charging data voltage also to prevent unsharp image or image retention, thus presentation video apace.
In addition, a plurality of lamps and a plurality of lamps that are used for liquid crystal panel 102 lower part subregions that are used for liquid crystal panel 102 top subregions by same lamp driver opening and closing.Therefore, can simplify the circuit that is used to drive lamp.
With reference to Figure 10 A, gate driver 104 sequentially enables once to be used for the grid line GL1-GLk of liquid crystal panel 102 top A in half of each frame period (for example, 1/60 second) of video data.Gate driver 104 sequentially enables once to be used for grid line GL (k+1)-GL2k of liquid crystal panel 102 lower part B synchronously to drive with grid line GL1-GLk.For example, gate driver 104 side by side enables the one-period of the first grid line GL1 and the lasting horizontal-drive signal of (k+1) bar grid line GL (k+1), side by side enable another cycle of the lasting horizontal-drive signal of the second grid line GL2 and (k+2) bar grid line GL (k+2), side by side enable the one-period again that the 3rd grid line GL3 and (k+3) bar grid line GL (k+3) continue horizontal-drive signal.In this way, k bar grid line GLk and 2k bar grid line GL2k side by side are enabled and continue last two cycles of horizontal-drive signal.That is to say that gate driver 104 is by driving k continues horizontal-drive signal to a k bar grid line GL1-GLk who is used for liquid crystal panel 102 top A and the 2nd k bar grid line GL (the k+1)-GL2k that is used for liquid crystal panel lower part B phase weekly over the ground.In addition, thus gate driver 104 does not enable any grid line for idle pulley in all the other field cycles in each frame period of video data.
For this reason, shown in Figure 10 A, gate driver 104 provides 2k sweep signal SGL1-SGL2k to 2k bar grid line GL1-GL2k respectively in each semiperiod of vertical synchronizing signal.2k sweep signal SGL1-SGL2k is divided into second sweep signal group SGL (k+1)-SGL2k of the 2nd k bar grid line GL (k+1)-GL2k of the first sweep signal group SGL1-SGLk of a k bar grid line GL1-GLk who offers liquid crystal panel 102 top A and liquid crystal panel 102 lower part B.The first sweep signal group SGL1-SGLk has its pulse grid high voltage VGH pulse identical with second sweep signal group SGL (k+1)-SGL2k with width.The pulse width of grid high voltage VGH is equivalent to the one-period of horizontal-drive signal.Along with the grid line GL on liquid crystal panel 102 top A moves down, the width of its body of pulse sequence ground translation of the grid high voltage VGH that comprises among the first sweep signal group SGL1-SGLk (for example, the one-period of horizontal-drive signal).Similarly, along with the grid line on liquid crystal panel 102 lower part B moves down, the width of its body of pulse sequence ground translation of the grid high voltage VGH that comprises among second sweep signal group SGL (k+1)-SGL2k (for example, the one-period of horizontal-drive signal).In addition, gate driver 104 keeps 2k sweep signal at grid low-voltage VGL in each cycle of vertical synchronizing signal, thereby does not carry out the operation of write data voltage.
Along with gate driver 104 sequentially enables the grid line GL1-GLk of liquid crystal panel 102 top A in each cycle of horizontal-drive signal, the first data driver 106A sequentially charges into data voltage to the liquid crystal cells Clc of liquid crystal panel 102 top A in line by line mode in semiperiod of vertical synchronizing signal.Then, the first data driver 106A is set to the sky pattern in the later half cycle of a vertical synchronizing signal.During the semiperiod of a vertical synchronizing signal,, upgrade the data line voltage that offers data line UDL1-UDLm by the first data driver 106A in each cycle of horizontal-drive signal promptly at the data voltage write cycle time.
Similarly, along with gate driver 104 sequentially enables grid line GL (k+1)-GL2k of liquid crystal panel 102 lower part B in each cycle of horizontal-drive signal, the second data driver 106B in semiperiod of vertical synchronizing signal to the liquid crystal cells Clc of liquid crystal panel 102 lower part B with the data voltage that sequentially charges of mode line by line.Then, the second data driver 106B is set to the sky pattern in the later half cycle of a vertical synchronizing signal.In each cycle of horizontal-drive signal, synchronously upgrade the data line voltage that offers data line LDL1-LDLm by the second data driver 106B with the data line voltage that provides by the first data driver 106A.
The first data driver 106A and 106B and gate driver 104 charge into data voltage in semiperiod of vertical synchronizing signal to the liquid crystal cells of the subregion of the liquid crystal cells of the subregion of liquid crystal panel 102 top A and liquid crystal panel 102 lower part B, thereby they are synchronized with each other respectively.For example, the liquid crystal cells of the subregion A1 of liquid crystal panel 102 top A and at the liquid crystal cells of the subregion B1 of liquid crystal panel 102 lower part B at the one 1/8 cycle DWP of vertical synchronizing signal charging data voltage, and keep the data voltage that charges in all the other 7/8 cycles of a vertical synchronizing signal.The liquid crystal cells of the subregion A2 of liquid crystal panel 102 top A and at the liquid crystal cells of the subregion B2 of liquid crystal panel 102 lower part B at the 2 1/8 cycle DWP of vertical synchronizing signal charging data voltage, and keep the data voltage that charges in the one 1/8 cycle of all the other 6/8 cycles of a vertical synchronizing signal and next vertical synchronizing signal.The liquid crystal cells of the subregion A3 of liquid crystal panel 102 top A and at the liquid crystal cells of the subregion B3 of liquid crystal panel 102 lower part B at the 3 1/8 cycle DWP of vertical synchronizing signal charging data voltage, and keep the data voltage that charges in the one 1/4 cycle of all the other 5/8 cycles of a vertical synchronizing signal and next vertical synchronizing signal.The liquid crystal cells of the subregion A4 of liquid crystal panel 102 top A and at the liquid crystal cells of the subregion B4 of liquid crystal panel 102 lower part B at the 4 1/8 cycle DWP of vertical synchronizing signal charging data voltage, and keep the data voltage that charges in 3/8 cycle of all the other 1/2 cycles of a vertical synchronizing signal and next vertical synchronizing signal.
First to fourth lamp driver 115A to 115D of the back light unit of jointly being controlled by time schedule controller 108 112 is each frame period opening and closing lamp 113A to 113H sequentially in each cycle of vertical synchronizing signal.In each frame period, lamp 113A to 113H each all opening and closing are once.Open after the saturated period expires of the orientation of subregion 113E-113H after liquid crystal cells charges into data voltage of the lamp 113A-113D of subregion A1-A4 and subregion B1-B4.Therefore, the lamp driving voltage that offers corresponding lamp 113A to 113H by first to fourth lamp driver 115A to 115D can be orientated saturated period expires after the data voltage write cycle time finishes effective afterwards the time, and invalid to the subregion write data voltage of liquid crystal panel 102 time.Remove the data write cycle of subregion in the cycle that is adjusted in a vertical synchronizing signal effective period of the lamp driving voltage that will produce by lamp driver 115A to 115D and be orientated in cycle the saturated cycle.Illustrate that with reference to Figure 10 B first to fourth lamp 115A to 115D produces the work and the influence of above-mentioned lamp driving voltage below.
With reference to Figure 10 B, waveform " DW113AE " expression is to the time cycle at the liquid crystal cells Clc write data voltage of the first subregion A1 of the top of liquid crystal panel 102 A and lower part B and B1.Waveform " LE113AE " the expression first lamp driver 115A exports the effective time cycle of the first lamp drive signal.According to time cycle DW113AE and LE113AE, comprising the semiperiod that data voltage is filled into the vertical synchronizing signal of the one 1/8 cycle DWP of vertical synchronizing signal of liquid crystal cells Clc of the first subregion A1 of liquid crystal panel 102 and B1 and the orientation saturated cycle ASP corresponding, having low level from the first lamp driving voltage LE113AE of the first lamp driver 115A with 3/8 cycle of vertical synchronizing signal.On the other hand, in cycle (rayed period L EP) the saturated cycle ASP of orientation that the first subregion A1 and the liquid crystal cells Clc among the B1 of liquid crystal panel 102 keep rearranging by the direction of orientation that is equivalent to data voltage except that liquid crystal molecule in the cycle (ASP_LEP) of data voltage, the first lamp driving voltage LE113AE has high level.Rayed period L EP is corresponding to the semiperiod of a vertical synchronizing signal, and can shorten according to first subregion A1 of liquid crystal panel 102 and the brightness value of B1.When shortening rayed period L EP, be orientated saturated cycle ASP and prolong, its prolongation value is the same big with rayed period L EP minimizing value.After the liquid crystal cells Clc of first subregion A1 that data voltage is write or fills into liquid crystal panel 102 and B1, in the semiperiod corresponding to the vertical synchronizing signal of the saturated cycle ASP of the orientation in 3/8 cycle of vertical synchronizing signal in the past, the common response of the first lamp 113A and the 5th lamp 113E is opened simultaneously from the first lamp driving voltage LE113AE of first lamp driver 115A output.Therefore, illumination is mapped on the first subregion A1 and B1 of liquid crystal panel 102.Because the first subregion A1 of liquid crystal panel 102 and the liquid crystal cells Clc on the B1 by and arrange back first lamp 113A and the 5th lamp 113E irradiates light corresponding to a direction of data voltage, so correct display pixel data.In addition, in the first lamp 113A and the 5th lamp 113E down periods, on the first subregion A1 of liquid crystal panel 102 and B1, show the black level data.Therefore, false pulse shows and has the greatest impact on the first subregion A1 of liquid crystal panel 102 and B1.
In Figure 10 B, waveform " DW113BF " expression is to the time cycle at the liquid crystal cells Clc write data voltage of the second subregion A2 of the top of liquid crystal panel 102 A and lower part B and B2.The effective time cycle of the second lamp drive signal of waveform " LE113BF " expression second lamp driver 115B output.According to time cycle DW113BF and LE113BF, comprise with data voltage fill into the second subregion A2 of liquid crystal panel 102 and B2 liquid crystal cells Clc vertical synchronizing signal the 2 1/8 cycle DWP and corresponding to the half period of the vertical synchronizing signal of the saturated cycle ASP of orientation in 3/8 cycle of vertical synchronizing signal, have low level from the second lamp driving voltage LE113BF of the second lamp driver 115B.On the other hand, in cycle (rayed period L EP) the saturated cycle ASP of orientation that the second subregion A2 and the liquid crystal cells Clc among the B2 of liquid crystal panel 102 keep rearranging by the direction of orientation that is equivalent to data voltage except that liquid crystal molecule in the cycle (ASP_LEP) of data voltage, the second lamp driving voltage LE113BF has high level.Rayed period L EP is corresponding to the semiperiod of a vertical synchronizing signal, and can shorten according to second subregion A2 of liquid crystal panel 102 and the brightness value of B2.When rayed period L EP is shortened, be orientated saturated cycle ASP and prolong, it is the same big that its prolongation value and rayed period L EP reduce value.In the semiperiod corresponding to the vertical synchronizing signal of the saturated cycle ASP of the orientation in 3/8 cycle of vertical synchronizing signal in the past, the common response of the second lamp 113B and the 6th lamp 113F is opened simultaneously from the second lamp driving voltage LE113BF that second lamp drives 115B output after the liquid crystal cells Clc of second subregion A2 that data voltage is write or fills into liquid crystal panel 102 and B2.Therefore, illumination is mapped on the second subregion A2 and B2 of liquid crystal panel 102.Because the second subregion A2 of liquid crystal panel 102 and the liquid crystal cells Clc on the B2 by and arrange back second lamp 113B and the 6th lamp 113F irradiates light corresponding to a direction of data voltage, so display pixel data correctly.In addition, when the second lamp 113B and the 6th lamp 113F down periods, on the second subregion A2 of liquid crystal panel 102 and B2, show the black level data.Therefore, false pulse shows and has the greatest impact on the second subregion A2 of liquid crystal panel 102 and B2.
In Figure 10 B, waveform " DW113CG " expression is to the time cycle at the liquid crystal cells Clc write data voltage of the 3rd subregion A3 of the top of liquid crystal panel 102 A and lower part B and B3.Waveform " LE113CG " expression the 3rd lamp drives the effective time cycle of the 3rd lamp drive signal of 115C output.According to time cycle DW113CG and LE113CG, comprise with data voltage fill into the 3rd subregion A3 of liquid crystal panel 102 and B3 liquid crystal cells Clc vertical synchronizing signal the 3 1/8 cycle DWP and corresponding to semiperiod of the vertical synchronizing signal of the saturated cycle ASP of orientation in 3/8 cycle of vertical synchronizing signal, have low level from the 3rd lamp driving voltage LE113CG of the 3rd lamp driver 115C.On the other hand, in cycle (rayed period L EP) the saturated cycle ASP of orientation that the 3rd subregion A3 and the liquid crystal cells Clc among the B3 of liquid crystal panel 102 keep rearranging by the direction of orientation that is equivalent to data voltage except that liquid crystal molecule in the cycle (ASP_LEP) of data voltage, the 3rd lamp driving voltage LE113CG has high level.The semiperiod of a rayed period L EP correspondence and a vertical synchronizing signal, and can shorten according to the 3rd subregion A3 of liquid crystal panel 102 and the brightness value of B3.When shortening rayed period L EP, be orientated saturated cycle ASP and prolong, it is the same big that its prolongation value and rayed period L EP reduce value.From corresponding to the vertical synchronizing signal of the saturated cycle ASP of the orientation in 3/8 cycle of vertical synchronizing signal in the past in the semiperiod, the 3rd lamp driving voltage LE113CG that the 3rd lamp 113C and the 7th lamp 113G respond the 3rd lamp driver 115C output altogether opens simultaneously after the liquid crystal cells Clc of the 3rd subregion A3 that data voltage is write or fills into liquid crystal panel 102 and B3.Therefore, illumination is mapped on the 3rd subregion A3 and B3 of liquid crystal panel 102.Because the 3rd subregion A3 of liquid crystal panel 102 and the liquid crystal cells Clc on the B3 by and arrange back the 3rd lamp 113C and the 7th lamp 113G irradiates light corresponding to a direction of data voltage, so correct display pixel data.In addition, when the 3rd lamp 113C and the 7th lamp 113G down periods, on the 3rd subregion A3 of liquid crystal panel 102 and B3, show the black level data.Therefore, false pulse shows and has the greatest impact on the 3rd subregion A3 of liquid crystal panel 102 and B3.
In Figure 10 B, waveform " DW113DH " expression is to the time cycle at the liquid crystal cells Clc write data voltage of the 4th subregion A4 of the top of liquid crystal panel 102 A and lower part B and B4.The effective time cycle of the 4th lamp drive signal of waveform " LE113DH " expression the 4th lamp driver 115D output.According to time cycle DW113DH and LE113, at the 4 1/8 cycle DWP of the vertical synchronizing signal of the liquid crystal cells Clc that comprises the 4th subregion A4 that data voltage filled into liquid crystal panel 102 and B4 with in the semiperiod corresponding to the vertical synchronizing signal of the saturated cycle ASP of orientation in 3/8 cycle of vertical synchronizing signal, has low level from the 4th lamp driving voltage LE113DH of the 4th lamp driver 115D.On the other hand, in cycle (rayed period L EP) the saturated cycle ASP of orientation that the 4th subregion A4 and the liquid crystal cells Clc among the B4 of liquid crystal panel 102 keep rearranging by the direction of orientation that is equivalent to data voltage except that liquid crystal molecule in the cycle (ASP_LEP) of data voltage, the 4th lamp driving voltage LE113DH has high level.Rayed period L EP is corresponding to the semiperiod of a vertical synchronizing signal, and can shorten according to the 4th subregion A4 of liquid crystal panel 102 and the brightness value of B4.When shortening rayed period L EP, be orientated saturated cycle ASP and prolong, it is the same big that its prolongation value and rayed period L EP reduce value.From corresponding to half vertical synchronizing signal of the saturated cycle ASP of the orientation in 3/8 cycle of vertical synchronizing signal in the past in the cycle, the 4th lamp 113D and the 8th lamp 113H response are opened simultaneously from the 4th lamp driving voltage LE113DH of the 4th lamp driver 115D output after the liquid crystal cells Clc of the 4th subregion A4 that data voltage is write or fills into liquid crystal panel 102 and B4.Therefore, illumination is mapped on the 4th subregion A4 and B4 of liquid crystal panel 102.Because arrange back the 4th lamp 113D and the 8th lamp 113H irradiates light by a direction, so correct display pixel data corresponding to data voltage at the 4th subregion A4 of liquid crystal panel 102 and the liquid crystal cells Clc on the B4.In addition, in the 4th lamp 113D and the 8th lamp 113H down periods, on the 4th subregion A4 of liquid crystal panel 102 and B4, show the black level data.Therefore, false pulse shows and has the greatest impact on the 4th subregion A4 of liquid crystal panel 102 and B4.
Shown in Figure 10 A and 10B, the time schedule controller 108 control gate drivers 104 and first and second data driver 106A and the 106B, thus data voltage is write on the liquid crystal cells of liquid crystal panel 102 in the cycle at field.Simultaneously, by the control of time schedule controller 108, lamp driver drives lamp 113A to 113H, and each opening and closing sequentially are once in each frame period.For this reason, time schedule controller 108 provides grid-control system signal to gate driver 104, provides data controlling signal to the first and second data driver 106A and 106B, and provides the lamp control signal to first to fourth lamp driver 115A to 115D.In addition, time schedule controller 108 provides two capable pixel datas for the first and second data driver 106A and 106B in the one-period of a horizontal-drive signal.That is to say that in the cycle, time schedule controller 108 provides the one-row pixels data to the first data driver 106A in a horizontal-drive signal, and provides the one-row pixels data to the second data driver 106B.For this reason, the vertical/horizontal synchronizing signal (Vsync/Hsync), data enable signal (DE), clock signal and the video data that produce by external system (not shown) of time schedule controller 108 response such as the TV signal decoding module of the graphics card of computer system or television receiver.Time schedule controller 108 is used for the grid-control system signal of gate driver 104, the lamp control signal that is used for the data controlling signal of the first and second data driver 106A and 106B and is used for first to fourth lamp driver 113A to 113D by utilizing vertical/horizontal synchronizing signal (Vsync/Hsync), data enable signal (DE) and clock signal to produce.In addition, R, G that time schedule controller 108 will be provided by external system and B pixel data are arranged in R, G and B pixel data line by line, and in each cycle of horizontal-drive signal the R of delegation, G and B pixel data are offered first and second data driver 106A and the 106B.
Therefore, the first data driver 106A converts the R of delegation, G and B pixel data to analog data voltage in each cycle of horizontal-drive signal.Offer upper data lines UDL1-UDLm simultaneously by the data line voltage after the first data driver 106A conversion.Synchronous with the first data driver 106A, the second data driver 106B converts the R of delegation, G and B pixel data to analog data voltage.Offer lower data lines LDL1-LDLm simultaneously by the data line voltage after the second data driver 106B conversion.Shown in Figure 10 B, on the subregion A1 to A4 that writes liquid crystal panel 102 from data voltage the saturated cycle ASP of back orientation in the past after in the time of the subregion A1 to A4 that begins data voltage is write liquid crystal panel 102, the first to fourth lamp driver 115A to 115D that is controlled by time schedule controller 108 opens first to fourth lamp 113A to 113D.In addition, first to fourth lamp driver 115A to 115D with synchronous mode opening and closing the 5th to the 8th lamp 113E to 113H of (simultaneously) of first to fourth lamp 113A to 113D.Therefore, from the saturated cycle ASP of orientation behind the subregion B1 to B4 that data voltage is write liquid crystal panel 102 in the past after in the time of the subregion B1 to B4 that begins data voltage is write liquid crystal panel 102, the 5th to the 8th lamp 113E to 113H opens.
After data voltage being write liquid crystal molecule behind the lamp 113A to 113H and being arranged by a direction corresponding with data voltage, time schedule controller 108 controls first to fourth lamp driver is mapped on the subregion of liquid crystal panel 102 illumination.Therefore, when lamp 113A to 113H opened, liquid crystal panel 102 correctly showed and the corresponding image of video data (data voltage) on subregion.On the other hand, when lamp 113A to 113H closes, with the corresponding subregion of lamp 113A to 113H on show the black level data.
Like this and since in every frame lamp 113A and each opening and closing of 113H once, the black level image and with the corresponding image of video data each correctly shows once, thereby it is minimum to make false pulse drive influence.Therefore, the LCD according to embodiment of the present invention can respond video data fast.In addition, when showing moving image, can not move blooming.In addition, also may prevent unsharp image or image retention.Therefore, the LCD according to embodiment of the present invention can show high quality graphic.
In addition, a plurality of lamps and a plurality of lamps that are used for liquid crystal panel lower part subregion that are used for liquid crystal panel top subregion by same lamp driver opening and closing.Therefore, can simplify the circuit that is used to drive lamp.
Thereby video data and black level data alternately show twice on liquid crystal panel 102 with the frame rate (for example second frame rate 120Hz) of the twice of the frame rate (for example, the first frame rate 60Hz) of the video data that produced by external system.Therefore, the LCD according to embodiment of the present invention can respond video data apace.Thereby, when showing moving image, can not move blooming.In addition,, can also prevent unsharp image or image retention owing to provide the charging data voltage simultaneously to two parts of liquid crystal panel, thus presentation video apace.
In addition, a plurality of lamps and a plurality of lamps that are used for liquid crystal panel lower part subregion that are used for liquid crystal panel top subregion by same lamp driver opening and closing.Therefore, can simplify the circuit that is used to drive lamp.
As mentioned above, in LCD and driving method thereof according to the embodiment of the present invention, alternately display video data and black level data are at least once with the frame rate (for example second frame rate 120Hz) of the twice of the frame rate (for example, the first frame rate 60Hz) of the video data that produced by external system on liquid crystal panel.Therefore, the LCD according to embodiment of the present invention can respond video data apace.Thereby, when showing moving image, can not move blooming.In addition, in per frame period on liquid crystal panel alternately display video data and black level data can also prevent not fogging clear or image retention, can show the ground display image thereby brightness is reduced fast minimum the time.
In addition, a plurality of lamps and a plurality of lamps that are used for liquid crystal panel lower part subregion that are used for liquid crystal panel top subregion by same lamp driver opening and closing.Therefore, can simplify the circuit that is used to drive lamp.
Obviously, those skilled in the art can carry out different modifications and improvement to the present invention.Therefore, the present invention is intended to comprise that all fall into modification and improvement that the present invention is carried out in claims and the equivalent scope thereof.

Claims (16)

1, a kind of liquid crystal display device comprises:
Liquid crystal panel, has grid line, described grid line comprises with data line and is taking second grid line that intersects on the 4th zone of first area remainder and second area remainder at first grid line that intersects on the 3rd zone that takies part first area and part second area with data line, wherein said first area is the top of described liquid crystal panel, and described second area is the lower part of described liquid crystal panel;
Back light unit has and comprises and be used for subregion in the first lamp group of at least two lamps of irradiates light on the described first area of liquid crystal panel with comprise the second lamp group that is used at least two lamps of irradiates light on the described second area of subregion at liquid crystal panel; And
Driver, be used for according to video data driven grid line with first frame rate and data line and be used to control the first lamp group and the second lamp group is driven simultaneously being higher than under second frame rate of first frame rate, thereby the lamp of the lamp of the first lamp group and the second lamp group is synchronously by the order opening and closing.
2, liquid crystal display device according to claim 1 is characterized in that, described driver comprises:
Gate driver is used for driven grid line;
Data driver is used for driving data lines,
Wherein said driver also comprises time schedule controller, and in response to the video data with first frame rate, the lamp that is used for control gate driver and data driver and enables the first and second lamp groups is with synchronously with one another by the order opening and closing.
3, liquid crystal display device according to claim 2, it is characterized in that, described back light unit comprises at least two lamp drivers, and described at least two lamp drivers are by time schedule controller control and produce the lamp that is used to enable the first and second lamp groups with synchronously with one another by the lamp driving voltage of order opening and closing.
4, liquid crystal display device according to claim 3 is characterized in that, lamp driving voltage has different duty factors.
5, liquid crystal display device according to claim 1 is characterized in that, second frame rate is the twice of first frame rate at least.
6, liquid crystal display device according to claim 1 is characterized in that, described driver comprises:
First grid driver is used to drive first grid line;
Second gate driver is used for driving second grid line with first grid line locking ground; With
Data driver is used for driving data lines,
Wherein said driver also comprises time schedule controller, in response to the video data with first frame rate, is used to the lamp controlling first and second gate drivers and data driver and enable the first and second lamp groups with synchronously with one another by the order opening and closing.
7, liquid crystal display device according to claim 6, it is characterized in that, described back light unit comprises at least two lamp drivers, and described at least two lamp drivers are by time schedule controller control and produce the lamp driving voltage of lamp to be driven in proper order synchronously with one another that is used to enable the first and second lamp groups.
8, liquid crystal display device according to claim 7 is characterized in that, lamp driving voltage has different duty factors.
9, liquid crystal display device according to claim 1 is characterized in that, second frame rate is the twice of first frame rate at least.
10, a kind of liquid crystal display device comprises:
Liquid crystal panel has grid line intersected with each other and data line;
Back light unit has and comprises and be used for respectively in the first lamp group of at least two lamps of irradiates light on the subregion of the first area of liquid crystal panel and comprise the second lamp group that is used for respectively at least two lamps of irradiates light on the subregion of the second area of liquid crystal panel; And
Driver, be used for driven grid line and data line the data voltage with video data of first frame rate is write in proper order the liquid crystal cells of liquid crystal panel at each frame in mode line by line, and be used to control the first and second lamp groups and be driven simultaneously being higher than under second frame rate of first frame rate, thereby at least two lamps of at least two lamps of the first lamp group and the second lamp group are opened in proper order or are closed synchronously with one another.
11, liquid crystal display device according to claim 10 is characterized in that, described driver comprises:
Gate driver is used in each frame sequential ground driven grid line;
Data driver is used for driving data lines; And
Time schedule controller, in response to video data, the lamp that is used for control gate driver and data driver and enables the first and second lamp groups is with synchronously with one another by the order opening and closing.
12, liquid crystal display device according to claim 11, it is characterized in that, described back light unit comprises at least two lamp drivers, and described at least two lamp drivers are by time schedule controller control and produce the lamp driving voltage of lamp to be driven in proper order synchronously with one another that is used to enable the first and second lamp groups.
13, liquid crystal display device according to claim 11 is characterized in that, lamp driving voltage has different duty factors.
14, a kind of driving method of liquid crystal display device, this liquid crystal display device have grid line and data line liquid crystal panel intersected with each other, and described method comprises:
According to video data driven grid line and data line with first frame rate; And
Control the first and second lamp groups with second frame rate that is higher than first frame rate by the while opening and closing, the first lamp group has at least two lamps of the first area that is used for liquid crystal panel and at least two lamps that the second lamp group has the second area that is used for liquid crystal panel.
15, method according to claim 14 is characterized in that, second frame rate is the twice of first frame rate at least.
16, method according to claim 14 is characterized in that, described grid line comprises:
First grid line intersects in the 3rd zone that takies part first and second zones with data line; And
Second grid line intersects in the 4th zone that takies the first and second regional remainders with data line.
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