CN1988175A - Super high voltage metal oxide semiconductor transistor tube element and its producing method - Google Patents
Super high voltage metal oxide semiconductor transistor tube element and its producing method Download PDFInfo
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- CN1988175A CN1988175A CN200510022959.6A CN200510022959A CN1988175A CN 1988175 A CN1988175 A CN 1988175A CN 200510022959 A CN200510022959 A CN 200510022959A CN 1988175 A CN1988175 A CN 1988175A
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- 239000004065 semiconductor Substances 0.000 title claims description 48
- 238000000034 method Methods 0.000 title claims description 23
- 229910044991 metal oxide Inorganic materials 0.000 title description 2
- 150000004706 metal oxides Chemical class 0.000 title description 2
- 238000002955 isolation Methods 0.000 claims abstract description 58
- 239000000463 material Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims description 45
- 239000011800 void material Substances 0.000 claims description 32
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 description 32
- 230000005684 electric field Effects 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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Abstract
This invention discloses a kind of super-high voltage MOS transistor elements including a grid extending to a first dielectric layer with a cavity under the edge of the grid and a second dielectric layer covering the grid and the first dielectric layer and maintaining the cavity, in which, the first dielectric layer can be a field oxidation layer or a shallow groove isolation region and further having a thickened dielectric layer above the field oxidation layer and the shallow groove isolation region, and the thickened dielectric layer can be a material of low dielectric coefficient, or the shallow groove isolation region can be filled with porous oxide material without any cavity, and the grid edge of the MOS transistor element has rather low vertical field.
Description
Technical Field
The present invention relates to a semiconductor ultra high voltage device, and more particularly, to an ultra high voltage MOS transistor device capable of reducing a vertical electric field caused by a gate edge.
Background
High-voltage metal-oxide-semiconductor (HVMOS) transistors have been widely used in CPU Power Supplies (CPUs), power management systems (power management systems), and DC/AC converters (AC/DC converters).
Referring to fig. 1, a cross-sectional view of a conventional ultra high voltage NMOS transistor device is shown. The conventional ultra high voltage NMOS transistor device 1 is fabricated on a semiconductor substrate 10, such as a P-type silicon substrate, and is isolated by a field oxide layer 44. Generally, the conventional uhp NMOS transistor device 1 includes a source 14, a gate 50 and a drain 24, wherein the source 14 is a heavily doped N-type region adjacent to a heavily doped P-type region 16, and the heavily doped N-type region (source) 14 and the heavily doped P-type region 16 are both disposed in a P-well 12. The drain 24 and the source 14 may be spaced apart by more than a few microns, wherein the drain 24 is a heavily doped N-well 22 disposed in an N-well 22, and the N-well 22 is disposed in a deep N-well 30, thereby forming a triple gradient well structure.
As shown in fig. 1, a gate dielectric layer 46 is formed on the source 14, and a gate 50 is disposed on the gate dielectric layer 46 and extends over a field oxide layer 42. The field oxide layer 42 is formed by local oxidation of silicon (LOCOS), which is interposed between the source 14 and the drain 24. To operate in the ultra-high voltage range, such as hundreds of volts or even thousands of volts, the thickness of the field oxide layer 42 needs to be at least 10,000 angstroms (angstrom) or more to reduce the ultra-high vertical field effect caused by the edge 52 of the gate 50. However, the field oxide layer 42 with such a thickness is not easy to be formed, which not only consumes more time in the furnace to reduce the productivity, but also has a large step height (step height) to be disadvantageous for the subsequent process.
Therefore, there is still a need for a HV MOS structure and a method of fabricating the same that can reduce the vertical electric field effect well.
Disclosure of Invention
The present invention is directed to an ultra high voltage MOS transistor device that reduces the vertical electric field caused by the gate edge.
The ultra-high voltage MOS transistor device comprises a semiconductor substrate; at least one doped region located on the semiconductor substrate; a gate electrode on the semiconductor substrate; a first dielectric layer located between the gate and the doped region for isolation, the gate extending onto the first dielectric layer, the first dielectric layer having at least one void located below the edge of the gate; and a second dielectric layer covering the gate, the doped region and the first dielectric layer, and leaving a void.
According to one embodiment of the present invention, the ultra high voltage MOS transistor device comprises a substrate having a first conductivity, a source doped region having a second conductivity and disposed in the substrate, a first doped region having the first conductivity and disposed in the substrate and adjacent to the source doped region, a first ion well having the first conductivity and surrounding the source doped region and the first doped region, a gate dielectric layer formed over the source doped region and the first ion well, a first dielectric layer formed over the semiconductor region and abutting the gate dielectric layer, a drain doped region having the second conductivity and disposed on a side of the first dielectric layer remote from the source doped region, a second ion well having the second conductivity and surrounding the drain doped region, a gate disposed over the gate dielectric layer and extending onto the first dielectric layer, the first dielectric layer having a void located under an edge of the gate, and a second dielectric layer covering the gate, the gate dielectric layer, and the first dielectric layer, and leaving the void.
In yet another embodiment of the present invention, the ultra high voltage MOS transistor device according to the present invention is as described above, but the first dielectric layer is replaced by a porous oxide material and may not have voids.
In yet another embodiment of the present invention, the ultra high voltage MOS transistor device according to the present invention is as described above, but the first dielectric layer is replaced by a low dielectric constant layer and a field oxide layer, and may not have a void.
A method for fabricating an ultra high voltage MOS transistor device according to another embodiment of the present invention comprises the following steps. First, a substrate with a first conductivity is provided, and a first ion well and a second ion well with the first conductivity and a second conductivity are respectively formed. Forming a first doped region with a first conductivity in the first ion well, and forming a source doped region and a drain doped region in the first ion well and the second ion well, respectively, wherein the source doped region has a second conductivity and is adjacent to the first doped region, so that the first ion well surrounds the source doped region and the first doped region, and the drain doped region has a second conductivity. Then, a grid dielectric layer is formed on the source electrode doped region and the first ion well, a first dielectric layer is formed on a semiconductor region and is connected with the grid dielectric layer, the drain electrode doped region is far away from the source electrode doped region, and the first dielectric layer is arranged between the drain electrode doped region and the source electrode doped region. Then, a grid is formed on the grid dielectric layer and extends to the first dielectric layer, and the part of the first dielectric layer under the edge of the grid is removed, so that a hollow hole is formed. Finally, a second dielectric layer is formed on the grid, the grid dielectric layer and the first dielectric layer, and the hollow is reserved.
A method for fabricating an ultra high voltage MOS transistor device according to another embodiment of the present invention comprises the following steps. First, a substrate with a first conductivity is provided, and a first ion well and a second ion well with the first conductivity and a second conductivity are respectively formed. Forming a first doped region with a first conductivity in the first ion well, and forming a source doped region and a drain doped region in the first ion well and the second ion well, respectively, wherein the source doped region has a second conductivity and is adjacent to the first doped region, so that the first ion well surrounds the source doped region and the first doped region, and the drain doped region has a second conductivity. Then, a grid dielectric layer is formed on the source electrode doped region and the first ion well, a field oxide layer is formed on a semiconductor region, a low dielectric coefficient material layer is formed on the field oxide layer, the drain electrode doped region is far away from the source electrode doped region, and the field oxide layer is positioned between the drain electrode doped region and the source electrode doped region. Then, a gate is formed on the gate dielectric layer and extends to the low-k material layer. Finally, a dielectric layer is formed on the grid, the grid dielectric layer and the low dielectric coefficient material layer.
A method for fabricating an ultra high voltage MOS transistor device according to another embodiment of the present invention comprises the following steps. First, a substrate with a first conductivity is provided, and a first ion well and a second ion well with the first conductivity and a second conductivity are respectively formed. Forming a first doped region with a first conductivity in the first ion well, and forming a source doped region and a drain doped region in the first ion well and the second ion well, respectively, wherein the source doped region has a second conductivity and is adjacent to the first doped region, so that the first ion well surrounds the source doped region and the first doped region, and the drain doped region has a second conductivity. Then, a grid dielectric layer is formed on the source electrode doped region and the first ion well, a shallow groove isolation region is formed on a semiconductor region and is connected with the grid dielectric layer, wherein the shallow groove isolation region is filled with porous oxide materials, and the drain electrode doped region is far away from the source electrode doped region and is arranged between the source electrode doped region and the shallow groove isolation region. Then, a gate is formed on the gate dielectric layer and extends to the shallow trench isolation region. Finally, a dielectric layer is formed on the grid, the grid dielectric layer and the shallow groove isolation region.
According to the ultra-high voltage MOS transistor device of the present invention, a void is formed under the gate edge (also called field plate edge) to reduce the electric field, or the dielectric layer under the gate edge comprises a low dielectric coefficient material to reduce the electric field, so that it is not necessary to pad a thick oxide layer under the gate edge to reduce the electric field, and thus the problems of difficult manufacturing of the thick oxide layer and step height are not caused.
Drawings
FIG. 1 is a schematic cross-sectional view of a conventional extra-high voltage NMOS transistor device;
FIG. 2 is a schematic cross-sectional view of an extra-high voltage NMOS device according to the present invention;
FIG. 3 is a schematic cross-sectional view of an extra-high voltage NMOS device according to another embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of an extra-high voltage NMOS device according to yet another embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of an extra-high voltage NMOS device according to yet another embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of an extra-high voltage NMOS device according to yet another embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view of an extra-high voltage NMOS device according to yet another embodiment of the present invention;
FIGS. 8 to 9 are schematic cross-sectional views illustrating the process of fabricating an extra-high voltage MOS transistor device according to the present invention;
FIG. 1O is a schematic cross-sectional view of an extra-high voltage MOS transistor device according to the present invention.
Description of the main elements
1 existing ultra-high voltage NMOS transistor element 10 semiconductor substrate
16 high concentration P-type doped region 22N-type well
24 drain 30 deep N-well
42 field oxide 44 field oxide
46 gate dielectric layer 50 gate
52 edge 54 hollow
56 dielectric layer 58 thickening oxide layer
60 opening 70 semiconductor substrate
72 source/drain 74 gate
76 dielectric layer 78 void
80 dielectric layer 82 Gate dielectric layer
100. 200, 300, 400, 500, 600, 700 ultra high voltage NMOS transistor element
142 field oxide layer
458 thickened oxide layer
342. 344, 642 shallow trench isolation region
Detailed Description
Referring to fig. 10, a cross-sectional view of the ultra high voltage MOS device of the present invention is shown. The ultra high voltage NMOS transistor device 700 is fabricated on a semiconductor substrate 70 and includes at least one doped region, such as but not limited to source/drain 72, and a gate 74. A dielectric layer 76 is disposed between the gate 74 and the source/drain 72, and the gate 74 extends to the dielectric layer 76. The dielectric layer 76 has a void 78 beneath the edge of the gate 74. Another dielectric layer 80 covers source/drains 72, gates 74, and dielectric layer 76, but leaves voids 78.
"at least one doped region" means that there can be more than one doped region, such as one source and the other drain, located on both sides of the gate. The gate is isolated from the source or drain by a dielectric layer, which may have voids below the edge of either end of the gate, for example, the dielectric layer below the edge of the end of the gate directed toward the drain may have voids, the dielectric layer below the edge of the end directed toward the source may have voids, or both.
The uhp NMOS transistor device 700 may further have a gate dielectric layer 82 between the gate 74 and the semiconductor substrate 70. Dielectric layer 76 may be in the form of a field oxide or shallow trench isolation region, for example. The method may further include stacking a thickened dielectric layer on the field oxide layer or the shallow trench isolation region, in which case the void may be located only at the thickened dielectric layer, or at both the thickened dielectric layer and the field oxide layer or the shallow trench isolation region. The voids may be further filled with a low-k material. The dielectric layer structure with voids can also be replaced by a shallow trench isolation region structure filled with porous oxide or a stacked structure of low-k material layer and field oxide layer, and can have no voids.
The present invention is applicable to, for example but not limited to: vertical-diffusion metal-oxide-semiconductor (VDMOS), Insulated Gate Bipolar Transistor (IGBT), lateral-diffusion metal-oxide-semiconductor (LDMOS), and the like are high-voltage devices fabricated in a chip. It can also be used in Double Diffused Drain (DDD) structure.
The invention is illustrated in more detail by the following examples. Referring to fig. 2, a cross-sectional view of the ultra high voltage NMOS device of the present invention is shown. The invention can also be applied to the ultrahigh voltage PMOS element process, and only the electrical property needs to be properly modified.
According to an embodiment of the present invention, the ultra high voltage NMOS transistor device 100 is fabricated on a semiconductor substrate 10, such as a P-type silicon substrate, and is isolated by a field oxide layer 44. The uhp NMOS transistor device 100 also includes a source 14, a gate 50, and a drain 24, wherein the source 14 is a heavily doped N-type region adjacent to a heavily doped P-type region 16, and the heavily doped N-type region (source) 14 and the heavily doped P-type region 16 are both disposed in a P-well 12. The drain 24 and the source 14 may be spaced apart by more than a few microns, wherein the drain 24 is a heavily doped N-well 22 disposed in an N-well 22, and the N-well 22 may be further disposed in a deep N-well 30, thereby forming a triple gradient well structure. The gate 50 may be a metal or polysilicon gate.
In accordance with an embodiment of the present invention, a gate dielectric layer, such as gate oxide 46, is formed over the source 14, and the gate 50 is disposed over the gate oxide 46 and extends laterally over a dielectric layer, such as field oxide 142, disposed over the semiconductor region, with a void 54 in the field oxide 142 below the edge of the gate 50. In addition, a plurality of floating field electrodes (field plates) (not shown) may be further disposed on the field oxide layer 142 for disturbing the lateral electric field. The field oxide layer 142 is formed by local oxidation of silicon (LOCOS), which is interposed between the source 14 and the drain 24. The uppermost layer is a dielectric layer 56, such as an oxide layer, covering the gate 50, gate oxide 46, and field oxide 142, but leaving the void 54. The feature of the present invention is that there is a void below the gate edge, which is not limited in size, and the void can reduce the vertical electric field at the gate edge, and thus the thickness of the dielectric layer (in this embodiment, the field oxide layer 142) can be relatively reduced.
According to the evaluation of RESURFLDMOS transmissions published in 1990 by Zahir Parpia et al: an Analytical Approach (IEEE Transactions on electronic devices, Vol.37, No.3, published by March 1990) shows that the breakdown voltage (breakdown voltage) of a device (device) can be expressed by the following relation:
BVc＝*cy+(tox/ε0εox)×(2ε0εsiqND*cy)1/2
wherein,
BVc: breakdown voltage
φcy: total pressure drop through the oxide under the gate edge
tox: thickness of field oxide layer
ε0: dielectric coefficient of free space
εox: relative dielectric constant of silicon dioxide
εsi: relative dielectric constant of silicon
q: electric charge
ND: impurity concentration doped in epitaxial layer
So that when epsilon is knownoxThe smaller the breakdown voltage, the higher. According to the invention, by providing the dielectric layer under the gate edge with a void (void) structure, an almost minimum ε can be obtainedox(ii) a Therefore, the required oxide thickness can be relatively reduced, reducing the step height.
Referring to fig. 3, a cross-sectional view of an extra-high voltage NMOS device 200 according to another preferred embodiment of the present invention is shown. The dielectric layer under the gate 50 of the uhp NMOS transistor device 200 may include a thickened dielectric layer, such as the thickened oxide layer 58, formed on the field oxide layer 142 in addition to the field oxide layer 142. According to a feature of the present invention, a void 54 is provided in the thickened oxide layer 58 below the edge of the gate 50. By doing so, the gate 50 can be raised and the permittivity below the edge of the gate can be relatively reduced, thereby solving the problem of ultra-high vertical electric field caused by the edge of the gate, and the thickness of the thickened oxide layer 58 can be relatively less thick.
It should also be appreciated that voids beneath the edges of gate 50 may also be formed in the thickened dielectric layer along with the field oxide layer (not shown).
Based on when epsilonoxThe dielectric layer under the gate edge of the ultra high voltage NMOS transistor device according to the present invention may include a field oxide layer and a low-k material layer (not shown), in which case the effect of reducing the vertical electric field can be achieved without forming voids under the gate edge.
Referring to fig. 4, a cross-sectional view of an extra-high voltage NMOS device 300 according to another embodiment of the present invention is shown. The difference between the ultra high voltage NMOS device 300 depicted in fig. 4 and the ultra high voltage NMOS device 100 depicted in fig. 2 is that the dielectric layer of the ultra high voltage NMOS device 300 depicted in fig. 4 is formed by a shallow trench isolation region 342, and a void 54 is also formed under the edge of the gate 50. The ultra high voltage NMOS transistor elements are isolated by shallow trench isolation regions 344.
Referring to fig. 5, a cross-sectional view of an extra-high voltage NMOS device 400 according to another preferred embodiment of the present invention is shown. The difference between the super high voltage NMOS device 400 depicted in fig. 5 and the super high voltage NMOS device 300 depicted in fig. 4 is that the dielectric layer of the super high voltage NMOS device 400 depicted in fig. 5 is formed by a shallow trench isolation region 342 and a thickened dielectric layer, such as oxide layer 458, on the shallow trench isolation region 342, and a void 54 is also formed in the thickened oxide layer 458 below the edge of the gate 50.
Referring to fig. 6, a cross-sectional view of an extra-high voltage NMOS device 500 according to another preferred embodiment of the present invention is shown. The difference between the extra-high voltage NMOS device 500 depicted in fig. 6 and the extra-high voltage NMOS device 400 depicted in fig. 5 is that the void 54 under the edge of the gate 50 of the extra-high voltage NMOS device 500 depicted in fig. 6 is formed in both the shallow trench isolation region 342 and the thickened oxide layer 458.
The voids in the ultra high voltage NMOS device according to the embodiments of the present invention can be filled with a low-k material, so as to reduce the vertical electric field at the edge of the gate.
Referring to fig. 7, a cross-sectional view of an extra-high voltage NMOS device 600 according to another preferred embodiment of the present invention is shown. The difference between the uhp NMOS device 600 and the uhp NMOS device 300 shown in fig. 4 is that the dielectric layer of the uhp NMOS device 600 shown in fig. 7 is formed by a shallow trench isolation region 642, but the trench is filled with a porous oxide material, which is connected to the gate dielectric layer, and does not have a void, such as void 54.
Several variations of the ultra high voltage NMOS transistor device according to the present invention are described above. Furthermore, when the ultra-high voltage NMOS device further includes a deep N-well (e.g., deep N-well 30), the deep N-well may be replaced by an N-epi silicon layer, such that the P-well (e.g., P-well 12) and the N-well (e.g., N-well 22) are both formed in an N-epi silicon (epi silicon) layer.
The ultra high voltage MOS transistor device according to the present invention can be manufactured by the following method. Please refer to fig. 8 to 9. As shown in fig. 8, first, a substrate 10, such as a semiconductor substrate, having a conductivity, such as a P-type or N-type silicon substrate, is provided, and two regions in the substrate 10 are doped with ions having different conductivities, respectively, to form an ion well 12 and an ion well 22. Then, a doped region 16 with a higher concentration is formed in the ion well 12, and a doped source region 14 and a doped drain region 24 are formed in the ion wells 12 and 22, respectively. The doped source region 14 is placed in close proximity to the doped region 16 such that the ion well 12 surrounds the doped source region 14 and the doped region 16.
Next, a dielectric material, such as oxide, is deposited on the surface of the doped source region 14 and the ion well 12 to form a gate dielectric layer 46. Then, a dielectric layer 142 is formed in the semiconductor region, such that the dielectric layer is connected to the gate dielectric layer. The dielectric layer may be formed by LOCUS or STI region formation. For example, as shown in fig. 8, a field oxide layer 142 with a LOCUS structure is formed. Then, a gate 50 is formed on the gate dielectric layer 46, and the gate 50 extends to the field oxide layer 142. The structures can be manufactured in the existing mode. The next step is to remove the portion of the field oxide 142 under the edge of the gate 50 to form a void. As shown in fig. 9, the opening 60 is a result of the partial removal of the field oxide layer 142. The removal method is not particularly limited as long as the removal can be achieved, and can be accomplished by, for example, an isotropic etching (isotropic etching) technique, such as a wet etching. With isotropic etching techniques, undercuts (undercuts) may be formed below the gate edge. Finally, a deposition step is carried out to cover the entire substrate with a dielectric layer, for example an oxide layer, namely: the cavity is maintained near the gate edge due to the undercut structure on the gate, gate dielectric, and field oxide.
In addition to the LOCUS or shallow trench isolation region structure, a thickened dielectric layer, such as a thickened oxide layer, which can be a CVD silicon oxide layer formed by a Chemical Vapor Deposition (CVD) method, can be further formed on the formed field oxide layer or shallow trench isolation region, or a doped polysilicon layer can be deposited first and then oxidized. When the cavity is formed, it may be formed only in the thickened dielectric layer, or may be formed together with the field oxide layer or the shallow trench isolation region in the thickened dielectric layer, without any particular limitation. In addition, a low dielectric coefficient material can be further deposited in the hollow hole.
According to another embodiment of the present invention, the present invention further provides a method for manufacturing an ultra high voltage MOS transistor device, comprising the following steps. After forming a field oxide layer on a semiconductor region, a low-k material layer is formed (e.g., deposited) on the field oxide layer, and a gate is formed on the gate dielectric layer and extends over the low-k material layer. Finally, a dielectric layer is formed on the grid, the grid dielectric layer and the low dielectric coefficient material layer. In the method, because a low dielectric coefficient material layer is formed below the edge of the grid, the ultrahigh voltage NMOS transistor element can reduce the vertical electric field at the edge of the grid, and therefore, the step of forming a cavity is not carried out.
According to another embodiment of the present invention, a method for fabricating an ultra high voltage MOS transistor device is provided, comprising the following steps. After the gate dielectric layer is formed on the source doped region and the ion well in the above steps, a shallow trench isolation region is formed on the semiconductor region instead of forming a field oxide layer. The shallow trench is filled with a porous oxide material by, for example, deposition to form a shallow trench isolation region. And forming a gate on the gate dielectric layer and extending to the shallow trench isolation region. Finally, a dielectric layer is formed on the grid, the grid dielectric layer and the shallow groove isolation region, and the manufacture of the ultrahigh voltage MOS transistor element is completed.
The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.
Claims (36)
1. An ultra high voltage MOS transistor device, comprising:
a substrate having a first conductivity;
a source doped region having a second conductivity and disposed in the substrate;
a first doped region having the first conductivity and disposed in the substrate and adjacent to the source doped region;
a first ion well having the first conductivity and surrounding the source doped region and the first doped region;
a gate dielectric layer formed on the source doped region and the first ion well;
a first dielectric layer formed on a semiconductor region and connected to the gate dielectric layer;
a doped drain region of the second conductivity type, remote from the doped source region and disposed on one side of the first dielectric layer;
a second ion well having the second conductivity and surrounding the drain doped region;
a gate electrode disposed on the gate dielectric layer and extending to the first dielectric layer; wherein the first dielectric layer has a cavity under the edge of the gate; and
a second dielectric layer covering the gate, the gate dielectric layer and the first dielectric layer, and keeping the hollow.
2. The ultra high voltage MOS transistor device of claim 1, wherein the first dielectric layer comprises a field oxide layer.
3. The ultra high voltage MOS transistor device of claim 1, wherein the first dielectric layer comprises a field oxide layer, abutting the gate dielectric layer, and formed on the semiconductor region; and a thickened dielectric layer covering the field oxide layer, the thickened dielectric layer having the cavity under the edge of the gate.
4. The ultra high voltage MOS transistor device of claim 1, wherein the first dielectric layer comprises a field oxide layer, abutting the gate dielectric layer, and formed on the semiconductor region; and a thickened dielectric layer covering the field oxide layer, wherein the field oxide layer and the thickened dielectric layer together have the cavity below the edge of the gate.
5. The ultra high voltage MOS transistor device of claim 1, wherein the void is filled with a low dielectric coefficient material.
6. The ultra high voltage MOS transistor device of claim 1, wherein the first dielectric layer comprises a shallow trench isolation region.
7. The ultra high voltage MOS transistor device of claim 1, wherein the first dielectric layer comprises a shallow trench isolation region abutting the gate dielectric layer and formed on the semiconductor region; and a thickened dielectric layer covering the shallow trench isolation region, the thickened dielectric layer having the cavity located below the edge of the gate.
8. The ultra high voltage MOS transistor device of claim 1, wherein the first dielectric layer comprises a shallow trench isolation region abutting the gate dielectric layer and formed on the semiconductor region; and a thickened dielectric layer covering the shallow trench isolation region, wherein the shallow trench isolation region and the thickened dielectric layer together have the hollow below the edge of the gate.
9. The uhv MOS transistor device as defined in claim 1, wherein the uhv MOS transistor device further comprises a third ion well of the second conductivity in the substrate below the first dielectric layer, surrounding the second ion well.
10. An ultra high voltage MOS transistor device, comprising:
a substrate having a first conductivity;
a source doped region having a second conductivity and disposed in the substrate;
a first doped region having the first conductivity and disposed in the substrate and adjacent to the source doped region;
a first ion well having the first conductivity and surrounding the source doped region and the first doped region;
a gate dielectric layer formed on the source doped region and the first ion well;
a field oxide layer connected to the gate dielectric layer and formed on a semiconductor region;
a low dielectric coefficient material layer covering the field oxide layer;
a doped drain region of the second conductivity type, which is far away from the doped source region and is arranged on one side of the field oxide layer;
a second ion well having the second conductivity and surrounding the drain doped region;
a gate electrode on the gate dielectric layer and extending to the field oxide layer and the low-k material layer; and
a dielectric layer covering the gate, the gate dielectric layer and the low-k material layer.
11. An ultra high voltage MOS transistor device, comprising:
a substrate having a first conductivity;
a source doped region having a second conductivity and disposed in the substrate;
a first doped region having the first conductivity and disposed in the substrate and adjacent to the source doped region;
a first ion well having the first conductivity and surrounding the source doped region and the first doped region;
a gate dielectric layer formed on the source doped region and the first ion well;
a shallow trench isolation region filled with porous oxide material, connected to the gate dielectric layer, and formed on a semiconductor region;
a drain doped region having the second conductivity, being far away from the source doped region and being disposed at one side of the shallow trench isolation region;
a second ion well having the second conductivity and surrounding the drain doped region;
a gate electrode on the gate dielectric layer and extending to the shallow trench isolation region; and
a dielectric layer covering the gate, the gate dielectric layer and the shallow trench isolation region.
12. A method of fabricating an ultra high voltage MOS transistor element, comprising:
providing a substrate having a first conductivity;
forming a first ion well and a second ion well having the first conductivity and a second conductivity, respectively;
forming a first doped region in the first ion well, the first doped region having the first conductivity;
forming a source doped region and a drain doped region in the first ion well and the second ion well, respectively, the source doped region having a second conductivity and being adjacent to the first doped region, such that the first ion well surrounds the source doped region and the first doped region, the drain doped region having the second conductivity;
forming a gate dielectric layer on the source doped region and the first ion well;
forming a first dielectric layer on a semiconductor region and contacting the gate dielectric layer, wherein the drain doped region is remote from the source doped region with the first dielectric layer therebetween;
forming a gate over the gate dielectric layer and extending over the first dielectric layer;
removing the part of the first dielectric layer below the edge of the grid electrode to form an opening; and
forming a second dielectric layer on the gate, the gate dielectric layer and the first dielectric layer, and forming a cavity in the opening.
13. The method of claim 12 wherein the step of forming the first dielectric layer is forming a field oxide layer.
14. The method of claim 12 wherein said step of forming a first dielectric layer forms a field oxide layer over said semiconductor region and abutting said gate dielectric layer, and a thickened dielectric layer over said field oxide layer; and the step of removing the portion of the first dielectric layer under the edge of the gate is to remove the portion of the thickened dielectric layer under the edge of the gate to form the opening.
15. The method of claim 12 wherein said step of forming a first dielectric layer forms a field oxide layer over said semiconductor region and abutting said gate dielectric layer, and a thickened dielectric layer over said field oxide layer; and the step of removing the portion of the first dielectric layer under the edge of the gate is to remove the thickened dielectric layer and the portion of the field oxide layer under the edge of the gate to form the opening.
16. The method of claim 12, further comprising filling a low-k material into the opening after forming the opening.
17. The method of claim 12, wherein the step of forming the first dielectric layer forms a shallow trench isolation region.
18. The method of claim 12, wherein said forming a first dielectric layer forms a shallow trench isolation region on said semiconductor region and abutting said gate dielectric layer, and a thickened dielectric layer over said shallow trench isolation region; and the step of removing the portion of the first dielectric layer under the edge of the gate is to remove the portion of the thickened dielectric layer under the edge of the gate to form the opening.
19. The method of claim 12, wherein said forming a first dielectric layer forms a shallow trench isolation region on said semiconductor region and abutting said gate dielectric layer, and a thickened dielectric layer over said shallow trench isolation region; and the step of removing the portion of the first dielectric layer under the edge of the gate is to remove the thickened dielectric layer and the portion of the shallow trench isolation region under the edge of the gate to form the opening.
20. A method of fabricating an ultra high voltage MOS transistor element, comprising:
providing a substrate having a first conductivity;
forming a first ion well and a second ion well having the first conductivity and a second conductivity, respectively;
forming a first doped region in the first ion well, the first doped region having the first conductivity;
forming a source doped region and a drain doped region in the first ion well and the second ion well, respectively, the source doped region having a second conductivity and being adjacent to the first doped region, such that the first ion well surrounds the source doped region and the first doped region, the drain doped region having the second conductivity;
forming a gate dielectric layer on the source doped region and the first ion well;
forming a field oxide layer on a semiconductor region;
forming a low-k material layer on the field oxide layer, wherein the drain doped region is far away from the source doped region and is sandwiched by the field oxide layer;
forming a gate on the gate dielectric layer and extending to the low-k material layer; and
forming a dielectric layer on the gate, the gate dielectric layer and the low-k material layer.
21. A method of fabricating an ultra high voltage MOS transistor element, comprising:
providing a substrate having a first conductivity;
forming a first ion well and a second ion well having the first conductivity and a second conductivity, respectively;
forming a first doped region in the first ion well, the first doped region having the first conductivity;
forming a source doped region and a drain doped region in the first ion well and the second ion well, respectively, the source doped region having a second conductivity and being adjacent to the first doped region, such that the first ion well surrounds the source doped region and the first doped region, the drain doped region having the second conductivity;
forming a gate dielectric layer on the source doped region and the first ion well;
forming a shallow trench isolation region on a semiconductor region and connected to the gate dielectric layer, wherein the shallow trench isolation region is filled with porous oxide material, and the drain doped region is far away from the source doped region and is located between the shallow trench isolation regions;
forming a gate on the gate dielectric layer and extending to the shallow trench isolation region; and
forming a dielectric layer on the gate, the gate dielectric layer and the shallow trench isolation region.
22. An ultra high voltage MOS transistor device, comprising:
a semiconductor substrate;
at least one doped region located in the semiconductor substrate;
a gate on the semiconductor substrate;
a first dielectric layer between the gate and the doped region for isolation, the gate extending over the first dielectric layer, wherein the first dielectric layer has at least one void below the edge of the gate; and
a second dielectric layer covering the gate, the doped region and the first dielectric layer, and keeping the void.
23. The uhv MOS transistor device as defined in claim 22, further comprising a gate dielectric layer between said gate and said semiconductor substrate.
24. The uhp MOS transistor device as defined in claim 22, wherein the doped region comprises a source or drain structure.
25. The uhp MOS transistor device as defined in claim 22, wherein said first dielectric layer comprises a field oxide layer.
26. The ultra high voltage MOS transistor device of claim 22, wherein the first dielectric layer comprises a field oxide layer and a thickened dielectric layer stacked on the field oxide layer, and the void is located at the field oxide layer.
27. The ultra high voltage MOS transistor device of claim 22, wherein the first dielectric layer comprises a field oxide layer and a thickened dielectric layer stacked on the field oxide layer, and the void is located at both the field oxide layer and the thickened dielectric layer.
28. The uhp MOS transistor device as defined in claim 22, wherein the first dielectric layer comprises a shallow trench isolation region.
29. The ultra high voltage MOS transistor device of claim 22, wherein the first dielectric layer comprises a shallow trench isolation region and a thickened dielectric layer stacked on the shallow trench isolation region, and the void is located at the shallow trench isolation region.
30. The ultra high voltage MOS transistor device of claim 22, wherein the first dielectric layer comprises a shallow trench isolation region and a thickened dielectric layer stacked on the shallow trench isolation region, and the void is located between the shallow trench isolation region and the thickened dielectric layer.
31. The uhv MOS transistor device as defined in claim 22, wherein said void is filled with a low-k material.
32. The ultra high voltage MOS transistor device of claim 22, comprising two doped regions as source and drain structures disposed on opposite sides of the gate.
33. The uhp MOS transistor device as defined in claim 32, wherein said first dielectric layer under the edge of said gate terminal directed to said drain or source structure has said void.
34. The uhp MOS transistor device as defined in claim 32, wherein said first dielectric layer under the edge of said gate electrode pointing to both ends of said drain and source structures has said void.
35. An ultra high voltage MOS transistor device, comprising:
a semiconductor substrate;
at least one doped region located in the semiconductor substrate;
a gate on the semiconductor substrate; and
a first dielectric layer located between the gate and the doped region for isolation, and the gate extending to the first dielectric layer, wherein the first dielectric layer comprises porous oxide material.
36. An ultra high voltage MOS transistor device, comprising:
a semiconductor substrate;
at least one doped region located in the semiconductor substrate;
a gate on the semiconductor substrate;
a low dielectric coefficient material layer and a field oxide layer stacked up and down and located between the gate and the doped region for isolation, and the gate extends to the low dielectric coefficient material layer; and
a second dielectric layer covering the gate, the doped region and the first dielectric layer.
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| CNB2005100229596A CN100468771C (en) | 2005-12-19 | 2005-12-19 | Super high voltage metal oxide semiconductor transistor tube element and its producing method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102129996B (en) * | 2010-01-18 | 2013-04-24 | 上海华虹Nec电子有限公司 | Manufacturing method of DDDMOS (Double Diffused Drain MOS (Metal-Oxide-Semiconductor)) device |
| CN110233130A (en) * | 2019-05-29 | 2019-09-13 | 长江存储科技有限责任公司 | Semiconductor structure, UHV device and preparation method thereof |
| CN112397591A (en) * | 2020-11-11 | 2021-02-23 | 武汉新芯集成电路制造有限公司 | Semiconductor device comprising LDMOS transistor and manufacturing method |
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2005
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102129996B (en) * | 2010-01-18 | 2013-04-24 | 上海华虹Nec电子有限公司 | Manufacturing method of DDDMOS (Double Diffused Drain MOS (Metal-Oxide-Semiconductor)) device |
| CN110233130A (en) * | 2019-05-29 | 2019-09-13 | 长江存储科技有限责任公司 | Semiconductor structure, UHV device and preparation method thereof |
| CN112397591A (en) * | 2020-11-11 | 2021-02-23 | 武汉新芯集成电路制造有限公司 | Semiconductor device comprising LDMOS transistor and manufacturing method |
| CN112397591B (en) * | 2020-11-11 | 2022-06-17 | 武汉新芯集成电路制造有限公司 | Semiconductor device comprising LDMOS transistor and manufacturing method |
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| CN100468771C (en) | 2009-03-11 |
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