CN1983630A - MOS field effect pipe and its production - Google Patents
MOS field effect pipe and its production Download PDFInfo
- Publication number
- CN1983630A CN1983630A CN 200510111431 CN200510111431A CN1983630A CN 1983630 A CN1983630 A CN 1983630A CN 200510111431 CN200510111431 CN 200510111431 CN 200510111431 A CN200510111431 A CN 200510111431A CN 1983630 A CN1983630 A CN 1983630A
- Authority
- CN
- China
- Prior art keywords
- silicon area
- oxide
- field effect
- metal
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention is concerned with a kind of MOS field-effect transistor. The thickness of gate oxide from the someplace of the simple channel insulated area closed to both sides of breadth and the silicon area on boundary of silicon area to simple channel insulated area and silicon area on boundary of silicon area is less than the thickness of gate oxide of the middle area of MOS transistor. The invention is also concerned with the production method of MOS field-effect transistor. During the etching step of double gate oxide, etch off the middle press thick gate oxide of the middle part of silicon area to MOS transistor and keep the middle press thick gate oxide from the someplace of the simple channel insulated area closed to both sides of breadth and the silicon area on boundary of silicon area to simple channel insulated area and silicon area on boundary of silicon area. It advances the threshold voltage to main transistor of low voltage MOS field-effect transistor and improves the problem about the descendent of threshold voltage coming from the anti-narrow channel effect of MOS field-effect transistor by keeping the middle press thick gate oxide of the rim of silicon area to low voltage MOS transistor.
Description
Technical field
The present invention relates to a kind of technical field of semiconductors, especially a kind of metal-oxide-semiconductor field effect transistor and preparation method thereof.
Background technology
In the technology of existing making metal-oxide-semiconductor field effect transistor, the Dual Gate Oxide etch step all etches away the thick grid oxygen of middle pressure in whole low voltage mos transistor zone.Fig. 1 is the metal-oxide-semiconductor field effect transistor cross-sectional structure schematic diagram of prior art.As shown in Figure 1, be shallow trench isolation region on the silicon area both sides, the top is a grid oxygen, and grid oxygen top is a polysilicon gate, and the grid oxygen of the metal-oxide-semiconductor field effect transistor in prior art is uniform in the transistor width direction.Fig. 2 is the metal-oxide-semiconductor field effect transistor domain schematic diagram of prior art.As shown in Figure 2, on the W direction, the thickness of grid oxygen is consistent.
In the metal-oxide-semiconductor field effect transistor of the utilization shallow trench isolation technology (STI) of prior art, there is reversed narrow-path effect usually easily.Reversed narrow-path effect is equivalent in " main transistor " both sides near local in parallel added two threshold voltages (Vt) relatively low " parasitic transistor " of silicon area with the shallow trench isolation region intersection.Therefore, this reversed narrow-path effect can cause transistor threshold voltage to descend.
Summary of the invention
Technical problem to be solved by this invention provides a kind of metal-oxide-semiconductor field effect transistor and preparation method thereof, can thicken the grid oxygen of low pressure metal-oxide-semiconductor field effect transistor near shallow trench isolation region, thereby improve reversed narrow-path effect, improves transistor threshold voltage.
For solving the problems of the technologies described above, the technical scheme of a kind of metal-oxide-semiconductor field effect transistor of the present invention is, this metal-oxide-semiconductor field effect transistor at the two ends of its Width near the somewhere in the silicon area of shallow trench isolation region and silicon area intersection to the thickness of the grid oxygen of shallow trench isolation region and silicon area intersection gate oxide thickness greater than the metal-oxide-semiconductor zone line.
A kind of technical scheme of making metal-oxide-semiconductor field effect transistor of the present invention is, in the Dual Gate Oxide etch step, only etch away the thick grid oxygen of middle pressure of low voltage mos transistor silicon area mid portion, the two ends that keep the metal-oxide-semiconductor field effect transistor Width are near somewhere in the silicon area of shallow trench isolation region and silicon area intersection and the thick grid oxygen of middle pressure between shallow trench isolation region and the silicon area intersection.
The present invention is by in the Dual Gate Oxide etch step, only etch away the thick grid oxygen of middle pressure of low voltage mos transistor silicon area mid portion, make metal-oxide-semiconductor field effect transistor at the silicon area edge near the thickness of the grid oxygen of shallow trench isolation region gate oxide thickness greater than the metal-oxide-semiconductor zone line, thereby improve reversed narrow-path effect, improve transistor threshold voltage.
Description of drawings
Below in conjunction with drawings and Examples the present invention is further described:
Fig. 1 is the metal-oxide-semiconductor field effect transistor cross-sectional structure schematic diagram of prior art;
Fig. 2 is the metal-oxide-semiconductor field effect transistor domain schematic diagram of prior art;
Fig. 3 is a metal-oxide-semiconductor field effect transistor cross-sectional structure schematic diagram of the present invention;
Fig. 4 is a metal-oxide-semiconductor field effect transistor domain schematic diagram of the present invention.
Embodiment
Fig. 3 is a metal-oxide-semiconductor field effect transistor cross-sectional structure schematic diagram of the present invention.As shown in Figure 3, metal-oxide-semiconductor field effect transistor of the present invention is a shallow trench isolation region on the silicon area both sides, and the top is a grid oxygen, and grid oxygen top is a polysilicon gate.Because in the Dual Gate Oxide etch step, the middle pressure grid oxygen in the middle of the silicon area is etched, therefore in the middle of silicon area, has only the low pressure of existence grid oxygen.And the distance apart from shallow trench isolation region and silicon area intersection is the place that a arrives above-mentioned intersection near the silicon area of shallow trench isolation region and silicon area intersection, the middle pressure grid oxygen of this part is not etched in the Dual Gate Oxide etch step, makes the grid oxygen of this part comprise low pressure grid oxygen and middle pressure grid oxygen.Therefore, this metal-oxide-semiconductor field effect transistor near the somewhere in the silicon area of shallow trench isolation region and silicon area intersection to the thickness of the grid oxygen of shallow trench isolation region and silicon area intersection gate oxide thickness greater than the metal-oxide-semiconductor zone line.Fig. 4 is a metal-oxide-semiconductor field effect transistor domain schematic diagram of the present invention.As shown in Figure 4, on the W direction, a is the reserve area of middle pressure grid oxygen, and is the etch areas of central grid oxygen in the centre of silicon area.
In order to make metal-oxide-semiconductor field effect transistor of the present invention, a kind of method of making metal-oxide-semiconductor field effect transistor of the present invention, the thick grid oxygen of piezoelectric crystal in must after being grown in the thin grid oxygen of low voltage transistor, growing.At first according to the order of severity of low voltage transistor reversed narrow-path effect, the thickness of middle piezoelectric crystal grid oxygen, the thickness of low voltage transistor grid oxygen, the comprehensive device property of low voltage transistor, and relevant layout design rules presses the geometric parameter " a " of the low voltage mos transistor silicon fringe region size that thick grid oxygen kept to be optimized to being used for characterizing.
Parameter " a " is carried out corresponding modification to Dual Gate Oxide etching photolithography plate domain after determining.Make when the Dual Gate Oxide etching, only etch away the thick grid oxygen of middle pressure of low voltage mos transistor silicon area mid portion, keep the middle pressure thick grid oxygen of silicon area edge near the low voltage mos transistor part of shallow trench isolation regions.Thereby on the common process basis, thicken the grid oxygen of low pressure metal-oxide-semiconductor field effect transistor near shallow trench isolation region by revising Dual Gate Oxide etching photolithography plate domain, make this metal-oxide-semiconductor field effect transistor at the silicon area edge near the thickness of the grid oxygen of shallow trench isolation region gate oxide thickness greater than the metal-oxide-semiconductor zone line.Thereby improve reversed narrow-path effect, avoid the reduction of threshold voltage.
The present invention is passing through to revise Dual Gate Oxide etching photolithography plate domain on the common process basis, make the Dual Gate Oxide etch step only the thick grid oxygen of the subregional middle pressure of the pars intermedia of low voltage mos transistor be etched away, kept the thick grid oxygen of middle pressure of the low voltage mos transistor silicon area marginal portion of close shallow trench isolation regions simultaneously.The thick grid oxygen of middle pressure that has kept low voltage mos transistor silicon area marginal portion, equivalence with artificially thickeied the grid oxygen of low voltage mos transistor marginal portion, thereby increased the gate oxide thickness of " parasitic transistor ".The gate oxide thickness that increases " parasitic transistor " will improve its threshold voltage effectively, thereby improve the total transistorized threshold voltage of low pressure metal-oxide-semiconductor field effect transistor, thereby improve the problem that threshold voltage that the metal-oxide-semiconductor field effect transistor reversed narrow-path effect causes descends.
Claims (4)
1. metal-oxide-semiconductor field effect transistor, it is characterized in that, this metal-oxide-semiconductor field effect transistor at the two ends of its Width near the somewhere in the silicon area of shallow trench isolation region and silicon area intersection to the thickness of the grid oxygen of shallow trench isolation region and silicon area intersection gate oxide thickness greater than the metal-oxide-semiconductor zone line.
2. metal-oxide-semiconductor field effect transistor according to claim 1, it is characterized in that, somewhere in the silicon area of close shallow trench isolation region in the two ends of metal-oxide-semiconductor field effect transistor Width and silicon area intersection and the distance between shallow trench isolation region and the silicon area intersection are by the thickness of the order of severity of low voltage transistor reversed narrow-path effect, middle piezoelectric crystal grid oxygen, the thickness of low voltage transistor grid oxygen, and the device synthesis characteristic of low voltage transistor is determined.
3. method of making the described metal-oxide-semiconductor field effect transistor of claim 1, it is characterized in that, in the Dual Gate Oxide etch step, only etch away the thick grid oxygen of middle pressure of low voltage mos transistor silicon area mid portion, the two ends that keep the metal-oxide-semiconductor field effect transistor Width are near somewhere in the silicon area of shallow trench isolation region and silicon area intersection and the thick grid oxygen of middle pressure between shallow trench isolation region and the silicon area intersection.
4. the method for the described metal-oxide-semiconductor field effect transistor of claim 3, it is characterized in that, the two ends of metal-oxide-semiconductor field effect transistor Width are near somewhere in the silicon area of shallow trench isolation region and silicon area intersection and the distance between shallow trench isolation region and the silicon area intersection, according to the thickness of the order of severity of low voltage transistor reversed narrow-path effect, middle piezoelectric crystal grid oxygen, the thickness of low voltage transistor grid oxygen, the comprehensive device property of low voltage transistor, and layout design rules is determined.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101114316A CN100446273C (en) | 2005-12-13 | 2005-12-13 | MOS field effect pipe and its production |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101114316A CN100446273C (en) | 2005-12-13 | 2005-12-13 | MOS field effect pipe and its production |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1983630A true CN1983630A (en) | 2007-06-20 |
| CN100446273C CN100446273C (en) | 2008-12-24 |
Family
ID=38165997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101114316A Active CN100446273C (en) | 2005-12-13 | 2005-12-13 | MOS field effect pipe and its production |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100446273C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956690A (en) * | 2011-08-16 | 2013-03-06 | 爱思开海力士有限公司 | Semiconductor device and method of manufacturing the same |
| CN103579316A (en) * | 2012-08-06 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor element, integrated circuit, manufacturing method of semiconductor element and integrated circuit and electronic device |
| CN110112065A (en) * | 2019-05-10 | 2019-08-09 | 德淮半导体有限公司 | Semiconductor devices and forming method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6189675A (en) * | 1984-10-09 | 1986-05-07 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPH06275822A (en) * | 1993-03-23 | 1994-09-30 | Fuji Electric Co Ltd | Mos transistor |
| US6033943A (en) * | 1996-08-23 | 2000-03-07 | Advanced Micro Devices, Inc. | Dual gate oxide thickness integrated circuit and process for making same |
| KR19990049409A (en) * | 1997-12-12 | 1999-07-05 | 윤종용 | How to Form Gate Oxides of Different Thickness |
| CN1269222C (en) * | 2003-02-20 | 2006-08-09 | 北京大学 | An asymmetric grid field effect transistor |
-
2005
- 2005-12-13 CN CNB2005101114316A patent/CN100446273C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956690A (en) * | 2011-08-16 | 2013-03-06 | 爱思开海力士有限公司 | Semiconductor device and method of manufacturing the same |
| CN102956690B (en) * | 2011-08-16 | 2016-09-28 | 爱思开海力士有限公司 | Semiconductor device and manufacture method thereof |
| CN103579316A (en) * | 2012-08-06 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor element, integrated circuit, manufacturing method of semiconductor element and integrated circuit and electronic device |
| CN103579316B (en) * | 2012-08-06 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices, integrated circuit and their manufacture method and electronic installation |
| CN110112065A (en) * | 2019-05-10 | 2019-08-09 | 德淮半导体有限公司 | Semiconductor devices and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100446273C (en) | 2008-12-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8193057B2 (en) | MOS transistor for reducing short-channel effects and its production | |
| US8673722B2 (en) | Strained channel field effect transistor and the method for fabricating the same | |
| US9082751B2 (en) | Half-FinFET semiconductor device and related method | |
| US20160359018A1 (en) | Split gate semiconductor device with curved gate oxide profile | |
| US10411116B2 (en) | Semiconductor super-junction power device and manufacturing method therefor | |
| CN105225935A (en) | There is trench gate structure and the manufacture method thereof of shield grid | |
| CN103515422A (en) | FinFET with high mobility and strain channel | |
| US20130292775A1 (en) | Strained silicon structure | |
| CN104103694A (en) | Trench type insulated gate field effect transistor and manufacture method thereof | |
| WO2016011674A1 (en) | Power mos transistor and manufacturing method therefor | |
| CN104103523A (en) | Method for manufacturing power device with U-shaped grooves | |
| CN104795445A (en) | Low-loss super-junction power device and manufacturing method thereof | |
| TW200636869A (en) | Method of making a planar double-gated transistor | |
| CN100446273C (en) | MOS field effect pipe and its production | |
| CN102479738B (en) | Trench isolation structure and forming method for same | |
| CN101752416A (en) | High-voltage LDMOS device | |
| CN108091695B (en) | Vertical double-diffused field effect transistor and manufacturing method thereof | |
| CN1983631A (en) | MOS field effective pipe and its production | |
| CN103187300B (en) | Fin formula field effect transistor and forming method thereof | |
| CN105206608B (en) | A kind of ditching type MOSFET processing method of dual-die | |
| CN102254949B (en) | Silicon-on-insulator mos transistor structure | |
| CN104576532A (en) | Manufacturing method of integrated structure of MOS transistor, polysilicon resistor and polysilicon capacitor | |
| CN115692501A (en) | Transistor structure | |
| US20110169079A1 (en) | Semiconductor device having an overlapping multi-well implant and method for fabricating same | |
| CN103594492A (en) | A LDMOS transistor and a forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131216 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20131216 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |