CN1983522A - Method for fabricating a dielectric stack - Google Patents

Method for fabricating a dielectric stack Download PDF

Info

Publication number
CN1983522A
CN1983522A CNA2006101608908A CN200610160890A CN1983522A CN 1983522 A CN1983522 A CN 1983522A CN A2006101608908 A CNA2006101608908 A CN A2006101608908A CN 200610160890 A CN200610160890 A CN 200610160890A CN 1983522 A CN1983522 A CN 1983522A
Authority
CN
China
Prior art keywords
layer
cluster
oxide layer
nitride
metallic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006101608908A
Other languages
Chinese (zh)
Inventor
普拉文·K·纳万卡
施雷亚斯·S·卡尔
尚克尔·穆苏克里斯南
拉胡·沙拉普尼
菲利普·克劳斯
克里斯·奥尔森
卡莱德·Z·埃哈迈德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/298,553 external-priority patent/US20060153995A1/en
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of CN1983522A publication Critical patent/CN1983522A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses methods for forming dielectric materials on a substrate in a single cluster tool. In one embodiment, the method includes providing a cluster tool having a plurality of deposition chambers, depositing a metal-containing oxide layer on a substrate in a first chamber of the cluster tool, treating the metal-containing oxide layer with an insert plasma process in a second chamber of the cluster tool, annealing the metal-containing oxide layer in a third chamber of the cluster tool, and depositing a gate electrode layer on the annealed substrate in a fourth chamber of the cluster tool.

Description

Be used to make the method for dielectric lamination
Technical field
Embodiments of the present invention relate to and being used in cluster (cluster tool) method of deposition materials on substrate, especially relate to the method that is used in integrated cluster deposition of dielectric materials when forming dielectric stack.
Background technology
Integrated circuit can comprise the microelectronics field-effect transistor (for example, CMOS (Complementary Metal Oxide Semiconductor) (CMOS) transistor) above 1,000,000, and it is formed on the substrate and cooperatively interacts in circuit to carry out multiple function.The CMOS transistor comprises and is arranged on the source region that is formed on the substrate and the grid structure between the drain region.The grid structure generally comprises grid and gate medium.Grid is arranged on the gate medium with the flowing of the charge carrier in the control channel region, and this channel region is formed between the drain region and source region under the gate medium.In order to improve transistorized speed, can form gate medium by having the material of dielectric constant greater than 4.0.Here this dielectric material is called as high dielectric constant material.
The grid structure that manufacturing has the field-effect transistor of high-dielectric-coefficient grid medium comprises series of process step (for example deposit multilayer), and it is implemented by different substrate processing reactors.In the forming process of grid stepped construction, not only require conformal thin film, and the boundary layer between every layer must have high-quality.
In traditional CMOS fabrication scheme, substrate need transmit having between the different reactor coupling equipment thereon.The process that transmits substrate at equipment room must make substrate move to the vacuum environment of second equipment from the vacuum environment of an equipment being used for transmitting under ambient pressure, around in the environment, substrate is exposed to such as in machinery such as particulate, moisture and the chemical pollutant, and these pollutants will damage the grid structure of making also may form unexpected boundary layer.Owing to becoming littler for the speed grid structure that improves device and/or more narrowing down, the adverse effect or the pollutant that form boundary layer are more paid close attention to.In addition, between cluster, transmit the manufacturing productive rate of the required time reduction field-effect transistor of substrate.
Therefore, integrated and a kind of improved cluster that is used to make the grid structure of field-effect transistor of technology is essential.
Summary of the invention
The invention provides the method that is used on substrate, forming dielectric material at single cluster.In one embodiment, a kind of method comprises provides a kind of cluster with a plurality of deposition chambers, in first process chamber of described cluster, on substrate, deposit the containing metal oxide layer, in second process chamber of described cluster, utilize the described containing metal oxide layer of inert, plasma PROCESS FOR TREATMENT, the described containing metal oxide layer of annealing in process in the 3rd process chamber of described cluster, and in the 4th process chamber of described cluster, on the containing metal oxide layer of described annealing in process, deposit grid layer.
In another embodiment, this method comprises provides a kind of cluster with a plurality of deposition chambers, prerinse substrate in described cluster, in first process chamber of described cluster, on substrate, deposit the containing metal oxide layer, in second process chamber of described cluster, utilize the described containing metal oxide layer of inert, plasma PROCESS FOR TREATMENT, the described containing metal oxide layer of annealing in process in the 3rd process chamber of described cluster, and in the 4th process chamber of described cluster, on the containing metal oxide layer of described annealing in process, deposit grid layer.
In an execution mode again, this method comprises provides a kind of cluster with a plurality of deposition chambers, prerinse substrate in described cluster, in described cluster, on substrate, deposit the containing metal oxide layer, in described cluster, adopt deposition post growth annealing annealing containing metal oxide layer, in described cluster, utilize the described containing metal oxide layer of inert, plasma PROCESS FOR TREATMENT, the described containing metal oxide layer of annealing in process in described cluster, and in described cluster, on the containing metal oxide layer of described annealing in process, deposit grid layer.
Description of drawings
Can make the present invention be easier to understand by following detailed description in conjunction with the accompanying drawings, in the accompanying drawings:
Fig. 1 be used for one embodiment of the present invention a kind of exemplary integrated Semiconductor substrate treatment system schematic diagram (for example: cluster);
Fig. 2 is used in the cluster of Fig. 1 the flow chart of the illustrative processes of dielectric layer on substrate; And
Fig. 3 A is to the schematic diagram of the substrate of Fig. 3 E during for the different phase of the operation mentioned among Fig. 2;
For the ease of understanding, represent components identical in the accompanying drawing with identical Reference numeral as far as possible.Element and the feature that should consider an execution mode can be following advantageously in conjunction with in other embodiments in situation about not further describing.
Yet, should be noted that only to show illustrative embodiments of the present invention in the accompanying drawing that therefore can not think limiting the scope of the invention, the present invention can allow other equivalent execution modes.
Embodiment
Embodiments of the present invention mainly are provided for preparation method and a kind of system that is used in the dielectric material in the different application, such as the gate stack that is used in the field effect transistor pipe manufacturer.In one embodiment, deposition of dielectric materials or dielectric lamination in integrated cluster.In another embodiment, the dielectric layer that contains metal oxide by deposition prepares dielectric material or dielectric lamination, for example utilize ald (ALD) technology on substrate, to deposit high dielectric constant material, utilization is exposed to substrate in the inert gas plasma technology, then substrate is exposed in the thermal anneal process and under break vacuum situation not in integrated cluster deposit spathic silicon grid layer and/or metal gate layer (for example, carrying out in the equipment of all technologies in kindred circumstances).Alternatively, in same equipment on the substrate deposition first dielectric layer before, but the prerinse substrate.
Fig. 1 be used for a kind of exemplary integrated Semiconductor substrate treatment system of one embodiment of the present invention schematic diagram (for example: cluster 100).Should consider that method as herein described can be applicable to have in other equipment of the processing chamber that is coupled to the necessity on it.
Equipment 100 comprises vacuum-tight processing platform 101, production interface (factory interface) 102 and system controller 136.Platform 101 comprises that a plurality of processing modules 110,108,114,112,118,116,124 and at least one load interlock process chamber (be depicted as and load interlock process chamber 120), and it is coupled to vacuum substrate transfer chamber 103,104.Production interface 102 is coupled to transfer chamber 104 by loading interlock process chamber 120.
In one embodiment, production interface 102 comprises at least one base (docking staion), at least one substrate transfer robot 138, at least one substrate transport platform 140 and at least one prerinse process chamber 124 and prerinse manipulator 122.This base is set makes it receive one or more front-open wafer boxes (FOUP).Shown in the execution mode of Fig. 1 be two FOUP128A, 128B.Design substrate transfer robot 138 makes it that substrate is sent to from production interface 102 and loads interlocking prerinse process chamber 124, carries out prerinse here and handles.Design prerinse manipulator 122 makes it load interlock process chamber 120 from substrate is transferred to from prerinse process chamber 124.Alternatively, substrate can be walked around prerinse process chamber 124 and directly is sent to from production interface 102 and loads the locking process chamber 120.
Loading interlock process chamber 120 has and first port of production interface 102 couplings and second port that is coupled with first transfer chamber 104.Load interlock process chamber 120 and be coupled to the pneumatic control system (not shown), when need additional substrate transmits between (for example atmosphere) environment around the vacuum environment of transfer chamber 104 and production interface 102 basic, this baric systerm be bled and exhaust to process chamber 120.
First transfer chamber 104 and second transfer chamber 103 have first manipulator 107 disposed thereon and second manipulator 105 respectively.Two substrate delivery platform 106A, 106B are arranged in the transfer chamber 104 to promote that substrate transmits between manipulator 105,107.Platform 106A, 106B not only can communicate with transfer chamber 103,104 but also can optionally isolate (i.e. sealing) with transfer chamber 103,104 to allow keeping different operating air pressures in each transfer chamber 103,104.
The manipulator (robot) 107 that is arranged in first transfer chamber 104 can transmit substrate between loading interlock process chamber 120, processing chamber 116,118 and substrate delivery platform 106A, 108B.The manipulator 105 that is arranged in second transfer chamber 103 can transmit substrate between substrate delivery platform 106A, 106B and processing chamber 112,114,110,108.
In one embodiment, the processing chamber with 104 couplings of first transfer chamber can be metal organic chemical vapor deposition (MOCVD) process chamber 118 and decoupled plasma nitridation (DPN) process chamber 116.Can be rapid thermal treatment (RTP) process chamber 114, chemical vapor deposition (CVD) process chamber 110, first ald (ALD) process chamber 108 and second ald (ALD) process chamber 112 with the processing chamber of second transfer chamber, 103 couplings.ALD, CVD, PVD, DPN, RTP and the MOCVD processing chamber that is fit to can (Applied Materials Inc) buys and obtains from the Applied Materials of the Santa Clara that is positioned at California, USA.
System controller 136 and integrated treatment facility 100 couplings.System controller 136 utilizes the processing chamber of direct control appliance 100 or alternatively, by the operation of relevant computer (perhaps controller) control appliance 100 of control and processing chamber and equipment 100.In operation, system controller 140 activates the data collection and the performance of feedback with optimization system 100 from each process chamber and system.
System controller 136 generally comprises CPU (CPU) 130, memory 134 and auxiliary circuit 132.CPU130 can be one of general-purpose computer processor that can be used for the arbitrary form in the industrial setting.Auxiliary circuit 132 generally is coupled to CPU130 and can comprises buffer, clock circuit, I/O subsystem, power supply etc.When utilizing CPU130 to carry out such as following during with reference to the described dielectric of Fig. 2 depositing operation 200, software program is converted to special-purpose computer (controller) 136 with CPU.Also can utilize storage of the second controller (not shown) and/or software program for execution away from equipment 100.
Fig. 2 is the flow chart that is used for such as an execution mode of the technology 200 of integrated cluster dielectric layer on substrate of aforesaid equipment 100.Fig. 3 A is a schematic cross-section for the different step of technology 200 to Fig. 3 E.
Method 200 starts from step 202, in this step substrate 300 is arranged in the equipment 100.As shown in Figure 3A, substrate 300 refers to carry out any substrate or the material that film is handled thereon.For example, substrate 300 can be such as crystalline silicon (for example Si＜100〉or Si＜111 〉), silica, stress silicon, SiGe, doping or un-doped polysilicon, doping or non-doping wafer and composition or the not silicon-on-insulator of composition (SOI) wafer, germanium, GaAs, glass, sapphire.Substrate 300 can comprise layer 301 disposed thereon.In the execution mode that layer 301 do not occur, can on substrate 300, carry out alternatively as technology in layer 301 the above execution.
Layer 301 can be any materials, such as metal, metal nitride, metal alloy and other electric conducting materials, barrier layer, titanium, titanium nitride, tungsten nitride, tantalum and tantalum nitride, dielectric material or silicon.Substrate 300 can be of different sizes, such as the wafer of 200mm or 300mm diameter, and rectangle or square-shaped planar.Unless stated otherwise, execution mode as herein described and example are to carry out on the substrate of 200mm or 300mm at diameter.Having or do not have layer 301 substrate 300 can be exposed in the pretreating process with grinding, etching, reduction, oxidation, hydroxylating, anneal and/or cure upper surface.
In optional step 203, the layer 301 that is arranged on the substrate 300 is carried out prerinse.Pre-wash step 203 is set makes lip-deep compound and the functional group's termination that is exposed to layer 301.The lip-deep functional group that adheres to and/or be formed on layer 301 comprises hydroxyl (OH), alkoxyl (OR, wherein R=Me, Et, Pr or Bu), oxyhalogen thing (haloxyl) (OX, wherein X=F, Cl, Br or I), halide (F, Cl, Br or iodine), oxygen radical and amino (NR or NR 2, wherein R=H, Me, Et, Pr or Bu).Prerinse technology can be exposed to layer 301 such as NH 3, B 2H 6, SiH 4, SiH 6, H 2O, HF, HCl, O 2, O 3, H 2O, H 2O 2, H 2, H atom, N atom, O atom, alcohol, amine, plasma and derivative or composition reactant in.Functional group can be that the chemical precursor that enters provides basic element so that it adheres on the surface of layer 301.In one embodiment, prerinse gas can be exposed to the surface of layer 301 time about 1 second to 2 minutes in the reactant.In another embodiment, the time of exposure can be from about 5 seconds to about 60 seconds.Prerinse technology can comprise that also the surface with layer 301 is exposed in RCA solution (SC1/SC2), HF-last solution, steam, hydrogenperoxide steam generator, acid solution, alkaline solution, plasma and the derivative thereof or composition from WVG or ISSG system.
In a prewashed example, substrate 300 is being exposed to wet cleaning has with formation that thickness is about or less than 10 , all 5  according to appointment remove natural oxidizing layer before the chemical oxide layer of 7 .Natural oxidizing layer can pass through the HF-last solution removal.Can be at TEMPEST TMCarry out wet cleaning in the wet purging system, this system can buy from Applied Materials and obtain.In another example, substrate 300 is exposed to from the steam of WVG system about 15 seconds.
In step 204, shown in Fig. 3 B, dielectric layer 302 is deposited on the layer 301 in processing chamber.Dielectric layer 302 can be metal oxide and can utilize ALD technology, MOCVD technology, traditional CVD technology or PVD technology to deposit.In addition, dielectric layer 302 can be and has dielectric constant greater than 4.0 dielectric layer.Can in one of them of aforesaid process chamber, carry out these technologies.
In one embodiment, dielectric layer 302 in the depositing operation process chamber, and this process chamber comprises the oxidizing gas that provided and such as at least a predecessor in hafnium precursor, zirconium precursor thing, silicon predecessor, aluminium predecessor, tantalum predecessor, titanium precursor thing, lanthanum predecessor and the composition thereof.The example of the dielectric material that can form during depositing operation comprises hafnium oxide, zirconia, lanthana thing, tantalum oxide, titanium oxide, aluminium oxide and derivative or composition.
In one embodiment, but ALD technology depositing metal oxide materials with cambium layer 302.In one embodiment, from about 1Torr to about 100Torr, or from about 1Torr to about 20Torr, or carry out ALD technology under the chamber pressure from about 1Torr to about 10Torr.The temperature of substrate 300 can maintain from about 70 degrees centigrade to about 1000 degrees centigrade, or from about 100 degrees centigrade to about 650 degrees centigrade, or from about 250 degrees centigrade to about 500 degrees centigrade.
In an example of the ALD technology that is suitable for sedimentary deposit 302, hafnium precursor is passed into the processing chamber with speed from about 5sccm to about 200sccm.Hafnium precursor can feed process chamber from about 50sccm to about 1000sccm with overall flow rate with the carrier gas such as nitrogen.According to the composition of the expection of the hafnium oxide material of concrete process conditions, hafnium precursor or deposition, hafnium precursor can feed to processing chamber in the speed pulse from about per second 0.1 pulse to about per second 10 pulses.In one embodiment, hafnium precursor with from about per second 1 pulse to about per second 5 pulses, the speed pulse of for example about per second 3 pulses feeds in the processing chamber.In another embodiment, hafnium precursor with from about per second 0.1 pulse to about per second 1 pulse, the speed pulse of for example about per second 0.5 pulse feeds in the processing chamber.In an example, hafnium precursor can be hafnium tetrachloride (HFCl 4).In another example, hafnium precursor can be four (two hydroxylaminos) hafnium compound.Such as four (lignocaine) hafnium ((Et 2N) 4Hf or TDEAH).
Usually, utilize the introducing carrier gas hafnium precursor to be dispersed in the processing chamber by the ampoule (ampoule) that contains hafnium precursor.Ampoule can comprise that ampoule, air bag, box or other are used to comprise or disperse the container of chemical precursor.The ampoule that is fit to is such as PROE-VAP TM, can buy from the Advanced Technology Materials company of the Danbury that is positioned at Land of Steady Habits and obtain.In an example, ampoule contain temperature from about 150 degrees centigrade to about 200 degrees centigrade HfCl 4In another example, ampoule can comprise liquid precursor (for example: TDEAH, TDMAH, TDMAS or Tris-DMA) and be the part of liquid conveying system, and this liquid conveying system comprises the injection valve system of the gas-carrying evaporation liquid precursor that is used to utilize heating.Usually, ampoule can be forced into about 414kPa (about 60psi) and is heated to or is lower than about 100 degrees centigrade from about 138kPa (about 20psi), for example from about 20 degrees centigrade to about 60 degrees centigrade.
Oxidizing gas can for example feed processing chamber from about 0.5sccm to about 100sccm with the flow velocity from about 0.05sccm to about 1000sccm.Oxidizing gas inputs to processing chamber with the speed pulse from about per second 0.05 pulse to about per second 10 pulses, for example from about per second 0.08 pulse to about per second 3 pulses, and in another embodiment, from about per second 0.1 pulse to about per second 2 pulses.In one embodiment, oxidizing gas with from about per second 1 pulse to about per second 5 pulses, for example about per second 1.7 pulses are to processing chamber.In one embodiment, oxidizing gas with from about per second 1 pulse to about per second 5 pulses, the speed pulse of for example about per second 1.7 pulses inputs in the processing chamber.In another embodiment, oxidizing gas with from about per second 0.1 pulse to about per second 3 pulses, the speed pulse of for example about per second 0.5 pulse inputs in the processing chamber.
Multiple predecessor is the material that is used for dielectric layer 302 in the embodiment of the present invention scope.Important predecessor is characterized as has suitable vapor pressure.Predecessor at ambient temperature and air pressure can be gas, liquid or solid.Yet, in the ALD process chamber, adopt volatile predecessor.Organo-metallic compound comprises at least a metallic atom and at least a such as containing of amino, alkyl, alkoxyl, alkyl amino or aniline of organic functional group.Predecessor can comprise organometallic, inorganic or halid compound.
Exemplary hafnium precursor comprises hafnium compound, and it comprises such as halide, alkyl amino, cyclopentadienyl, alkyl, alkoxide and derivative thereof or its composition.Hafnium halide compound as hafnium precursor can comprise HfCl 4, Hfl 4, and HfBr 4Comprise (RR ' N) as the hafnium amino compounds of hafnium precursor 4Hf, wherein R or R ' are hydrogen, methyl, ethyl, propyl group or butyl independently.The hafnium precursor that is used to deposit hafnium containing material comprises (Et 2N) 4Hf, (Me 2N) 4Hf, (MeEtN) 4Hf, ( tBuC 5H 4) 2HfCl 2, (C 5H 5) 2HfCl 2, (EtC 5H 4) 2HfCl 2, (Me 5C 5) 2HfCl 2, (Me 5C 5) HfCl 3, ( iPrC 5H 4) 2HfCl 2, ( iPrC 5H 4) HfCl 3, ( tBuC 5H 4) 2HfMe 2, (acac) 4Hf, (hfac) 4Hf, (tfac) 4Hf, (thd) 4Hf, (NO 3) 4Hf, ( tBuO) 4Hf, ( iPrO) 4Hf, (EtO) 4Hf, (MeO) 4The Hf or derivatives thereof.In addition, the hafnium precursor that is used for here during the depositing operation comprises HfCl 4, (Et 2N) 4Hf or (Me 2N) 4Hf.
After the depositing operation, can be exposed to back deposition anneal (PDA) technology alternatively at step 205 substrate 300.The substrate 300 that is provided with dielectric layer 302 thereon is transferred to annealing chamber 114, such as RADIANCE TMIn the RTP process chamber.Because annealing chamber 114 is positioned on the same cluster as deposition chambers, so substrate 300 is annealed not being exposed under the surrounding environment.Substrate 300 temperature can be heated to from about 600 degrees centigrade to about 1,200 degree centigrade, perhaps from about 600 degrees centigrade to about 1,150 degree centigrade, perhaps from about 600 degrees centigrade to about 1,000 degree centigrade.The maintainable duration of PDA technology is from about 1 second to about 5 minutes, for example, and from about 1 minute to about 4 minutes, and in another embodiment, from about 2 minutes to about 4 minutes.Usually, process chamber gas comprises at least a anneal gas, such as oxygen (O 2), ozone (O 3), oxygen atom (O), water (H 2O), nitric oxide (NO), nitrous oxide (N 2O), nitrogen dioxide (NO 2), dinitrogen pentoxide (N 2O 5), nitrogen (N 2), ammonia (NH 3), hydrazine (N 2H 4) and derivative or composition.Anneal gas commonly used comprises nitrogen and at least a oxygen-containing gas such as oxygen.The air pressure of process chamber be from about 5Torr to about 100Torr, for example, about 10Torr.In an example of PDA technology, the substrate 200 that will comprise oxide skin(coating) 202 in oxygen atmosphere was heated to about 600 ℃ temperature about 4 minutes.
In step 206, shown in Fig. 3 C, dielectric layer 302 is exposed in the inert, plasma technology and forms plasma treatment layer 304 simultaneously with the sclerosis dielectric material.Inert, plasma technology can comprise uncoupling inert gas plasma technology or long-range inert gas plasma technology, by inert gas being fed (being DPN process chamber 116) execution uncoupling inert gas plasma technology in uncoupling pecvd nitride (DPN) process chamber,, inert gas carries out long-range inert gas plasma technology in the processing chamber that is assemblied in remote plasma system by being fed.
In an execution mode of inert, plasma technology, substrate 300 is sent in the DPN process chamber 114, because the DPN process chamber is the same cluster that is positioned at as being used for the ALD process chamber of dielectric layer 302, and this process chamber is used to deposit after annealing alternatively to be handled, so substrate 300 is not exposed in the surrounding environment when transmitting between cluster.During transmitting substrate, can in transfer chamber 104,103, feed nitrogen to avoid between the two, forming boundary layer.In inert, plasma technology, and adopt by argon gas being fed the argon ion bombardment dielectric layer 302 that forms in the DPN process chamber.The gas that can be used in the inert, plasma technology comprises nitrogenous gas, argon gas, helium, xenon or its composition.
If nitrogen is fed or nitrogen is fed with inert gas, nitrogen is with the nitrogenize dielectric material, such as making metal oxide be converted into metal oxynitride.Be used for trace nitrogen nitriding process and that may be present in the DPN process chamber and may non-ly carry out plasma process with inert gas in conjunction with the while wittingly.The utilization of inert, plasma gas comprises at least a inert gas or the gas of a trace nitrogen only.In one embodiment, because the remaining nitrogen in the inert gas, nitrogen gas concn is about 1% volume or littler, for example, and about 0.1% or small size more, and in one embodiment, about 100ppm or littler, all 50ppm according to appointment.In an example, inert, plasma technology comprises argon gas and nonnitrogenous gas or nonnitrogenous substantially gas.Therefore, inert, plasma technology has improved the stability and the density of dielectric material, has reduced equivalent oxide thickness (EOT) value simultaneously.
The duration that inert, plasma technology is carried out is from about 10 seconds to about 5 minutes, for example, and from about 30 seconds to about 4 minutes, and in one embodiment, from about 1 minute to about 3 minutes.In addition, be under about 500 watts to about 3,000 watts in that plasma power is set, for example, about 700 watts to about 2,500 watts, for example carry out inert, plasma technology to about 1,800 watt of scope from about 900 watts.Usually, about 50% to 100% in duty ratio, and pulse frequency is carried out plasma process under about 10kHz.The air pressure that the DPN process chamber can have arrives about 80mTorr for about 10mTorr.The flow velocity of inert gas from about per minute 10 standard cubic centimeters (sccm) to about per minute 5 standard liters (slm), perhaps from about 50sccm to about 750sccm, perhaps from about 100sccm to about 500sccm.In one embodiment, inert, plasma is the unazotized argon plasma that produces among the DPN.
In another embodiment, during the inert, plasma technology of step 206, do not transmitting under the situation of substrate 300 between the processing chamber, the processing chamber that also is used for dielectric layer 302 is to form plasma treatment layer 304.For example, being used for the processing chamber that disposes remote plasma equipment of dielectric layer 302, in ALD process chamber or CVD process chamber, dielectric layer 302 is exposed in the long-range argon plasma with direct formation plasma treatment layer 304.Can utilize other inertia technologies to form the equivalent layer of plasma treatment layer 304, such as adopting laser treatment layer 302.
In step 208, the plasma treatment layer 304 that is arranged on the substrate 300 is exposed in the thermal anneal process, in one embodiment, substrate 300 is sent in the annealing chamber such as RTP process chamber 114, being exemplified as of the RTP process chamber that is fit to can (Applied Materials Inc) buys the CENTURA that obtains from Applied Materials TMRADIANCE TMThe RTP process chamber, and this substrate 300 is exposed in the thermal anneal process, because annealing chamber 114 is the same as with the nitrogen treatment chamber with deposition chambers being positioned on the cluster 100, thus can be not exposed to cluster between under the situation of the relevant surrounding environment of transmission substrate article on plasma body processing layer 304 anneal.
In an execution mode of annealing process, plasma treatment layer 304 can be heated to from about 600 degrees centigrade to about 1,200 degree centigrade temperature.In another embodiment, temperature can be from about 700 degrees centigrade to about 1,150 degree centigrade.In an execution mode again, plasma treatment layer 304 can be heated to from about 800 degrees centigrade to about 1,000 degree centigrade temperature.Thermal anneal process is different duration.In one embodiment, the duration of thermal anneal process can be from about 1 second to about 120 seconds.In another embodiment, the duration of thermal anneal process can be from about 2 seconds to about 60 seconds.In another execution mode, the duration of thermal anneal process can be from about 5 seconds to about 30 seconds.Usually, process chamber gas comprises at least a anneal gas, such as oxygen (O 2), ozone (O 3), oxygen atom (O), water (H 2O), nitric oxide (NO), nitrous oxide (N 2O), nitrogen dioxide (NO 2), dinitrogen pentoxide (N 2O 5), nitrogen (N 2), ammonia (NH 3), hydrazine (N 2H 4) and derivative or composition.Anneal gas can comprise nitrogen and at least a oxygen-containing gas such as oxygen.Process chamber can have the air pressure from about 5Torr to about 100Torr, for example, and about 10Torr.In an example of thermal anneal process, in oxygen atmosphere, with the temperature of substrate 200 be heated to about 1,050 degree centigrade about 15 seconds.In another example, during annealing process, in the gas of nitrogen that comprises the equal volume amount and oxygen, with substrate 300 temperature be heated to about 1,100 degree centigrade about 25 seconds.
Shown in Fig. 3 D, thermal anneal process becomes plasma treatment layer 304 dielectric material or retreats fire bed 306.Thermal anneal process has been repaired any damage that is caused by plasma and has been reduced the fixed charge (fixed charge) that retreats fire bed 306 in step 206.Dielectric material remains nitrogen concentration unbodied and that can have different range.In one embodiment, nitrogen concentration is to about 25 atomic percents from about 5 atomic percents.In another embodiment, nitrogen concentration be from about 10 atomic percents to about 20 atomic percents, for example about 15 atomic percents.Retreat fire bed 306 and can have different film thicknesses.In one embodiment, this thickness can be from about 5  to about 300 .In another embodiment, this thickness can be from about 10  to about 200 .In an execution mode again, this thickness can be from about 20  to about 100 .In another example, the thickness that retreats fire bed 306 can be from about 10  to about 60 , such as, from about 30  to about 40 .
In step 210, shown in Fig. 3 E, the dielectric layer 306 tops deposition grid layer 308 of annealing.Grid layer 308 can be formed by the material that is rotated for the premise equipment demand.Usually, grid layer 308 can form this technology such as MOCVD, LPCVD, PECVD, vapour phase epitaxy (Vapor Phase Epitaxy (VPE)), ALD or PVD by utilizing CVD technology.In one embodiment, grid layer 308 can be polysilicon, amorphous silicon or other materials that is fit to by utilizing LPCVD process chamber (being deposition chambers 110) deposition.A kind of suitable process chamber is can (AppliedMaterials Inc) buys the POLYGen process chamber obtain from Applied Materials.In another embodiment, grid layer 308 can be included in metal and/or the containing metal compound that deposits in ALD or the PVD process chamber.In an illustrative embodiments, grid layer 308 is formed by tantalum nitride silicon (TaSiN).In the execution mode that substitutes, grid layer 308 can comprise such as titanium (Ti), tantalum (Ta), rubidium (Ru), molybdenum metalloids such as (Mo), and/or such as tantalum nitride (TaN), titanium nitride (TiN), tantalum nitride silicon (TaSiN), titanium silicon nitride (TiSiN), ramet (TaC), TiAlN (TiAlN), rubidium tantalum (RuTa), molybdenum nitride (MoN), tungsten nitride similar containing metal compounds such as (WN).In another embodiment, grid layer 308 can comprise metal and/or containing metal compound, is coated with polysilicon or amorphous silicon in its over top.In an example, grid layer can be such as titanium (Ti), tantalum (Ta), rubidium (Ru), molybdenum metalloids such as (Mo), then is coated with polysilicon or amorphous silicon thereon.In another example, the grid layer can be such as can be such as titanium (Ti), tantalum (Ta), rubidium (Ru), molybdenum metalloids such as (Mo), and/or, next be coated with polysilicon layer or amorphous silicon layer above it such as tantalum nitride (TaN), titanium nitride (TiN), tantalum nitride silicon (TaSiN), titanium silicon nitride (TiSiN), ramet (TaC), TiAlN (TiAlN), rubidium tantalum (RuTa), molybdenum nitride (MoN), tungsten nitride similar containing metal compounds such as (WN).Can carry out all these metals in ALD, CVD or PVD process chamber, containing metal grid layer or silicon layer, described ALD, CVD or PVD process chamber are bought from Applied Materials and are obtained.Because deposition grid layer 308 in cluster 100, so in the surrounding environment that substrate 300 is not exposed to the transmission substrate is relevant between cluster with connected deposition chambers, nitrogen treatment chamber and thermal anneal process chamber.
Therefore, the invention provides the method that is used to prepare dielectric material, this dielectric material can be used in the grid manufacturing of field-effect transistor.This method permission is preparation and deposition of dielectric materials or electric stacked in integrated cluster, thereby has avoided owing to be exposed to the pollution that the transmission between the device-to-device of being correlated with by traditional manufacturing process causes.
Though more than described embodiments of the present invention, under the situation that does not depart from base region of the present invention, can design other execution modes of the present invention, and limit scope of the present invention by following claims.

Claims (28)

1. method that is used for forming on substrate at single cluster dielectric material comprises:
Cluster with a plurality of deposition chambers is provided;
On the substrate of first process chamber that is arranged in described cluster the deposition metallic oxide layer, wherein said metallic oxide layer be high dielectric constant material;
In second process chamber of described cluster, utilize the metallic oxide layer of inert, plasma PROCESS FOR TREATMENT;
The layer of the described containing metal oxidation of annealing in process in the 3rd process chamber of described cluster; And
In the 4th process chamber of described cluster the metallic oxide layer of described annealed processing on the metallic grid layer of deposition.
2. method according to claim 1 is characterized in that, before the described metallic oxide layer of deposition, the prerinse substrate is to remove oxide layer from described substrate in the prerinse process chamber of described cluster.
3. method according to claim 1 is characterized in that, also is included in to carry out before the inert, plasma technology, in cluster metallic oxide layer is exposed in the deposition post growth annealing.
4. method according to claim 2 is characterized in that, also is included in the described cluster substrate is sent to described first process chamber by loading the interlock process chamber from described prerinse process chamber.
5. method according to claim 1 is characterized in that, described metallic oxide layer comprise hafnium, tantalum, titanium, aluminium, zirconium, lanthanum and composition thereof at least one of them.
6. method according to claim 1 is characterized in that, the described described inertia etc. utilized comprises from the step of handling the containing metal oxide layer in body technology:
Form plasma by one of them the inert gas at least that comprises nitrogenous gas, argon gas, helium or xenon.
7. method according to claim 1 is characterized in that, the described step of the metallic oxide layer of inert gas plasma PROCESS FOR TREATMENT of utilizing comprises:
Apply from about 500 watts to about 3,000 watts power in described second process chamber, to keep plasma; And
Expose described metallic oxide layer and arrived about 5 minutes time in about 30 seconds.
8. method according to claim 1 is characterized in that, the step of the metallic oxide layer of described annealing also comprises:
Make described metallic oxide layer maintain from about 600 degrees centigrade to about 1,200 degree centigrade about 1 second to about 120 seconds duration.
9. method according to claim 8 is characterized in that, the step of the metallic oxide layer of described annealing also comprises:
Oxygen is fed in described the 3rd process chamber.
10. method according to claim 1 is characterized in that, the step of the metallic grid layer of described deposition also comprises:
Deposit the first metallic grid layer; And
The deposition second containing metal grid layer on the described first metallic grid layer.
11. method according to claim 10 is characterized in that, the described first containing metal grid layer be tantalum nitride, titanium nitride, tantalum nitride silicon, titanium silicon nitride, ramet, TiAlN, rubidium tantalum, molybdenum nitride or tungsten nitride at least one of them.
12. method according to claim 11 is characterized in that, the described second metallic grid layer is the metal level that is selected from the group of being made up of titanium, tantalum, rubidium and molybdenum.
13. method according to claim 11 is characterized in that, the described second metallic grid layer be tantalum nitride, titanium nitride, tantalum nitride silicon, titanium silicon nitride, ramet, TiAlN, rubidium tantalum, molybdenum nitride or tungsten nitride at least one of them.
14. method according to claim 10 is characterized in that, the step that described deposition second contains the grid layer of metal also comprises:
Depositing metal layers on the described second metallic grid layer.
15. method according to claim 14 is characterized in that, described metal level be titanium, tantalum, rubidium or molybdenum at least one of them.
16. method according to claim 1 is characterized in that, the step that described deposition contains the grid layer of metal also comprises:
Deposit spathic silicon layer on described metal-containing layer.
17. method according to claim 10 is characterized in that, the step of the described deposition second containing metal grid layer also comprises:
At the described second containing metal grid layer top deposit spathic silicon.
18. method according to claim 14 is characterized in that, the step of described depositing metal layers also comprises:
Deposit spathic silicon layer on the top of described metal level.
19. a method that is used for forming on substrate at single cluster dielectric material comprises:
Cluster with a plurality of deposition chambers is provided;
Prerinse substrate in described cluster;
The metallic oxide layer of deposition on the substrate in described cluster;
Utilizing the deposition after annealing to handle in described cluster anneals to described metallic oxide layer;
In described cluster, utilize the described metallic oxide layer of inert, plasma PROCESS FOR TREATMENT;
The metallic oxide layer of the described processing of annealing in described cluster;
In described cluster, on metallic oxide layer described annealing, that handle, deposit the first containing metal grid layer; And
In described cluster, on the described first metallic grid layer, deposit the second containing metal grid layer.
20. method according to claim 19 is characterized in that, also comprises:
In first processing chamber, carry out described annealing process and deposition containing metal oxide layer in same processing chamber.
21. method according to claim 19 is characterized in that, also comprises:
In first processing chamber, carry out annealing process and in first processing chamber of described cluster, the containing metal oxide layer after the described processing is annealed.
22. method according to claim 19 is characterized in that, the described first metallic grid layer be tantalum nitride, titanium nitride, tantalum nitride silicon, titanium silicon nitride, ramet, TiAlN, rubidium tantalum, molybdenum nitride or tungsten nitride at least one of them.
23. method according to claim 22 is characterized in that, the described second metallic grid is the metal level that is selected from the group of being made up of titanium, tantalum, rubidium and molybdenum.
24. method according to claim 19 is characterized in that, the described second metallic grid be tantalum nitride, titanium nitride, tantalum nitride silicon, titanium silicon nitride, ramet, TiAlN, rubidium tantalum, molybdenum nitride or tungsten nitride at least one of them.
25. method according to claim 19 is characterized in that, also comprises:
Depositing metal layers on the described second metallic grid.
26. method according to claim 25 is characterized in that, described metal level is one of them of titanium, tantalum, rubidium or molybdenum.
27. method according to claim 19 is characterized in that, also comprises:
In described cluster on the top of the described second metallic grid deposit spathic silicon layer.
28. method according to claim 25 is characterized in that, also comprises:
In described cluster on the metal level on the described second metallic grid deposit spathic silicon layer.
CNA2006101608908A 2005-12-09 2006-12-08 Method for fabricating a dielectric stack Pending CN1983522A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/298,553 US20060153995A1 (en) 2004-05-21 2005-12-09 Method for fabricating a dielectric stack
US11/298,553 2005-12-09

Publications (1)

Publication Number Publication Date
CN1983522A true CN1983522A (en) 2007-06-20

Family

ID=38165947

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2006101608908A Pending CN1983522A (en) 2005-12-09 2006-12-08 Method for fabricating a dielectric stack

Country Status (3)

Country Link
KR (1) KR20070061451A (en)
CN (1) CN1983522A (en)
TW (1) TW200723400A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102851733A (en) * 2012-09-04 2013-01-02 程凯 Preparation system and preparation method for gallium nitride base material and device thereof
CN104220651A (en) * 2012-03-28 2014-12-17 株式会社丰田中央研究所 Laminated substate of silicon single crystal and group iii nitride single crystal with off angle

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200373200A1 (en) 2019-05-24 2020-11-26 Applied Materials, Inc. Metal based hydrogen barrier

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104220651A (en) * 2012-03-28 2014-12-17 株式会社丰田中央研究所 Laminated substate of silicon single crystal and group iii nitride single crystal with off angle
CN104220651B (en) * 2012-03-28 2017-06-20 株式会社丰田中央研究所 The multilayer board of silicon single crystal and group III-nitride monocrystalline with drift angle
US9728609B2 (en) 2012-03-28 2017-08-08 Kabushiki Kaisha Toyota Chuo Kenkyusho Layered substrate with a miscut angle comprising a silicon single crystal substrate and a group-III nitride single crystal layer
CN102851733A (en) * 2012-09-04 2013-01-02 程凯 Preparation system and preparation method for gallium nitride base material and device thereof
CN102851733B (en) * 2012-09-04 2016-08-17 苏州晶湛半导体有限公司 Gallium nitride-based material and the preparation system of device and preparation method

Also Published As

Publication number Publication date
KR20070061451A (en) 2007-06-13
TW200723400A (en) 2007-06-16

Similar Documents

Publication Publication Date Title
US20060153995A1 (en) Method for fabricating a dielectric stack
US8361910B2 (en) Pretreatment processes within a batch ALD reactor
US7601648B2 (en) Method for fabricating an integrated gate dielectric layer for field effect transistors
US6544900B2 (en) In situ dielectric stacks
US7910497B2 (en) Method of forming dielectric layers on a substrate and apparatus therefor
US11139383B2 (en) Titanium aluminum and tantalum aluminum thin films
US20060062917A1 (en) Vapor deposition of hafnium silicate materials with tris(dimethylamino)silane
US7202166B2 (en) Surface preparation prior to deposition on germanium
US8119210B2 (en) Formation of a silicon oxynitride layer on a high-k dielectric material
KR20200069223A (en) Method of forming a structure including silicon nitride on titanium nitride and structure formed using the method
CN111199871A (en) Method for forming metal silicate film and semiconductor device structure
US20060019033A1 (en) Plasma treatment of hafnium-containing materials
TW201903847A (en) Low resistivity film containing molybdenum
TW201833374A (en) A method for passivating a surface of a semiconductor and related systems
US20080014759A1 (en) Method for fabricating a gate dielectric layer utilized in a gate structure
CN101298663A (en) Methods for depositing a high-k dielectric material using chemical vapor deposition process
KR20090027162A (en) Modulating the stress of poly-crystaline silicon films and surrounding layers through the use of dopants and multi-layer silicon films with controlled crystal structure
WO2005096358A1 (en) A silicon germanium surface layer for high-k dielectric integ ration
TW202247469A (en) Mosfet gate engineerinng with dipole films
CN1983522A (en) Method for fabricating a dielectric stack
KR20240006002A (en) Conformal doped amorphous silicon as nucleation layer for metal deposition
US8163343B2 (en) Method of forming an aluminum oxide layer
US20190148140A1 (en) Dry and wet etch resistance for atomic layer deposited tio2 for sit spacer application
TWI830087B (en) Treatments to enhance material structures
TWI841680B (en) Methods for depositing a hafnium lanthanum oxide film on a substrate by a cyclical deposition process in a reaction chamber

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20070620