CN1982910A

CN1982910A - Method for testing EFlash serial interface based on selective bit number

Info

Publication number: CN1982910A
Application number: CN 200510111429
Authority: CN
Inventors: 陈凯华
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2005-12-13
Filing date: 2005-12-13
Publication date: 2007-06-20
Anticipated expiration: 2025-12-13
Also published as: CN100523849C

Abstract

A method for testing EF lash serial interface based on selectable digit includes inputting digit selection signal to built-in storage unit by serial interface test circuit, controlling level of digit selection signal by serial interface command sent out by serial interface test circuit, applying X 16 digit mode to carry out writing operation of the chip.

Description

Based on the optional EFlash serial ports of figure place method of testing

Technical field

The present invention relates to a kind of method of testing of SIC (semiconductor integrated circuit), particularly relate to a kind of based on the optional EFlash serial ports of figure place method of testing.

Background technology

The control signal of Flash (flash memory) has sheet choosing (CS), reads effectively (OE), with imitating (WE), address wire (ADDRESS), data line (DATA), test pattern (TMEN) etc.Must be when test with these PIN (pin) according to certain time sequence, place required level, finish the various operations to Flash, so these PIN must be linked to each other with the passage of tester completely in common design, chip will need a lot of PAD (chip pin) like that.Serial ports design can be reduced the PAD number of Embedded NVM (embedded non-volatile memory) greatly, improves the output of single piece of silicon chip non-defective unit.But the time can reach original test purpose completely again in test, the control signal of entire chip is required just than higher.In the serial port circuit design, chip desired control signal, is latched in the register under the cooperation of system clock by single I/O passage.Then by outside trigger pip, convert the setting in the register level of setting to, place on each pin of Embedded NVM.In test process, find for the chip that designs based on serial port circuit, owing to need to guarantee the quality of chip, need a large amount of write operations that implementation is undertaken by byte to entire chip repeatedly, so just in whole test process, occupied the quite most test duration; If can reduce the number of times of write operation, can reach the purpose of test again, this part test duration just can be compressed greatly so.Wherein figure place optional * just have among the EFlash IP (embedded flash memory nuclear) of 8 and * 16 (or * 32) and select the position of figure place to select signal.For example: if this piece IP (nuclear) is applied to 16 system in common design, the position selects signal to put height with regard to perseverance; Be applied to 8 systems, it is low that the position selects signal to put with regard to perseverance.For the IP that is applied to 8 systems, can only be that a unit carries out full sheet write operation just so, obviously than the time of having spent more one times by 16 bit manipulations according to 8.

Summary of the invention

The technical problem to be solved in the present invention provides that a kind of it can shorten the test duration based on the optional EFlash serial ports of figure place method of testing, reduces testing cost, improves output capacity.

For solving the problems of the technologies described above, the present invention is based on the optional EFlash serial ports of figure place method of testing is to adopt following technical scheme to realize, the position selects signal to input to built-in storage unit by the serial ports test circuit, the mode of * 16 (than long numbers) is adopted in the serial port command control that the level that signal is selected in the position is sent by the serial ports test circuit when carrying out full sheet write operation.

Adopt method of the present invention, can shorten for about 1/3 test duration on original basis, in whole test process, the minimizing test duration means has reduced testing cost, has improved the competitiveness of product.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is existing based on the optional EFlash serial ports of figure place method of testing synoptic diagram;

Fig. 2 the present invention is based on the optional EFlash serial ports of figure place method of testing synoptic diagram.

Embodiment

In existing EFlash serial ports method of testing, usually can be according to the application requirements of system, it is high or low to select signal to be fixed as the position.When test, just can only carry out write operation like this according to selected figure place.In the memory capacity NVM (non-volatility memorizer) that is 512K, if adopt * 8 to write full sheet and need just can finish full sheet write operation 64K time.

The present invention is based on the optional EFlash serial ports of figure place method of testing, is on existing method basis, selects signal to discharge to serial ports input control this position, and the mode of employing * 16 is controlled in the process of carrying out full sheet write operation.In original design, the test control signal of chip is converted by the register of serial ports test circuit, as long as utilize the redundant digit of this register to connect on the selected control system signal that puts in place among the present invention, trigger by external control signal then, the pin of all chip under test is placed required level, just can reach the purpose of remarkable shortening test duration, reduce testing cost.

For example, select signal to import the position,, when carrying out full sheet write operation, adopt * 16 mode,, saved the time of half than existing method as long as 32K time just can be finished for the memory capacity NVM that is 512K by serial port command.

Fig. 1 is existing based on the optional EFlash serial ports of figure place method of testing synoptic diagram, trigger the data latching on the I/O passage in the register of serial ports test circuit by the CLK edge, by trigger pip these level are added on the control signal of embedded storage unit then.The serial ports test circuit is enabled effectively by logical circuit, the position can be selected simultaneously signal place the needed level of system represent * 16 or * 8 systems.

Fig. 2 the present invention is based on the optional EFlash serial ports of figure place method of testing synoptic diagram, the difference of it and existing method just is, originally selected signal to be imported by the outside by the serial ports test circuit by the position of logical circuit control, the position of logical circuit originally selects signal and other control signals by the conductively-closed of MUX (selector switch) circuit.

Claims

1, a kind of based on the optional EFlash serial ports of figure place method of testing, it is characterized in that: the position selects signal to input to built-in storage unit by the serial ports test circuit, * 16 mode is adopted in the serial port command control that the level that signal is selected in the position is sent by the serial ports test circuit when carrying out full sheet write operation.

2, according to claim 1 based on the optional EFlash serial ports of figure place method of testing, it is characterized in that: the redundant digit of the register of described serial ports test circuit is connected on the selected control system signal that puts in place, trigger by external control signal then, the pin of all chip under test is placed required level.