CN108519937A - Interface circuit test method, system, readable storage medium storing program for executing and mainboard - Google Patents
Interface circuit test method, system, readable storage medium storing program for executing and mainboard Download PDFInfo
- Publication number
- CN108519937A CN108519937A CN201810300943.4A CN201810300943A CN108519937A CN 108519937 A CN108519937 A CN 108519937A CN 201810300943 A CN201810300943 A CN 201810300943A CN 108519937 A CN108519937 A CN 108519937A
- Authority
- CN
- China
- Prior art keywords
- level
- pin
- memory
- mainboard
- interface circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
A kind of interface circuit test method of present invention offer, system, readable storage medium storing program for executing and mainboard, the mainboard are electrically connected with a memory, and the interrupt pin and reset pin of the mainboard respectively connect the address choice pin of a memory, the method includes：Rule is set according to preset level, sets the pin level of the interrupt pin and the reset pin to predetermined level；Corresponding current address access request is combined with current level to memory transmission, and the current level is combined as the combination that the current level of the interrupt pin and the reset pin sorts according to preset rules；When being respectively received the response that the memory is made for each address access request, determine that the interface circuit test of the mainboard is normal.Interface circuit test method in the present invention realizes the interface circuit automatically to mainboard and is detected, efficient.
Description
Technical field
The present invention relates to electronic communication technology field, more particularly to a kind of interface circuit test method, system, readable storage
Medium and mainboard.
Background technology
Along with mobile phone products in the quick universal of the whole world, the demand of mobile phone constantly increases.In order to make mobile phone towards height
End, high quality trend development, PCBA (the Pinter Circuit Board Assembly, i.e. fit on of current mobile phone
The circuit board of various electronic devices) mainboard has to before manufacture by detecting layer by layer, to ensure that follow-up mobile phone can be transported normally
Row.
Wherein, one of the conventional item for being detected as mainboard factory testing of touch screen interface circuit, the detection can ensure to touch
Whether the function of touch screen interface circuit is normal.The touch screen interface circuit of mobile phone is generally logical by power supply interface (PWR), I2C at present
Communication interface (containing SDA and SCL), interrupt pin (INT) and reset pin (RESET) composition, mainly judge that these connect when detecting
Controllably whether mouth circuit is with the presence or absence of short circuit and breaking phenomena, and reset with interrupt pin.
In the prior art, for current interface circuit test mainly by manually completing, efficiency is low, and labor intensity is big,
And manually decision errors are big, influence the accuracy of test.
Invention content
Based on this, the object of the present invention is to provide a kind of interface circuit test method, system, readable storage medium storing program for executing and masters
Plate, to improve the testing efficiency of interface circuit.
A kind of interface circuit test method according to the ... of the embodiment of the present invention is applied to a mainboard, the mainboard and a storage
Device is electrically connected, and the interrupt pin and reset pin of the mainboard respectively connect the address choice pin of a memory, institute
The method of stating includes：
Rule is set according to preset level, the pin level of the interrupt pin and the reset pin is set as pre-
If level；
Corresponding current address access request, the current level combination are combined with current level to memory transmission
The combination sorted according to preset rules for the current level of the interrupt pin and the reset pin；
When being respectively received the response that the memory is made for each address access request, the mainboard is determined
Interface circuit test is normal.
In addition, a kind of interface circuit test method according to the above embodiment of the present invention, can also have following additional
Technical characteristic：
Further, described that according to preset level, rule is set, by drawing for the interrupt pin and the reset pin
The step of foot level is set as predetermined level include：
Obtain the predetermined level combination of preset number, the queueing discipline and the current level group of the predetermined level combination
The queueing discipline of conjunction is consistent；
Sequentially the level by each predetermined level combination is correspondingly arranged to the interrupt pin and the reset pin.
Further, corresponding current address access request is combined with current level to memory transmission described
After step, further include：
Judge that the memory whether is received in preset time is answered for what the current address access request was made
It answers；
If so, being correspondingly arranged the level of next predetermined level combination to the interrupt pin and the reset
Pin.
Further, it is described obtain preset number predetermined level combination the step of include：
Preset high level and preset low level are subjected to permutation and combination, to obtain the described default of the preset number
Level combinations.
Further, it is visited for the current address whether the judgement receives the memory in preset time
After asking the step of response that request is made, further include：
If it is not, then judging whether the current address access request is that the access of address for the first time sent out to the memory is asked
It asks；
If it is not, then send out abnormal prompt information, to prompt at least one in the interrupt pin and the reset pin
It is a to there is exception.
Further, corresponding current address access request is combined with current level to memory transmission described
After step, further include：
When any address access request does not receive the response of the memory, the unique mark letter of the mainboard is obtained
Breath, and the unique identification information is sent to background server.
Further, after the normal step of the interface circuit test of the determination mainboard, further include：
Test regular prompt information is sent out, to prompt the interface circuit test of the mainboard normal；
Cancel the pin level of the interrupt pin and reset pin setting.
A kind of interface circuit test system according to the ... of the embodiment of the present invention is applied to a mainboard, the mainboard and a storage
Device is electrically connected, and the interrupt pin and reset pin of the mainboard respectively connect the address choice pin of a memory, institute
Stating interface circuit test system includes：
Level setup module, for rule to be arranged according to preset level, by the interrupt pin and the reset pin
Pin level be set as predetermined level；
Request sending module is asked for combining corresponding current address access with current level to memory transmission
It asks, the current level is combined as the group that the current level of the interrupt pin and the reset pin sorts according to preset rules
It closes；
Normal determining module, for working as the response for being respectively received the memory and being made for each address access request
When, determine that the interface circuit test of the mainboard is normal.
The present invention also proposes a kind of computer readable storage medium, is stored thereon with computer program, which is handled
Such as above-mentioned interface circuit test method is realized when device executes.
The present invention also proposes that a kind of mainboard, the mainboard are electrically connected with a memory, the interrupt pin of the mainboard and multiple
Position pin respectively connects the address choice pin of a memory, and the mainboard includes memory, processor and storage
On a memory and the computer program that can run on a processor, the processor are realized when executing described program as above-mentioned
Interface circuit test method.
Above-mentioned interface circuit test method, system, readable storage medium storing program for executing and mainboard are interrupted and reset pin by changing
Level state is arranged the level state of two address choice pins of memory, and then changes the access address of memory, so
The address visiting demand under current level state is sent to memory afterwards, and detects whether to obtain the response of memory, due to depositing
Reservoir will generate corresponding access address for each level combinations of two address choice pins, if the address sent every time
Access request can receive the response of memory, then memory normal response can be made by representing the pin level being often arranged,
Reflect that reset pin and the interrupt pin of mainboard are controllable, and there is no the situations of short circuit, open circuit for interface circuit, simultaneously also
It can reflect that main board power supply and I2C communications are normal, system will send out test regular prompt information at this time, to prompt the interface of mainboard
Circuit test is normal.Therefore, the interface circuit test method, system, readable storage medium storing program for executing and mainboard are realized by program
Automatically the interface circuit of mainboard is detected, it is efficient, hand labor intensity is reduced, and compared to artificial judgement, accurately
Property higher.
Description of the drawings
Fig. 1 is the structural schematic diagram of mainboard touch screen interface circuit；
Fig. 2 is the flow chart of the interface circuit test method in first embodiment of the invention；
Fig. 3 is the connection diagram of the mainboard and memory in first embodiment of the invention；
Fig. 4 is the flow chart of the interface circuit test method in second embodiment of the invention；
Fig. 5 is the structure chart of the interface circuit test system in third embodiment of the invention；
Fig. 6 is the structural schematic diagram of the mainboard in fourth embodiment of the invention.
Main element symbol description：
| Level setup module | 11 | Request sending module | 12 |
| Normal determining module | 13 | Level acquiring unit | 111 |
| Level setting unit | 112 | Response judgment module | 14 |
| Judgment module is set | 15 | Obtain subelement | 1111 |
| Ask judgment module | 16 | Abnormal prompt module | 17 |
| Identifier acquisition module | 18 | Regular prompt module | 19 |
| Level cancels module | 20 | Mainboard | 100 |
| Memory | 200 | Memory | 20 |
| Processor | 10 | Computer program | 30 |
Detailed description below will be further illustrated the present invention in conjunction with above-mentioned attached drawing.
Specific implementation mode
To facilitate the understanding of the present invention, below with reference to relevant drawings to invention is more fully described.In attached drawing
Give several embodiments of the present invention.But the present invention can realize in many different forms, however it is not limited to this paper institutes
The embodiment of description.On the contrary, purpose of providing these embodiments is make it is more thorough and comprehensive to the disclosure.
It should be noted that when element is referred to as " being fixedly arranged on " another element, it can be directly on another element
Or there may also be elements placed in the middle.When an element is considered as " connection " another element, it can be directly connected to
To another element or it may be simultaneously present centering elements.Term as used herein " vertical ", " horizontal ", " left side ",
" right side " and similar statement are for illustrative purposes only.
Unless otherwise defined, all of technologies and scientific terms used here by the article and belong to the technical field of the present invention
The normally understood meaning of technical staff is identical.Used term is intended merely to description tool in the description of the invention herein
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term " and or " used herein includes one or more phases
Any and all combinations of the Listed Items of pass.
Each embodiment can be applicable in mainboard as shown in Figure 1 below, and Fig. 1 shows that the touch screen of the mainboard connects
Mouth circuit diagram, including power supply interface (PWR), I2C communication interfaces (containing SDA and SCL), interrupt pin (INT) and reset pin
(RESET)。
This neighborhood technique personnel are not it should be understood that touch screen interface circuit shown in Fig. 1 is constituted to mainboard interface
The restriction of circuit, the interface circuit of mainboard can also either combine certain interfaces or not than illustrating more or fewer interfaces
Same interface arrangement.
Referring to Fig. 2, the interface circuit test method showing in first embodiment of the invention, is applied to as described in Figure 1
Mainboard in, including step S01 to step S03.
Before testing, the electric connection of mainboard and a memory can be established according to connection type as shown in Figure 3, so that main
The address choice pin A0 of the interrupt pin connection memory of plate, another address choice of the reset pin connection memory of mainboard
Pin A1, and the I2C communication interfaces of mainboard and memory is made to interconnect.Memory uses EEPROM in the present embodiment
(Electrically Erasable Programmable Read-Only Memory, the band read-only storage of electric erazable programmable
Device) chip.
In addition to this, mainboard can be also put into test platform, which can have power supply, display test knot
The functions such as fruit.
When detecting enabling signal rule is arranged according to preset level, by the interrupt pin and institute in step S01
The pin level for stating reset pin is set as predetermined level.
Wherein, the enabling signal can be power on signal, click signal, switching signal, or detect some hardware or
The insertion of program can also be the test initiation command etc. that test platform is sent to mainboard.
In addition, can apply a voltage to interruption and reset pin to interruption and reset pin setting pin level, it be somebody's turn to do
Voltage can be high level voltage and be alternatively low level voltage, can specifically be set in test program.
Step S02 combines corresponding current address access request with current level to memory transmission, described current
The combination that level combinations sort for the current level of the interrupt pin and the reset pin according to preset rules.
Wherein, the preset rules can be the sequence of interrupt pin level in preceding, the posterior number of reset pin level sequence
According to queueing discipline.For example, when the current level of interrupt pin is 1, the current level of reset pin is 0, then according to described default
The current level of rule compositor is combined as (1,0).
In addition it is also necessary to, it is noted that be based on the level group of interface connection type shown in Fig. 3, interruption and reset pin
It closes consistent with the level combinations of AO and A1 always.
It should be pointed out that according to the characteristic of memory it is found that memory is for the two address choice pins of AO and A1
Each level combinations will generate corresponding access address.It for example, should when the level combinations of (AO, A1) are (1,0)
The device first address of memory is 0xA3, and when the level combinations of (AO, A1) are (1,1), the device first address of the memory is
0xA7 can specifically consult the address choice pin of memory and the mapping table of access address.
Based on above-mentioned association, once the level of interruption and reset pin determines that system would know that the current of memory
Access address is sent to memory to generate current address access request.
In addition, current address access request can be to read data in the current address of memory.
Step S03 determines institute when being respectively received the response that the memory is made for each address access request
The interface circuit test for stating mainboard is normal.
It should be pointed out that since memory will production for each level combinations of two address choice pins AO and A1
Raw corresponding access address represents and is often arranged if the address access request sent every time can receive the response of memory
Pin level can make memory normal response, that is, reflect that the reset pin of mainboard and interrupt pin are controllable, and connect
There is no the situations of short circuit, open circuit for mouth circuit, while can also reflect main board power supply and I2C communications normally, and system is automatic at this time
Judge that the interface circuit test of the mainboard is normal.
To sum up, the interface circuit test method in the above embodiment of the present invention is interrupted and reset pin by changing
Level state is arranged the level state of two address choice pins of memory, and then changes the access address of memory, so
The address visiting demand under current level state is sent to memory afterwards, and detects whether to obtain the response of memory, due to depositing
Reservoir will generate corresponding access address for each level combinations of two address choice pins, if the address sent every time
Access request can receive the response of memory, then memory normal response can be made by representing the pin level being often arranged,
Reflect that reset pin and the interrupt pin of mainboard are controllable, and there is no the situations of short circuit, open circuit for interface circuit, simultaneously also
It can reflect that main board power supply and I2C communications are normal, system will send out test regular prompt information at this time, to prompt the interface of mainboard
Circuit test is normal.Therefore, the interface circuit test method, system, readable storage medium storing program for executing and mainboard are realized by program
Automatically the interface circuit of mainboard is detected, it is efficient, hand labor intensity is reduced, and compared to artificial judgement, accurately
Property higher.
Referring to Fig. 4, the interface circuit test method showing in second embodiment of the invention, is applied to a mainboard, institute
It states mainboard to be electrically connected with a memory, the interrupt pin and reset pin of the mainboard respectively connect the ground of a memory
Location selects pin (specific connection type can refer to circuit diagram shown in Fig. 3), and the interface circuit test method includes step S11
To step S20.
Step S11 obtains the predetermined level combination of preset number when detecting enabling signal.
Wherein, the predetermined level is combined as the level combinations that two pin levels sort according to preset rules, this is default
Rule defines the setting object of the level in each predetermined level combination.
In the present embodiment, the preset number is four, and the interface circuit test method is used preset height
Level and preset low level carry out the mode of permutation and combination, to obtain 4 predetermined levels combinations, respectively (0,0),
(1,0), (0,1) and (1,1), wherein 1 represents preset high level, 0 represents preset low level.
The level of each predetermined level combination is sequentially correspondingly arranged to the interrupt pin and described by step S12
Reset pin.
In the specific implementation, the combination of above-mentioned 4 predetermined levels can be ranked up according to preset queueing discipline, with
Obtain the priority setting sequence of 4 predetermined level combinations.
Step S13 combines corresponding current address access request with current level to memory transmission.
Wherein, the current level is combined as the current level of the interrupt pin and the reset pin according to described pre-
If the combination of rule compositor, the as predetermined level combination of current setting.For example, if the predetermined level of current setting is combined as
(1,0), then current level combination is (1,0).
It should be pointed out that since the primary interruption of every setting and the pin level of reset pin, current level combination are deposited
It can change, therefore a pin level is often set, system can send to memory and combine corresponding work as with current level
Preceding address access request.
Step S14 judges that the memory whether is received in preset time is directed to the current address access request
The response made.
Wherein, the memory is received in preset time made for the current address access request when determining
Response when, represent memory normal response, then follow the steps S15 to step S17；Do not receive in preset time when determining
When the response made to the memory for the current address access request, then representing the interface circuit of mainboard, there are different
Often, S18 is thened follow the steps to step S20.
Step S15, judges whether all predetermined level combinations have been arranged to the interrupt pin and the reset
Pin.
Wherein, draw to the interrupt pin and the reset when determining all predetermined levels combinations and be not arranged
It when foot, returns and executes the step S12, the level of next predetermined level combination is correspondingly arranged and is drawn to the interruption
Foot and the reset pin；It has been arranged to the interrupt pin and the reset when determining all predetermined level combinations
When pin, represents 4 groups of predetermined level combinations and be arranged to interrupt pin and reset pin, and the address access sent every time is asked
The response for receiving memory is asked, S16 is thened follow the steps.
Step S16 determines that the interface circuit test of the mainboard is normal, and sends out test regular prompt information.
It should be understood that when 4 groups of predetermined levels combine the ground for being respectively provided with to interrupt pin and reset pin, and sending every time
Location access request receives the response of memory, then representing 4 level settings can make memory change corresponding access
Address, and mainboard communicates normally the access of memory, represents reset pin and interrupt pin is controllable, and interface circuit is not deposited
In the situation of short circuit, open circuit, while it can also reflect that main board power supply and I2C communications are normal.
In the specific implementation, the mainboard can be established before testing and tests the electric connection of terminal, so that when test
When normal, which can be shown by the test terminal.
Step S17 cancels the pin level of the interrupt pin and reset pin setting.
In the specific implementation, once touch screen interface circuit test is normal, that is, next production work can be put by representing the mainboard
Sequence flows in order to avoid the pin electrification of mainboard in producing line, after testing is complete, cancels the pin electricity being arranged before this immediately
It is flat, it is ensured that production safety.
Step S18 obtains the unique identification information of the mainboard, and the unique identification information is sent to background service
Device.
It should be understood that when there is response that access request is unable to get memory, interface circuit existing defects are represented,
Concretely：There is phenomena such as short circuit, open circuit, abnormal electrical power supply in interface circuit；Reset pin and interrupt pin are uncontrolled, cause
Storage address can not follow change；Or I2C communication abnormalities.Above-mentioned abnormal conditions can influence the normal work of mainboard, in order to
The mainboard of the exception is tracked, system is by the unique identification information for obtaining the mainboard (unique code of such as mainboard) and after being recorded
In platform server.
Step S19 judges whether the current address access request is that the address for the first time sent out to the memory accesses
Request.
Wherein, it is not that the access of address for the first time sent out to the memory is asked when determining the current address access request
When asking, S20 is thened follow the steps.
Step S20 sends out abnormal prompt information, to prompt at least one in the interrupt pin and the reset pin
It is a to there is exception.
It should be understood that not being the address for the first time sent out to the memory when determining the current address access request
When access request, represent the address access request that sends out before this, the memory can normal response, interface electricity can be excluded in this way
There is short circuit, breaking, abnormal electrical power supply and I2C communication abnormalities defect in road, be based on this, system can determine interrupt pin and reset
Pin at least one of is worked as uncontrolled, and sends out the abnormal prompt information automatically.
Another aspect of the present invention also provides a kind of interface circuit test system, described to please refer to Fig. 5, show the present invention the
Interface circuit test system in three embodiments is applied to a mainboard, and the mainboard is electrically connected with a memory, the mainboard
Interrupt pin and reset pin respectively connect the address choice pin of a memory, the interface circuit test system packet
It includes：
Level setup module 11, for when detecting enabling signal, rule being arranged according to preset level, in described
The pin level of disconnected pin and the reset pin is set as predetermined level；
Request sending module 12 is asked for combining corresponding current address access with current level to memory transmission
It asks, the current level is combined as the group that the current level of the interrupt pin and the reset pin sorts according to preset rules
It closes；
Normal determining module 13 is answered for that ought be respectively received the memory for what each address access request was made
When answering, determine that the interface circuit test of the mainboard is normal.
Further, the level setup module 11 includes：
Level acquiring unit 111, the predetermined level for obtaining preset number combine, the arrangement of the predetermined level combination
The regular queueing discipline combined with the current level is consistent；
The level of each predetermined level combination is sequentially correspondingly arranged and draws to the interruption by level setting unit 112
Foot and the reset pin.
Further, the interface circuit test system further includes：
Response judgment module 14, for judging that whether receiving the memory in preset time is directed to the current position
The response that location access request is made；
Judgment module 15 is set, the memory is received in preset time for the current position for working as to determine
When the response that location access request is made, judge whether all predetermined level combinations have been arranged to the interrupt pin
With the reset pin；
When determining all predetermined levels combinations and not being arranged to the interrupt pin and the reset pin,
The level of next predetermined level combination is correspondingly arranged to the interrupt pin and described by the level setting unit 112
Reset pin；And
When determining all predetermined levels combinations and being arranged to the interrupt pin and the reset pin, institute
It states normal determining module 13 and sends out the test regular prompt information.
Further, the level acquiring unit 111 includes：
Subelement 1111 is obtained, for preset high level and preset low level to be carried out permutation and combination, to obtain
State the predetermined level combination of preset number.
Further, the interface circuit test system further includes：
Judgment module 16 is asked, the memory is not received in preset time for described current for working as to determine
When the response that address access request is made, judge whether the current address access request is to be sent out for the first time to the memory
Address access request.
Abnormal prompt module 17 is not sent out for that ought determine the current address access request to the memory
For the first time when the access request of address, abnormal prompt information is sent out, to prompt in the interrupt pin and the reset pin extremely
Few one has exception.
Further, the interface circuit test system further includes：
Identifier acquisition module 18, for when any address access request does not receive the response of the memory, obtaining
The unique identification information of the mainboard, and the unique identification information is sent to background server.
Further, the interface circuit test system further includes：
Regular prompt module 19 is normally carried for after determining that the interface circuit test of the mainboard is normal, sending out test
Show information；
Level cancels module 20, for after sending out the test regular prompt information, cancelling the interrupt pin and institute
State the pin level of reset pin setting.
The present invention also proposes a kind of computer readable storage medium, is stored thereon with computer program, which is handled
Such as above-mentioned interface circuit test method is realized when device executes.
Another aspect of the present invention also proposes a kind of mainboard, please refers to Fig. 6, the master showing in fourth embodiment of the invention
Plate 100, the mainboard 100 are electrically connected with a memory 200, the mainboard 100 according in Fig. 3 circuit connecting mode and institute
The connection of memory 200 is stated, the mainboard 100 includes memory 20, processor 10 and is stored on memory 20 and can locate
The computer program 30 run on reason device 10, the processor 10 realize that above-mentioned interface circuit such as is surveyed when executing described program 30
Method for testing.
Wherein, the memory 200 uses EEPROM storage chips.
It will be understood by those skilled in the art that in flow charts indicate or logic described otherwise above herein and/or
Step can implement for example, being considered the order list of the executable instruction for realizing logic interface circuit
In any computer-readable medium, for instruction execution mainboard, device or equipment (such as computer based mainboard including place
Manage device mainboard or other can be from instruction execution mainboard, device or equipment instruction fetch and the mainboard executed instruction) use, or knot
It closes these instruction execution mainboard, device or equipment and uses.For the purpose of this specification, " computer-readable medium " can be any
It can include, store, communicate, propagate, or transport program is held for instruction execution mainboard, device or equipment or in conjunction with these instructions
Row mainboard, device or equipment and the device used.
The more specific example (non-exhaustive list) of computer-readable medium includes following：It is connected up with one or more
Electrical connection section (electronic device), portable computer diskette box (magnetic device), random access memory (RAM), read-only memory
(ROM), erasable edit read-only storage (EPROM or flash memory), fiber device and portable optic disk is read-only deposits
Reservoir (CDROM).In addition, computer-readable medium can even is that the paper that can print described program on it or other are suitable
Medium, because can be for example by carrying out optical scanner to paper or other media, then into edlin, interpretation or when necessary with it
His suitable method is handled electronically to obtain described program, is then stored in computer storage.
It should be appreciated that each section of the present invention can be realized with hardware, software, firmware or combination thereof.Above-mentioned
In embodiment, multiple steps or method can use the software that storage executes in memory and by suitable instruction execution mainboard
Or firmware is realized.It, and in another embodiment, can be under well known in the art for example, if realized with hardware
Any one of row technology or combination thereof are realized：With the logic gate for realizing logic interface circuit to data-signal
The discrete logic of circuit, the application-specific integrated circuit with suitable combinational logic gate circuit, programmable gate array (PGA),
Field programmable gate array (FPGA) etc..
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
Centainly refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
One or more embodiments or example in can be combined in any suitable manner.
Several embodiments of the invention above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
Cannot the limitation to the scope of the claims of the present invention therefore be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the guarantor of the present invention
Protect range.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of interface circuit test method is applied to a mainboard, which is characterized in that the mainboard is electrically connected with a memory,
The interrupt pin and reset pin of the mainboard respectively connect the address choice pin of a memory, the method packet
It includes：
Rule is set according to preset level, sets the pin level of the interrupt pin and the reset pin to default electricity
It is flat；
Corresponding current address access request is combined with current level to memory transmission, the current level is combined as institute
State the combination that the current level of interrupt pin and the reset pin sorts according to preset rules；
When being respectively received the response that the memory is made for each address access request, the interface of the mainboard is determined
Circuit test is normal.
2. interface circuit test method according to claim 1, which is characterized in that described be arranged according to preset level is advised
Then, the step of setting the pin level of the interrupt pin and the reset pin to predetermined level include：
The predetermined level combination of preset number is obtained, what the queueing discipline that the predetermined level combines was combined with the current level
Queueing discipline is consistent；
Sequentially the level by each predetermined level combination is correspondingly arranged to the interrupt pin and the reset pin.
3. interface circuit test method according to claim 2, which is characterized in that it is described to the memory send with
After current level combines the step of corresponding current address access request, further include：
Judge that the memory whether is received in preset time is directed to the response that the current address access request is made；
Draw to the interrupt pin and the reset if so, being correspondingly arranged the level of next predetermined level combination
Foot.
4. interface circuit test method according to claim 2, which is characterized in that the default electricity for obtaining preset number
Putting down the step of combining includes：
Preset high level and preset low level are subjected to permutation and combination, to obtain the predetermined level of the preset number
Combination.
5. interface circuit test method according to claim 3, which is characterized in that be in preset time in the judgement
It is no receive the step of response that the memory is made for the current address access request after, further include：
If it is not, then judging whether the current address access request is the address access request for the first time sent out to the memory；
If it is not, then send out abnormal prompt information, deposited with prompting the interrupt pin and the reset pin at least one of to work as
In exception.
6. interface circuit test method according to claim 1, which is characterized in that it is described to the memory send with
After current level combines the step of corresponding current address access request, further include：
When any address access request does not receive the response of the memory, the unique identification information of the mainboard is obtained,
And the unique identification information is sent to background server.
7. interface circuit test method according to claim 1, which is characterized in that in the interface of the determination mainboard
After the normal step of circuit test, further include：
Send out test regular prompt information；
Cancel the pin level of the interrupt pin and reset pin setting.
8. a kind of interface circuit test system is applied to a mainboard, which is characterized in that the mainboard is electrically connected with a memory,
The interrupt pin and reset pin of the mainboard respectively connect the address choice pin of a memory, the interface circuit
Test system includes：
Level setup module, for rule to be arranged according to preset level, by drawing for the interrupt pin and the reset pin
Foot level is set as predetermined level；
Request sending module, for combining corresponding current address access request, institute with current level to memory transmission
It states current level and is combined as the combination that the current level of the interrupt pin and the reset pin sorts according to preset rules；
Normal determining module, for when the response for being respectively received the memory and making for each address access request,
Determine that the interface circuit test of the mainboard is normal.
9. a kind of computer readable storage medium, is stored thereon with computer program, which is characterized in that the program is held by processor
The method as described in claim 1-7 is any is realized when row.
10. a kind of mainboard, which is characterized in that the mainboard is electrically connected with a memory, the interrupt pin of the mainboard and reset
Pin respectively connects the address choice pin of a memory, and the mainboard includes memory, processor and is stored in
On memory and the computer program that can run on a processor, the processor realize such as claim when executing described program
Any methods of 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810300943.4A CN108519937A (en) | 2018-04-04 | 2018-04-04 | Interface circuit test method, system, readable storage medium storing program for executing and mainboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810300943.4A CN108519937A (en) | 2018-04-04 | 2018-04-04 | Interface circuit test method, system, readable storage medium storing program for executing and mainboard |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108519937A true CN108519937A (en) | 2018-09-11 |
Family
ID=63431475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810300943.4A Withdrawn CN108519937A (en) | 2018-04-04 | 2018-04-04 | Interface circuit test method, system, readable storage medium storing program for executing and mainboard |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108519937A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116644011A (en) * | 2023-05-31 | 2023-08-25 | 合芯科技有限公司 | Quick identification method, device and equipment of I2C equipment and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1595367A (en) * | 2004-07-06 | 2005-03-16 | 天津百维软件科技有限公司 | A method for detecting PC Card interface data wire and address wire |
| CN1982910A (en) * | 2005-12-13 | 2007-06-20 | 上海华虹Nec电子有限公司 | Method for testing EFlash serial interface based on selective bit number |
| CN102169154A (en) * | 2011-01-13 | 2011-08-31 | 深圳创维－Rgb电子有限公司 | A method and a device for testing an HDMI |
| CN103176094A (en) * | 2011-12-22 | 2013-06-26 | 希姆通信息技术（上海）有限公司 | Method for testing PIN of LCD (Liquid Crystal Display) interface of module |
| US20140058699A1 (en) * | 2012-08-27 | 2014-02-27 | Fujitsu Limited | Information processing apparatus, test data generating apparatus, and test data generating method |
| CN104198911A (en) * | 2014-06-24 | 2014-12-10 | 航天科工深圳（集团）有限公司 | Test method and circuit for chip pin of DTU (Date Transfer Unit) |
| CN104516800A (en) * | 2013-09-27 | 2015-04-15 | 国际商业机器公司 | Method, system and relative circuit system for diagnosing server mainboard |
| CN106199394A (en) * | 2016-07-26 | 2016-12-07 | 中国船舶重工集团公司第七二四研究所 | RAM chip engineering detecting method based on FPGA |
-
2018
- 2018-04-04 CN CN201810300943.4A patent/CN108519937A/en not_active Withdrawn
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1595367A (en) * | 2004-07-06 | 2005-03-16 | 天津百维软件科技有限公司 | A method for detecting PC Card interface data wire and address wire |
| CN1982910A (en) * | 2005-12-13 | 2007-06-20 | 上海华虹Nec电子有限公司 | Method for testing EFlash serial interface based on selective bit number |
| CN102169154A (en) * | 2011-01-13 | 2011-08-31 | 深圳创维－Rgb电子有限公司 | A method and a device for testing an HDMI |
| CN103176094A (en) * | 2011-12-22 | 2013-06-26 | 希姆通信息技术（上海）有限公司 | Method for testing PIN of LCD (Liquid Crystal Display) interface of module |
| US20140058699A1 (en) * | 2012-08-27 | 2014-02-27 | Fujitsu Limited | Information processing apparatus, test data generating apparatus, and test data generating method |
| CN104516800A (en) * | 2013-09-27 | 2015-04-15 | 国际商业机器公司 | Method, system and relative circuit system for diagnosing server mainboard |
| CN104198911A (en) * | 2014-06-24 | 2014-12-10 | 航天科工深圳（集团）有限公司 | Test method and circuit for chip pin of DTU (Date Transfer Unit) |
| CN106199394A (en) * | 2016-07-26 | 2016-12-07 | 中国船舶重工集团公司第七二四研究所 | RAM chip engineering detecting method based on FPGA |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116644011A (en) * | 2023-05-31 | 2023-08-25 | 合芯科技有限公司 | Quick identification method, device and equipment of I2C equipment and storage medium |
| CN116644011B (en) * | 2023-05-31 | 2023-11-03 | 合芯科技有限公司 | Quick identification method, device and equipment of I2C equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0116553B1 (en) | Method and apparatus for bus fault location | |
| CN108564104A (en) | Product defects detection method, device, system, server and storage medium | |
| CN104502743A (en) | Automatic testing system and method for power management product based on Labview | |
| CN110213258A (en) | Abnormity monitoring method and device for vehicle CAN bus and computer equipment | |
| CN105301450A (en) | Distribution network fault automatic diagnosis method and system | |
| JP4582038B2 (en) | Software automatic test program, software automatic test apparatus, and software automatic test method | |
| CN108519937A (en) | Interface circuit test method, system, readable storage medium storing program for executing and mainboard | |
| CN109257742A (en) | The number of writing method and the number of writing equipment | |
| CN108519935A (en) | Board test method, device, readable storage medium storing program for executing and computer equipment | |
| CN102981956A (en) | Method, and device for establishing overlay symbol table, method and device and program modulation system for establishing and searching overlay symbol table, and program modulation system | |
| CN111142889A (en) | eMMC automatic volume production method, device, storage medium and electronic equipment | |
| CN102480383B (en) | A kind of log information message processing method and device | |
| CN107341074B (en) | A kind of abnormal restorative procedure of upgrading upgrades abnormal prosthetic device and intelligent terminal | |
| US6745146B1 (en) | Automated test system and method for device having circuit and ground connections | |
| US7076739B2 (en) | Data computation apparatus and method for using the data computation apparatus for adjustment of electronic controller | |
| CN111432078A (en) | System for judging code number abnormity | |
| CN112711858B (en) | FMEA-MSR analysis method and device | |
| CN110177271A (en) | A kind of method and device improving video camera focusing checkability | |
| CN109557453A (en) | A kind of more main control chip identifying processing method and system | |
| CN105975370A (en) | Method and device for testing | |
| DE112022002045T5 (en) | ADAPTIVE MULTIPROTOCOL USB CHARGING | |
| CN108335721A (en) | A kind of method and system of real-time detection of random access memory address line failure | |
| US20200242751A1 (en) | Enhanced automatic cosmetic grading | |
| CN106951276A (en) | The software upgrading of multi-controller and address conflict detecting method, device | |
| CN108549608A (en) | A kind of the UI sectional drawings test method and system of APP |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20180911 |