CN1972135A - Tracking receiver digital demodulation apparatus - Google Patents

Tracking receiver digital demodulation apparatus Download PDF

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Publication number
CN1972135A
CN1972135A CNA2006101020756A CN200610102075A CN1972135A CN 1972135 A CN1972135 A CN 1972135A CN A2006101020756 A CNA2006101020756 A CN A2006101020756A CN 200610102075 A CN200610102075 A CN 200610102075A CN 1972135 A CN1972135 A CN 1972135A
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pin
signal
digital
converter
output
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CN100488066C (en
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李强
闵洁
李靖
赵蔚兰
杨锁强
林兴隆
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CETC 54 Research Institute
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CETC 54 Research Institute
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Abstract

This invention discloses one trace receiver digital demodulation device, which can be used as single channel and impulse trace receiver and comprises modulator, integral device, down transducer, monitor, amplifier, digital demodulator unit, wherein, the it processes control modulator and digital down transducer through digital demodulator unit and then gets signal log power, signal to noise proportion, position error voltage and forward error voltage.

Description

Tracking receiver digital demodulation apparatus
Technical field
The present invention relates to a kind of tracking receiver digital demodulation apparatus of the communications field, be specially adapted to make single channel monopulse track receiver or stepping track receiver in the antenna servo tracking system.
Background technology
Track receiver in the current antenna servo tracking system mainly contains two kinds: Mono-pulse Tracking Receiver and stepping track receiver.The stepping track receiver mainly is to detect the power of input beacon signal and be converted to direct current signal, and Mono-pulse Tracking Receiver needs orientation, the pitch error angle signal that detected beacon signals forms in antenna feed and is converted to direct current signal.The test section of these two kinds of receivers is at present main adopts the signal to noise ratio of method when improving restituted signal of the superhet pll lock input beacon signal of analog circuit form, and coherent demodulation goes out the amplitude and the error signal of input signal then.Adopt the method for the superhet phase-locked link demodulation of analog circuit form exist equipment interoperability poor, go into that lock is slow, equipment is complicated, debugging and make difficulty, the more high many shortcomings of cost.
Summary of the invention
The objective of the invention is to avoid the weak point in the above-mentioned background technology and provide a kind of promptly can be used for stepping track receiver demodulating equipment can be used for the Mono-pulse Tracking Receiver demodulating equipment, based on the tracking receiver digital demodulation apparatus of Digital Signal Processing, the present invention also have integrated degree height, volume little, make and debug simple, stable and reliable for performance, characteristics such as versatility is good.
The object of the present invention is achieved like this: it comprises modulator 1, mixer 2, low-converter 3, digital demodulation unit 4, watch-dog 5, amplifier 6, wherein external and signal A input mixer 2 go into end 1 pin, difference signal B input modulator 1 go into end 1 pin, modulator 1 multiplies each other the low-frequency square-wave signal of input difference signal B and amplifier 6 outputs and forms the modulation difference signal, output 3 pin of modulator 1 are connected with end 2 pin of going into of mixer 2, mixer 2 closes the Lu Chengyi road to the modulation difference signal from modulator 1 input with external with signal A, output 3 pin of mixer 2 are connected with end 1 pin of going into of low-converter 3, the port one pin of watch-dog 5 is connected with port 3 pin of low-converter 3, low-converter 3 makes the signal after mixer 2 closes the road finish the selection frequency conversion of frequency input signal under the frequency control signal control of watch-dog 5 inputs, amplify, export intermediate-freuqncy signal after the filtering, low-converter 3 is sent to watch-dog 5 with working state signal, output 2 pin of low-converter 3 are connected with end 1 pin of going into of digital demodulation unit 4, port 2 pin of digital demodulation unit 4 are connected with port 2 pin of watch-dog 5, digital demodulation unit 4 is finished under the control signal control of watch-dog 5 inputs and demodulate the direct-flow error voltage signal from intermediate-freuqncy signal, with the signal that demodulates by the output of output port 4 pin behind the signal power signal, digital demodulation unit 4 also will export digital signal and the internal state signal is sent to watch-dog 5, watch-dog 5 will show from the output digital signal and the internal state signal of digital demodulation unit 4 inputs, digital demodulation unit 4 outputs 3 pin are connected with end 1 pin of going into of amplifier 6, what the low-frequency square-wave signal that digital demodulation unit 4 produces outputed to modulator 1 after amplifier 6 amplifies goes into end 2 pin, and modulator 1 is finished the modulation of error originated from input signal.
The present invention can also reach by following measure:
Digital demodulation unit 4 of the present invention comprises dummy source 7, switch 8, band pass filter 9, voltage control Amplifier 10, crystal oscillator 11, modulus converter A/D 12, digital down converter 13, memory chip FLASH 14, digital to analog converter D/A 15, digital signal processor 16, watchdog circuit 17, wherein switch 8 goes out analog if signal that end 2 pin input intermediate-freuqncy signal and dummy source 7 go out the input of end 2 pin with low-converter 3 and goes out at digital signal processor 16 to select one tunnel intermediate-freuqncy signal to output to band pass filter 9 under the control of peripheral circuit DMAC output control signal of end 1 pin to go into to hold 1 pin, band pass filter 9 is finished the anti-aliasing filter of input signal, the signal input voltage control Amplifier 10 of aliasing filtering is gone into end 1 pin, voltage control Amplifier 10 is adjusted amplitude output signal in going out of digital to analog converter D/A 15 under the control of end 2 pin output voltage signals and is inputed to modulus converter A/D 12, modulus converter A/D 12 goes out the synchronous analog-to-digital conversion and the bandpass sampling of finishing down the input analog signal of the synchronizing signal of end 1 pin output at crystal oscillator 11, modulus converter A/D 12 goes out to hold the digital signal after 3 pin will be sampled to output to digital down converter 13 and goes into end 2 pin, modulus converter A/D 12 goes out end 4 pin the saturation pulse signal is outputed to the timer circuit TIMERO that digital signal processor 16 is gone into end 3 pin, timer circuit TIMERO carries out the constant duration counting to the saturation pulse signal, the central processor CPU of digital signal processor 16 is gone into end 1 pin according to the count value of pre-defined algorithm and timer circuit TIMERO by what its external memory interface circuit EMIF that comes in and goes out end 2 pin inputed to digital to analog converter D/A 15, digital to analog converter D/A 15 goes out the gain of end 2 pin output control voltage control voltage control Amplifier 10, digital down converter 13 goes out to hold the output digital signal of 3 pin to receive synchronously with modulus converter A/D 12 down in the synchronizing signal that crystal oscillator 11 goes out the output of end 2 pin synchronously, the external memory interface circuit EMIF of digital signal processor 16 discrepancy ends 2 pin is connected with end 5 pin of going into of digital down converter 13, digital down converter 13 goes out end 3 pin output digital signal to modulus converter A/D 12 and carries out digital quadrature mixing under digital signal processor 16 is come in and gone out the output control signal control of holding 2 pin, filtering, down-sampled processing, digital down converter 13 will be handled the back data and go out end 4 pin synchronous serial interfaces by it and deliver to digital signal processor 16 and go into the multichannel buffered serial port McBSP0 of end 7 pin and carry out data sync and receive, the synchronous serial interface output frame synchronizing signal that digital down converter 13 goes out end 3 pin inputs to the multichannel buffered serial port McBSP0 that digital signal processor 16 is gone into end 6 pin, go into the timer circuit TIMER1 of end 5 pin, timer circuit TIMER1 goes out end 4 pin and goes into end 1 pin with dummy source 7 respectively, amplifier 6 is gone into end 1 pin, watchdog circuit 17 is gone into end 2 pin and is connect, the central processor CPU of digital signal processor 16 is by synchronous down the produce low-frequency square-wave signal of pre-defined algorithm control timer circuit TIMER1 in frame synchronizing signal, low-frequency square-wave signal goes out end 4 pin by it and inputs to dummy source 7 respectively, amplifier 6, watchdog circuit 17, dummy source 7 utilizes low-frequency square-wave signal to produce analog if signal to go out end 2 pin by it and export switch 8 to and go into end 2 pin, watchdog circuit 17 detects low-frequency square-wave signal and goes out to hold 2 pin to be input to the reset circuit RESET that digital signal processor 16 is gone into end 9 pin so that produce reset signal when improper resetting by it, low-frequency square-wave signal is exaggerated and is input to modulator 1 after device 6 amplifies, the multichannel buffered serial port McBSP1 of digital signal processor 16 discrepancy ends 10 pin comes in and goes out with watch-dog 5 and holds 2 pin to be connected, digital signal processor 16 obtains external control information from watch-dog 5, watch-dog 5 obtains demodulating unit state and dateout from digital signal processor 16, digital signal processor 16 is connected with memory chip FLASH14 discrepancy end 1 pin by the external memory interface circuit EMIF of its end 2 pin of coming in and going out, digital signal processor 16 is finished bootstrapping and will be needed to preserve when resetting writing data into memory chip FLASH 14 preservations, RAM data field C in the digital signal processor 16 or RAM data field D are used for storing data, controller circuitry DMA in the digital signal processor 16 is continual under predetermined set to move storage that multichannel buffered serial port McBSP0 receives to data field C or data field D, realize receiving the uninterrupted reception and the processing of data, central processor CPU in the digital signal processor 16 is with the error signal that demodulates, power signal, signal-noise ratio signal is input to digital to analog converter D/A 15 by its external memory interface circuit EMIF that comes in and goes out end 2 pin and goes into to hold 1 pin to be converted to analog signal, go out the output of end 3 pin 0 end by digital to analog converter D/A 15, central processor CPU in the digital signal processor 16 is exported by the transmission mouth that it goes out the multichannel buffered serial port McBSP0 of end 8 pin the signal data and the state that demodulate with serial data form 0 end, the clock circuit in the digital signal processor 16 provides its synchronizing clock signals.
The present invention compares with background technology has following advantage:
1. the present invention adopts the analog demodulator device that the digital demodulation unit 4 based on large-scale digital ic replaces based on small scale integrated circuit, has that integrated degree height, volume are little, a manufacturing and debug characteristics simple, stable and reliable for performance.
2. circuit of the present invention has software, the general distinguishing feature of hardware, hardware designs promptly can be used for the single channel monopulse track receiver also can be used for the stepping track receiver, the stepping receiver is the part of single channel monopulse track receiver on software, so versatility is good.
Description of drawings
Fig. 1 is the electric functional-block diagram of the embodiment of the invention.
Fig. 2 is the electric functional-block diagram of the digital demodulation unit 4 of the embodiment of the invention.
Embodiment
With reference to Fig. 1, Fig. 2, the present invention includes modulator 1, mixer 2, low-converter 3, digital demodulation unit 4, watch-dog 5, amplifier 6.Fig. 1 is the electric functional-block diagram of the embodiment of the invention, embodiment presses Fig. 1 connection line, its modulator 1 uses commercially available 0～π phase modulator of different frequency range as modulator according to the application band different mining, its effect is the suppressed carrier modulation of finishing difference signal, and difference signal is separated on frequency domain with signal.Mixer 2 is made of commercially available two mixers of different frequency range according to the application band different mining, and its effect is to synthesize one road signal with signal and modulation difference signal.Amplifier 6 adopts the MAX319 analog switch to make, and is installed in digital demodulation unit 4 printed boards, and its effect is that square-wave signal is amplified.In the stepping track receiver, do not need the demodulation difference signal, so embodiment modulator 1, mixer 2, amplifier 6 do not need in the stepping track receiver, needn't install.Low-converter 3 mainly is made of local oscillator and frequency conversion, filtering, amplifier section, according to the low-converter of application band different mining with different frequency range, its effect is the signal to noise ratio of selecting the beacon signal frequency conversion under the control of watch-dog 5, be enlarged into intermediate-freuqncy signal and other signal raising beacon signal of filtering from wideband input signal, and embodiment adopts homemade down-converter circuit to make.Watch-dog 5 is made of liquid crystal display, button, indicator light, monitoring microprocessor and peripheral chip etc., it mainly acts on and comprises demonstration and control track receiver internal state, data, man-machine interface is provided, receives extraneous control etc., embodiment adopts homemade monitor circuit to make.
The main effect of digital demodulation unit 4 of the present invention comprises from input and demodulates beacon signal power, beacon signal signal to noise ratio, error voltage and output the analog if signal, and square-wave modulation signal is provided in Mono-pulse Tracking Receiver.It comprises dummy source 7, switch 8, band pass filter 9, voltage control Amplifier 10, crystal oscillator 11, modulus converter A/D 12, digital down converter 13, memory chip FLASH 14, digital to analog converter D/A15, digital signal processor (being called for short DSP) 16, watchdog circuit 17, Fig. 2 is the electric functional-block diagram of digital demodulation unit 4 of the present invention, and embodiment presses Fig. 2 connection line.Wherein dummy source 7 provides analog if signal, digital demodulation unit 4 utilizes analog if signal to realize self check, embodiment adopts commercially available SA602 chip and 70MHz crystal to make, the vibration of SA602 chip internal oscillator is on external 70MHz crystal frequency, the multiplier that utilizes chip internal is to the square-wave signal of outside input and the 70MHz oscillator signal formation modulated-analog signal that multiplies each other, modulated-analog signal and oscillator signal addition formation analog if signal; As stepping trace demodulation device the time, the input square wave can be disconnected and only export the 70MHz oscillator signal.The effect of switch 8 is to select the output of one tunnel intermediate-freuqncy signal from two-way input intermediate-freuqncy signal, embodiment adopts commercially available TQ2 relay and 74HC04 driving gate circuit production, provides enough drive currents to make relay TQ2 connect input intermediate-freuqncy signal or analog if signal by the driving gate circuit.Band pass filter 9 its effects are the frequency parts that in the filtering input signal A/D bandpass sampling caused aliasing, can also improve the signal to noise ratio that is input to the A/D signal in addition, and embodiment adopts commercially available Surface Acoustic Wave Filter CF70-0.8A to make.Voltage control Amplifier 10 effects are to make in the best transition level range of signal at modulus converter A/D 12 that is input to A/D12 at adjustment amplitude output signal under the control of analog to digital converter D/A15 output voltage signal, embodiment adopts commercially available AD8367 chip manufacturing, the yield value (logarithm) of AD8367 chip when the data of utilizing the log gain characteristic of AD8367 chip and digital to analog converter D/A15 being set can calculate work accurately.Crystal oscillator 11 effects provide the synchronizing clock signals of modulus converter A/D 12, digital down converter 13, and embodiment adopts commercially available QS33.00 clock to shake and driving gate circuit 74LVC04 makes, and crystal oscillator 11 operating frequencies are 33MHz.Modulus converter A/D 12 effect is with the 33MHz crystal oscillator signal analog if signal of 70MHz centre frequency that goes to sample, and obtains the digital signal of 4MHz centre frequency, and embodiment adopts commercially available AD9235 digital to analog converter making.Digital down converter 13 embodiment adopt commercially available AD6620 digital down converter to make, its effect is by the digital controlled oscillator frequency of AD6620 chip internal is set, digital controlled oscillator output becomes the zero center frequency signal with the digital signal quadrature mixing of input 4MHz centre frequency, exports by synchronous serial interface with lower sampling rate through three grades of filtering and three grades of down-sampled backs.Memory chip FLASH14 embodiment adopts commercially available SST39VF040 chip manufacturing, be connected on CE1 space among the EMIF of digital signal processor 16, its effect is the working procedure of 64kbyte storage digital signal processor 16 before the SST39VF040 chip internal, these programs are moved the program's memory space of digital signal processor 16 by bootstrap approach by storage digital signal processor 16 when resetting, required fixed data during 16 operations of the other parts of SST39VF040 chip storage digital signal processor is moved the data space of digital signal processor 16 when the reset routine initialization.Analog to digital converter D/A15 embodiment adopts commercially available DAC8412F chip manufacturing, its effect is to be connected on CE0 space among the EMIF of digital signal processor 16, chip internal four road D/A are operated in+5v ,-5v voltage under, one road D/A output is as the gain controlling of AD8367 chip, one road D/A output is as receiving and the output of signal logarithm power, and two-way D/A is used as error voltage output or is used as signal-noise ratio signal output and frequency offset signals output in the stepping track receiver in Mono-pulse Tracking Receiver.Digital signal processor 16 embodiment adopt commercially available TMS320C6204 chip configuration to form, its effect is the core of digital demodulation unit 4, and major function comprises the synchronous serial data of the gain of regulating the AD8367 chip, the AD6620 chip that produces the CE3 space of square-wave modulation signal, control switch 8 selection input signals, configuration EMIF, demodulated output data, the output of reception AD6620 chip and therefrom demodulates desired data etc.Watchdog circuit 17 effects produce reset signal when being electrification reset and abnormal operation, and embodiment adopts commercially available ADM706R and 74LVC08 chip manufacturing.
Concise and to the point operation principle of the present invention is as follows:
And if signal is u 1(t): u 1(t)=Acos (ω t)
Difference signal u 2(t): u 2(t)=and μ Acos (ω t+ +γ)
Wherein A is and signal amplitude, μ be the difference signal amplitude relatively and the normalized value of signal amplitude, ω is the signal angular frequency,  is that the error voltage synthesis phase is poor, γ be before closing the road difference signal with respect to the additional channel phase shift of signal.
If modulation signal c (t) is:
c ( t ) = + 1 0 &le; 2 n&pi; - &pi; / 2 &le; &Omega;t < 2 n&pi; + &pi; / 2 - 1 2 n&pi; + &pi; / 2 &le; &Omega;t < 2 n&pi; + 3 &pi; / 2 - - - ( 1 )
N is 0,1,2,3 in the formula, 4 ... etc. positive integer, Ω is the angular frequency of square-wave signal, multiplies each other with difference signal with modulation signal c (t) in modulator 1, draw the back difference signal that multiplies each other easily and do not contain carrier frequency component, therefore can be in mixer 2 with and signal be combined into one the tunnel, the signal that closes behind the road is:
u 3(t)＝Acosωt+μAcos(ωt++γ)×c(t)
Process modulus converter A/D 12 conversions again, digital down converter 13 conversion after frequency conversion amplification, the filtering in low-converter 3, the overall channel gain is made as b, and frequency becomes Low Medium Frequency and is made as λ, and sample frequency is F, and signal form is:
u 4(t)＝bAcosλt+bAμcos(λt++γ)×c(t) (3)
If the data that current McBSP0 receives by the dma controller of digital signal processor 16 under predetermined set the continual RAM memory of moving digital signal processor 16 2 nPoint data reception area C, CPU is to 2 of RAM memory simultaneously nThe data that received among the point data district D are carried out the signal demodulation process, finish and export back wait data field C in the data processing of data field D and receive 2 nPoint data, C receives 2 in the data field nTransfer dma controller continual storage that McBSP0 is received under predetermined set in the time of point data to and start simultaneously the data of data field C are carried out the signal demodulation process to data field D, so circulation realizes the uninterrupted reception and the processing of signal.
To each sampling obtain 2 nPoint data is carried out windowing, carries out 2 then nPoint rapid fourier change (FFT) can be obtained initial phase ψ with signal, the initial phase ψ of difference signal according to special algorithm from FFT result i, the difference signal amplitude relatively and the normalized value μ of signal amplitude, behind the FFT with signal power P s, noise average power spectrum density P behind the FFT n
In Mono-pulse Tracking Receiver, the azimuthal error voltage U AZ, the pitch error voltage U ELBe calculated as follows:
U AZ＝μcos(ψ-ψ i-γ AZ′) (4)
U EL＝μcos(ψ-ψ i-γ EL′) (5)
ψ-ψ wherein iBe the difference signal that calculates by this FFT result with and signal differ γ ' AZBe azimuthal channel difference correction value, γ ' when desirable AZ=γ, γ ' ELBe pitch channel difference correction value, γ ' when desirable EL=γ+90 °.
With the signal to noise ratio S/N of signal be:
S / N = 10 log ( P s P n ) ( dBc / Hz ) - - - ( 6 )
If mixer 2, low-converter 3, band pass filter 9, the gain of digital down converter 13 hardware and the windowing of digital signal processor 16, its overall gain of gain sum of FFT are fixed value x (dB), if voltage control Amplifier 10 gain setting values are ydB, then import and signal power P SumFor:
P sum＝10logP s-x-y (dBm) (7)
In the stepping track receiver, there is not difference signal, need not modulate and close the road yet, a demand goes out (6) formula and (7) formula result gets final product.
The embodiments of the invention mounting structure is as follows: digital demodulation unit 4 and amplifier 6 are installed in a 135 * 122mm 26 layers of printed board on, top layer and bottom are signals layer, components and parts are installed, the intermediate layer be one deck power supply, a layer signal, one deck simulation ground and power supply, one deck digitally, to numeral and analog power isolation filter, simulate ground and digitally separately and by magnetic bead be connected, the shielding box shielding is partly adopted in simulation except that A/D12, digital down converter 13, DSP16, both can realize the spatial separation of electromagnetic signal, make things convenient for the earth terminal nearby of radiofrequency signal again, avoided the phase mutual interference of radiofrequency signal at cabinet inside.Low-converter 3 is according to the different differences of installing of application band, and embodiment and watch-dog 5, digital demodulation unit 4 are installed in the same cabinet.Modulator 1, mixer 2 are installed on the antenna as Mono-pulse Tracking Receiver the time, and modulator 1, mixer 2, amplifier 6 need not be installed as the stepping track receiver time, assembly cost invention thus.

Claims (2)

1. tracking receiver digital demodulation apparatus, it comprises modulator (1), mixer (2), low-converter (3), watch-dog (5), amplifier (6), it is characterized in that: also comprise digital demodulation unit (4), wherein external and signal A input mixer (2) go into end 1 pin, difference signal B input modulator (1) go into end 1 pin, modulator (1) multiplies each other the low-frequency square-wave signal of input difference signal B and amplifier (6) output and forms the modulation difference signal, output 3 pin of modulator (1) are connected with end 2 pin of going into of mixer (2), mixer (2) closes the Lu Chengyi road to the modulation difference signal from modulator (1) input with external with signal A, output 3 pin of mixer (2) are connected with end 1 pin of going into of low-converter (3), the port one pin of watch-dog (5) is connected with port 3 pin of low-converter (3), low-converter (3) makes the signal after mixer (2) closes the road finish the selection frequency conversion of frequency input signal under the frequency control signal control of watch-dog (5) input, amplify, export intermediate-freuqncy signal after the filtering, low-converter (3) is sent to watch-dog (5) with working state signal, output 2 pin of low-converter (3) are connected with end 1 pin of going into of digital demodulation unit (4), port 2 pin of digital demodulation unit (4) are connected with port 2 pin of watch-dog (5), digital demodulation unit (4) is finished under the control signal control of watch-dog (5) input and demodulate the direct-flow error voltage signal from intermediate-freuqncy signal, with the signal that demodulates by the output of output port 4 pin behind the signal power signal, digital demodulation unit (4) also will export digital signal and the internal state signal is sent to watch-dog (5), watch-dog (5) will show from the output digital signal and the internal state signal of digital demodulation unit (4) input, digital demodulation unit (4) output 3 pin are connected with end 1 pin of going into of amplifier (6), what the low-frequency square-wave signal that digital demodulation unit (4) produces outputed to modulator (1) after amplifier (6) amplifies goes into end 2 pin, and modulator (1) is finished the modulation of error originated from input signal.
2. a kind of tracking receiver digital demodulation apparatus according to claim 1, it is characterized in that: digital demodulation unit (4) comprises dummy source (7), switch (8), band pass filter (9), voltage control Amplifier (10), crystal oscillator (11), modulus converter A/D (12), digital down converter (13), memory chip FLASH (14), digital to analog converter D/A (15), digital signal processor (16), watchdog circuit (17), wherein switch (8) with low-converter (3) go out analog if signal that end 2 pin input intermediate-freuqncy signal and dummy source (7) go out the input of end 2 pin go out at digital signal processor (16) end 1 pin peripheral circuit DMAC output control signal control down selection one tunnel intermediate-freuqncy signal output to band pass filter (9) and go into to hold 1 pin, band pass filter (9) is finished the anti-aliasing filter of input signal, the signal input voltage control Amplifier (10) of aliasing filtering is gone into end 1 pin, voltage control Amplifier (10) is adjusted amplitude output signal in going out of digital to analog converter D/A (15) under the control of end 2 pin output voltage signals and is inputed to modulus converter A/D (12), modulus converter A/D (12) goes out the synchronous analog-to-digital conversion and the bandpass sampling of finishing down the input analog signal of the synchronizing signal of end 1 pin output at crystal oscillator (11), modulus converter A/D (12) goes out to hold the digital signal after 3 pin will be sampled to output to digital down converter (13) and goes into end 2 pin, modulus converter A/D (12) goes out end 4 pin the saturation pulse signal is outputed to the timer circuit TIMERO that digital signal processor (16) is gone into end 3 pin, timer circuit TIMERO carries out the constant duration counting to the saturation pulse signal, the central processor CPU of digital signal processor (16) is gone into end 1 pin according to the count value of pre-defined algorithm and timer circuit TIMERO by what its external memory interface circuit EMIF that comes in and goes out end 2 pin inputed to digital to analog converter D/A (15), digital to analog converter D/A (15) goes out the gain of end 2 pin output control voltage control voltage control Amplifiers (10), digital down converter (13) goes out to hold the output digital signal of 3 pin to receive synchronously with modulus converter A/D (12) down in the synchronizing signal that crystal oscillator (11) goes out the output of end 2 pin synchronously, the external memory interface circuit EMIF of digital signal processor (16) discrepancy end 2 pin is connected with end 5 pin of going into of digital down converter (13), digital down converter (13) goes out end 3 pin output digital signal to modulus converter A/D (12) and carries out digital quadrature mixing under digital signal processor (16) is come in and gone out the output control signal control of holding 2 pin, filtering, down-sampled processing, digital down converter (13) will be handled the back data and go out end 4 pin synchronous serial interfaces by it and deliver to digital signal processor (16) and go into the multichannel buffered serial port McBSPO of end 7 pin and carry out data sync and receive, the synchronous serial interface output frame synchronizing signal that digital down converter (13) goes out end 3 pin inputs to the multichannel buffered serial port McBSPO that digital signal processor (16) is gone into end 6 pin, go into the timer circuit TIMER1 of end 5 pin, timer circuit TIMER1 goes out end 4 pin and goes into end 1 pin with dummy source (7) respectively, amplifier (6) is gone into end 1 pin, watchdog circuit (17) is gone into end 2 pin and is connect, the central processor CPU of digital signal processor (16) is by synchronous down the produce low-frequency square-wave signal of pre-defined algorithm control timer circuit TIMER1 in frame synchronizing signal, low-frequency square-wave signal goes out end 4 pin by it and inputs to dummy source (7) respectively, amplifier (6), watchdog circuit (17), dummy source (7) utilizes low-frequency square-wave signal to produce analog if signal to go out end 2 pin by it and export switch (8) to and go into end 2 pin, watchdog circuit (17) detects low-frequency square-wave signal and goes out to hold 2 pin to be input to the reset circuit RESET that digital signal processor (16) is gone into end 9 pin so that produce reset signal when improper resetting by it, low-frequency square-wave signal is exaggerated and is input to modulator (1) after device (6) amplifies, the multichannel buffered serial port McBSP1 of digital signal processor (16) discrepancy end 10 pin comes in and goes out with watch-dog (5) and holds 2 pin to be connected, digital signal processor (16) obtains external control information from watch-dog (5), watch-dog (5) obtains demodulating unit state and dateout from digital signal processor (16), digital signal processor (16) is connected with memory chip FLASH (14) discrepancy end 1 pin by the external memory interface circuit EMIF of its end 2 pin of coming in and going out, digital signal processor (16) is finished bootstrapping and will be needed to preserve when resetting writing data into memory chip FLASH (14) preservation, RAM data field C in the digital signal processor (16) or RAM data field D are used for storing data, controller circuitry DMA in the digital signal processor (16) is continual under predetermined set to move storage that multichannel buffered serial port McBSPO receives to data field C or data field D, realize receiving the uninterrupted reception and the processing of data, central processor CPU in the digital signal processor (16) is with the error signal that demodulates, power signal, signal-noise ratio signal is input to digital to analog converter D/A (15) by its external memory interface circuit EMIF that comes in and goes out end 2 pin and goes into to hold 1 pin to be converted to analog signal, go out the output of end 3 pin 0 end by digital to analog converter D/A (15), central processor CPU in the digital signal processor (16) is exported by the transmission mouth that it goes out the multichannel buffered serial port McBSPO of end 8 pin the signal data and the state that demodulate with serial data form 0 end, the clock circuit in the digital signal processor (16) provides its synchronizing clock signals.
CNB2006101020756A 2006-10-25 2006-10-25 Tracking receiver digital demodulation apparatus Expired - Fee Related CN100488066C (en)

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CN102104438A (en) * 2009-12-21 2011-06-22 Nxp股份有限公司 Full spectrum time shifting device
CN105119612A (en) * 2015-07-08 2015-12-02 泉州市琪祥电子科技有限公司 RF gain adjusting circuit
CN106443592A (en) * 2016-06-24 2017-02-22 西安电子科技大学 Single channel receiver signal tracking system based on digital phase-locked loop and single channel receiver signal tracking method based on digital phase-locked loop
CN106761711A (en) * 2016-12-26 2017-05-31 中石化江汉石油工程有限公司 A kind of downhole instrument multifunctional communication control system
CN108988932A (en) * 2018-06-28 2018-12-11 中国人民解放军63698部队 Digital tracking receiver emulation platform based on MATLAB

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104438A (en) * 2009-12-21 2011-06-22 Nxp股份有限公司 Full spectrum time shifting device
CN105119612A (en) * 2015-07-08 2015-12-02 泉州市琪祥电子科技有限公司 RF gain adjusting circuit
CN106443592A (en) * 2016-06-24 2017-02-22 西安电子科技大学 Single channel receiver signal tracking system based on digital phase-locked loop and single channel receiver signal tracking method based on digital phase-locked loop
CN106761711A (en) * 2016-12-26 2017-05-31 中石化江汉石油工程有限公司 A kind of downhole instrument multifunctional communication control system
CN106761711B (en) * 2016-12-26 2024-02-02 中石化江汉石油工程有限公司 Multifunctional communication control system for downhole instrument
CN108988932A (en) * 2018-06-28 2018-12-11 中国人民解放军63698部队 Digital tracking receiver emulation platform based on MATLAB

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