CN1971895A - Chip buried base plate encapsulation structure - Google Patents
Chip buried base plate encapsulation structure Download PDFInfo
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- CN1971895A CN1971895A CNA2005101234002A CN200510123400A CN1971895A CN 1971895 A CN1971895 A CN 1971895A CN A2005101234002 A CNA2005101234002 A CN A2005101234002A CN 200510123400 A CN200510123400 A CN 200510123400A CN 1971895 A CN1971895 A CN 1971895A
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- bearing bed
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- base plate
- loading plate
- encapsulating structure
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- 238000004806 packaging method and process Methods 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 6
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- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 4
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- 239000004643 cyanate ester Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
This invention relates to one imbed baseboard sealing structure, which comprises the following parts: one supportive board with at least one gradient open; one semiconductor to contain gradient open with several electrode pads; one bioelectricity layer formed on the semiconductor chip and support board filled into the gap between semiconductor chip and load board; one circuit layer formed on dielectric layer connected to semiconductor chip pad through conductor structure.
Description
Technical field
The invention relates to a kind of encapsulating structure of chip buried base plate, particularly about a kind of encapsulating structure that is integrated with semiconductor chip.
Background technology
Evolution along with semiconductor packaging, semiconductor device (Semiconductor device) has been developed different encapsulation kenels, it mainly is a first device semiconductor chip on a base plate for packaging (package substrate) or lead frame, again semiconductor chip is electrically connected on this base plate for packaging or the lead frame, then encapsulates with colloid.Spherical grid array type (Ball grid array wherein, BGA) be a kind of advanced person's semiconductor packaging, it adopts a base plate for packaging to settle semiconductor chip, and utilize automatic contraposition (Self-alignment) technology to plant and put the tin ball (Solder ball) that a plurality of one-tenth grid arrays are arranged at this base plate for packaging back side, make on the semiconductor chip carrier of same units area and can hold more I/O link (I/O connection), the semiconductor chip needs that meet Highgrade integration (Integration) weld and are electrically connected to external device (ED) by these tin balls with whole encapsulation unit.
The conventional semiconductor package structure is that semiconductor chip is sticked on substrate top surface, carry out routing and engage (wire bonding) or chip bonding (Flip chip) encapsulation, planting the tin ball at the back side of substrate again electrically connects, so, though can realize the purpose of multiway number, but when high frequency more uses or during high speed operation, because of the lead access path long, its electrical characteristic usefulness not only can't be promoted, and can limit to some extent, in addition, because of conventional package needs repeatedly connecting interface, relatively increase manufacturing cost.
In view of this, in order to promote electrical quality effectively and to meet the application of next-generation, industry is studied employing one after another with in the chip buried loading plate, does this direct electric connection, shorten electrical conducting path, and reduce the loss of signal, distorted signals and be lifted at the ability of high speed operation.
As shown in Figure 1, it is the semiconductor package part that the 6th, 709, No. 898 patent cases of the U.S. propose.As shown in the figure, this semiconductor package part comprises a heating panel 102, and this heating panel 102 has at least one recess 104; Semiconductor chip 114, the non-action face of this semiconductor chip 114 connect by a heat conduction sticky material 118 and put in this recess 104; One circuit layer reinforced structure 122 is to be formed on this heating panel 102 and this semiconductor chip 114 by increasing a layer technology.Wherein, the recess 104 of this heating panel 102 extends to this heating panel 102 inner certain perforate degree of depth from the upper surface of this heating panel 102, semiconductor chip 114 is adhered to the base plane of recess 104 with heat conduction sticky material 118, again on this chip 114 and heating panel 102 with existing hot pressing processing procedure, dielectric material is flowed in the recess 104, be filled between chip 114 and the heating panel 102.
When dielectric material flows into recess 104, because of the size restrictions of recess 104 and the surface tension of dielectric material itself, make the space that dielectric material can't complete filling recess 104, cause space or bubble to produce easily, make follow-up in carrying out the thermal cycle processing procedure of semiconductor package part, gas in this space or the bubble is met thermal expansion, makes chip impaired even push the chip explosion in the packaging part; In addition since dielectric material can't complete filling in this recess 104, cause this dielectric materials layer surface smoothness poor, can't be applied on the high-order integrated circuit (IC) products.
Moreover, though can directly on chip, extend circuit in this semiconductor package part, shorten electrical conducting path, be lifted at the ability of high speed operation, but multi-functional in the face of electronic product now, the semiconductor chip of imbedding in this semiconductor package part is the element of single form mostly, does not form multi-functional module architectures as yet, is not inconsistent electronic product development trend now.
Summary of the invention
For overcoming the disappearance of above-mentioned prior art, main purpose of the present invention is to provide a kind of encapsulating structure of chip buried base plate, and semiconductor chip is positioned in the chip bearing member effectively.
Another object of the present invention is to provide a kind of encapsulating structure of chip buried base plate, can integrate a plurality of semiconductor chips, promote the electrical functionality of electronic installation.
A further object of the present invention is to provide a kind of encapsulating structure of chip buried base plate, can keep planarization and the consistency of semiconductor element in the loading plate opening, and then promotes the manufacturing capacity of follow-up fine rule road processing procedure.
Another purpose of the present invention is to provide a kind of encapsulating structure of chip buried base plate, and the processing procedure of integrating semiconductor chip and substrate for client provides bigger demand elasticity, is simplified semiconductor industry fabrication steps, cost and interface problem.
For reaching above-mentioned and other purpose, the encapsulating structure of a kind of chip buried base plate of the present invention comprises: a loading plate, and this loading plate has at least one stepped opening; The semiconductor chip is accommodated in this stepped opening, and has a plurality of electronic padses on this semiconductor chip; One dielectric layer is formed on this semiconductor chip and the loading plate, and is filled in the gap between this semiconductor chip and loading plate; And a line layer, be formed on this dielectric layer, and this line layer can be by being formed on the electronic pads that conductive structure in the dielectric layer is electrically connected to this semiconductor chip.
This loading plate can be an overall structure in the present invention, and offers the different opening of size in this loading plate in regular turn, forms stepped opening, and this loading plate with stepped opening also has a plurality of opening sizes that vary in size in addition.
The invention still further relates to a kind of encapsulating structure of chip buried base plate, the encapsulating structure of this chip buried base plate comprises: a loading plate, be by first bearing bed, second bearing bed and the 3rd bearing bed are formed, this second bearing bed is to connect to put on this first bearing bed, and this second bearing bed has at least one perforate that runs through, the 3rd bearing bed has at least one perforate that runs through again, this perforate is corresponding to the second bearing bed tapping, and its bore size is the size greater than the second bearing bed perforate, in this loading plate, form the stepped opening that opening from bottom to top amplifies gradually, expose outside the face of putting that connects of first bearing bed, and the face of putting that connects that appears this second bearing bed part surface; A plurality of semiconductor chips be accommodated in the face of putting that connects of first, second bearing bed in the stepped opening of this loading plate, and these semiconductor chips have a plurality of electronic padses; One dielectric layer is formed on these semiconductor chips and the loading plate, and is filled in the gap between these semiconductor chips and loading plate; And a line layer, be formed on this dielectric layer, and this line layer can be electrically connected to the electronic pads of these semiconductor chips by being formed at conductive structure in the dielectric layer.
Therefore, the encapsulating structure of chip buried base plate of the present invention utilizes this loading plate to have stepped opening, and this stepped opening is the shape that adopts opening from bottom to top to amplify gradually, make dielectric layer material be filled to easily in the gap of this semiconductor chip and loading plate opening, this semiconductor chip can be fixed in this loading plate effectively, and keep the loading plate dielectric layer profile pattern and the consistency of taking in semiconductor chip, and then promote the follow-up reliability that on dielectric layer, forms the circuit processing procedure.
The present invention also goes out the encapsulating structure of another chip buried base plate, it takes in a chip portfolio that comprises a plurality of semiconductor chips in the stepped opening of this loading plate, and these semiconductor chips are that next-door neighbour's the ladder of putting in this stepped opening that connects connects on the face of putting, for follow-up when on this semiconductor chip and loading plate, covering dielectric layer and forming line layer, simultaneously can these semiconductor chips be electrically connected by this line layer, can make these electrical connection paths that are accommodated between the semiconductor chip of loading plate opening shorten, thereby promote the transmission quality of these chip chamber electrical signals, reduce the received signal distortion, reach the purpose of signal high-speed transfer, formation is integrated with the modular construction of a plurality of chips, meets the multi-functional demand of electronic product now.
In addition, but since the bearing part manufacturing and the encapsulation process of encapsulating structure integrating semiconductor element of the present invention big demand elasticity of client can be provided and simplify semiconductor industry processing procedure and interface coordination problem.
Description of drawings
Fig. 1 is the encapsulating structure of existing integrating semiconductor chip;
Fig. 2 A and Fig. 2 B are the generalized sections of the encapsulating structure embodiment 1 of chip buried base plate of the present invention; And
Fig. 3 A and Fig. 3 B are the generalized sections of the encapsulating structure embodiment 2 of chip buried base plate of the present invention.
Embodiment
Embodiment 1
It shown in Fig. 2 A the generalized section of the encapsulating structure embodiment 1 of chip buried base plate of the present invention.As shown in the figure, this encapsulating structure comprises a loading plate 20, and this loading plate 20 has at least one stepped opening 20a, can take at least one semiconductor element; At least one semiconductor chip 21 is accommodated among the stepped opening 20a of this loading plate 20; One dielectric layer 22 is formed on this semiconductor chip 21 and the loading plate 20, and the material of this dielectric layer 22 is filled in the gap of this semiconductor chip 21 and loading plate opening 20a, and this semiconductor chip 21 is fixed in this loading plate 20.Wherein, also can be formed with a line layer 23 on this dielectric layer 22, and this line layer 23 can be electrically conducted this semiconductor chip 21.
This loading plate 20 is made up of a plurality of bearing bed storehouses in the present invention, and is positioned at the above bearing bed of the bottom and has at least one and run through perforate, and this runs through perforate and successively increases progressively expansion from lower to upper.Below promptly explain with three-decker.This loading plate 20 comprises first bearing bed 200, second bearing bed 202 and the 3rd bearing bed 204.This second bearing bed 202 is to connect to put on this first bearing bed 200, and this second bearing bed has and at least onely run through its surperficial perforate 202a, and makes this first bearing bed 200 close the side of this perforate 202a.The 3rd bearing bed 204 has at least one its surperficial perforate 204a that runs through, this perforate 204a position is corresponding to the second bearing bed perforate 202a place, and the size of this perforate 204a is the size greater than perforate 202a, forms the stepped opening 20a that opening from bottom to top amplifies gradually in this loading plate 20.This first, second and third bearing bed can be insulating barrier, metal level, ceramic layer or the inner combination in any that has formed the substrate of line layer.What this must declare be, the number of plies of this loading plate 20 can decide that (for example this loading plate can be four layers according to actual needs, five layers even more multi-layered loading plate), be simple declaration this law effect of the present invention and advantage, be that example is illustrated only now, but be not in order to restriction the present invention with 3 layers of loading plate.
In addition, this loading plate 20 also can be integrated structure, and this is the stepped opening 20a that amplifies gradually of opening size from bottom to top, can make by the corresponding in regular turn opening that forms different size in loading plate 20.
This semiconductor chip 21 has an active surface 21a and the non-active surface 21b relative with this active surface.This semiconductor chip 21 is to connect with its non-active surface 21b to put on this first bearing bed 200, and is accommodated among this stepped opening 20a, and the active surface 21a of this semiconductor chip 21 has a plurality of electronic padses 210.This semiconductor chip 21 can be active or passive chip, for example is selected from electric capacity chip, memory chip, ASIC (Application Specific Integrated Circuit) chip or cpu chip etc.
This dielectric layer 22 can for example be that epoxy resin (Epoxy resin), polyimides (Polyimide), cyanate ester (Cyanate ester), glass fibre (Glass fiber), Bismaleimide Triazine (BT, Bismaleimide triazine) or materials such as blending epoxy and glass fibre constitute.
This line layer 23 is to be formed on this dielectric layer 22, and can be electrically conducted the electronic pads 210 of this semiconductor chip 21 by the conductive structure 222 (for example conductive blind hole or projection) that is formed in this dielectric layer 22.The generation type of this line layer 23 is the existing process technique of industry, so no longer give unnecessary details for literary composition at this.
Compared with prior art, the encapsulating structure of chip buried base plate of the present invention mainly is that semiconductor chip 21 is placed among the stepped opening 20a of loading plate 20, and by the form of amplifying gradually of this stepped opening 20a, the material of dielectric layer fully is filled in the gap between this semiconductor chip 21 and this loading plate 20 opening 20a, this semiconductor chip 21 is fixed in this loading plate 20 effectively, thereby makes this semiconductor die package reach good quality and reliability.
Follow-up in encapsulating structure of the present invention, also can increase floor processing procedure at this dielectric layer 22 and line layer 23 enterprising line roads according to actual needs, connect with the circuit that constitutes required electrical design.It shown in Fig. 2 B the generalized section that increases floor encapsulating structure that processing procedure forms on the dielectric layer 22 shown in Fig. 2 A and line layer 23 enterprising line roads.Structure shown in its structure and Fig. 2 A is roughly the same, just also is formed with a circuit layer reinforced structure 24 on this dielectric layer 22 and line layer 23.
Consult Fig. 2 B, this circuit layer reinforced structure 24 includes insulating barrier 240, be stacked in the patterned line layer 242 on this insulating barrier 240 and pass the conductive blind hole 242a that this insulating barrier 240 electrically connects this line layer 242, and these a plurality of conductive blind hole 242a can be electrically connected to this line layer 23.On the line layer of the outer surface of this circuit layer reinforced structure 24, then be formed with a plurality of electric connection pads 244, and on this outermost layer circuit layer, be to be coated with a welding resisting layer 25, this welding resisting layer 25 has a plurality of openings, expose outside this electric connection pad 244, plant and be equipped with a plurality of conducting elements 260, for example tin ball (Solder ball), conductive pole or welding column, this semiconductor chip 21 that is accommodated in this loading plate 20 can be electrically conducted external electronic by electronic pads 210, line layer 23, this circuit layer reinforced structure 24 and this conducting element.
Embodiment 2
Fig. 3 A is the generalized section of the encapsulating structure embodiment 2 of chip buried base plate of the present invention, and it and embodiment 1 are roughly the same, and its main difference is to be equipped with chipset in the stepped opening of loading plate.As shown in the figure, this encapsulating structure comprises a loading plate 30, has at least one stepped opening 30a; Chip portfolio with semiconductor chip 31a, 31b, 31c is accommodated among this stepped opening 30a, and has a plurality of electronic pads 310a, 310b, 310c on these semiconductor chips 31a, 31b, 31c; One dielectric layer 32 is formed on this semiconductor chip 31a, 31b, 31c and the loading plate 30, and the material of this dielectric layer 32 is fully to be filled in this loading plate 30 opening 30a and the chip gap, and these semiconductor chips are fixed in this loading plate 30.Wherein, also can be formed with a line layer 33 on this dielectric layer 32, and this line layer 33 is electrically conducted these semiconductor chips 31a, 31b, 31c.
This loading plate 30 is made up of a plurality of bearing bed storehouses, and is positioned at each above bearing bed of the bottom and all has at least one perforate that runs through, and this runs through perforate and successively increases progressively expansion from lower to upper.Below promptly explain with three layers structure.This loading plate 30 comprises first bearing bed 300, second bearing bed 302 and the 3rd bearing bed 304.This second bearing bed 302 connects and places on this first bearing bed 300, and this second bearing bed 302 has at least one its surperficial perforate 302a that runs through, a side that makes this first bearing bed 300 seal this perforate 302a.The 3rd bearing bed 304 has at least one its surperficial perforate 304a that runs through, this perforate 304a is corresponding to this perforate 302a place, and the size of this perforate 304a is the size greater than this perforate 302a, in this loading plate 30, form the stepped opening 30a that opening from bottom to top amplifies gradually, and this stepped opening 30a has one to expose outside first bearing bed 300 and meet the perforate 302a that puts face 300b, and appears the formed perforate 304a that puts face 302b that connects of these second bearing bed, 302 part surfaces.This first, second and third bearing bed 300,302,304 can be insulating barrier, metal level, ceramic layer or the inner combination in any that has formed the substrate of line layer.What this must declare be, the number of plies of this loading plate 30 can be decided (for example this loading plate can be four, five layers even more multi-layered loading plate) according to actual needs, be simple declaration effect of the present invention and advantage, only the loading plate with three-decker is that example is illustrated, but is not in order to restriction the present invention.
This semiconductor chip 31a, 31b, 31c are that connecing of next-door neighbour places connecing of first bearing bed 300 to put connecing of the face 300b and second bearing bed 302 to put on the face 302b, and are accommodated in this stepped opening 30a.Wherein, these semiconductor chips 31a, 31b, 31c can be active or passive chip, capacitive silicon chip for example, memory chip, the combination in any of the semiconductor chip of types such as ASIC (Application Specific IntegratedCircuit) chip or cpu chip.
This dielectric layer 32 can be for example being that epoxy resin (Epoxy resin), polyimides (Polyimide), cyanate ester (Cyanate ester), glass fibre (Glass fiber), Bismaleimide Triazine (BT, Bismaleimide triazine) or materials such as blending epoxy and glass fibre constitute.
This line layer 33 is to be electrically conducted electronic pads 310a, 310b, 310c on these semiconductor chips 31a, 31b, the 31c by a plurality of conductive structures 322 (for example conductive blind hole or projection) that are formed in this dielectric layer 32.Line layer 33 can be simultaneously in order to provide directly being electrically conducted between these semiconductor chips 31a, 31b, 31c, shorten the electrical connection path between these semiconductor chips, guarantee the transmission quality of these chip chamber electrical signals, reduce the received signal distortion, reach the purpose that signal high-speed transfer and electrical functionality are integrated.
In the encapsulating structure of chip buried base plate of the present invention, also can on this dielectric layer 32 and line layer 33, carry out the build-up circuit processing procedure according to actual needs, the circuit that constitutes required electrical design connects.It shown in Fig. 3 B the generalized section that increases the formed encapsulating structure of floor processing procedure on the dielectric layer 32 shown in Fig. 3 A and line layer 33 enterprising line roads, structure shown in its structure and Fig. 3 A is roughly the same, just also is formed with circuit layer reinforced structure 34 on this dielectric layer 32 and line layer 33.
See also Fig. 3 B, this circuit layer reinforced structure 34 is to comprise insulating barrier 340, be stacked in the line layer 342 on this insulating barrier 340 and pass the conductive blind hole 342a that this insulating barrier 340 is electrically connected to this line layer 33, and these a plurality of conductive blind hole 342a can be electrically connected to line layer 33.On the line layer of the outer surface of this circuit layer reinforced structure 34, then be formed with a plurality of electric connection pads 344, and be to be coated with a welding resisting layer 35 on this outer-layer circuit layer, this welding resisting layer 35 is to have a plurality of openings, expose outside this layer electric connection pad 344, provide to plant and be equipped with a plurality of conducting elements 360, tin ball (Solder ball) for example, conductive pole or welding column, for this semiconductor chip 31a that is accommodated in this loading plate 30,31b, 31c can pass through electronic pads 310a, 310b, 310c, line layer 33, circuit layer reinforced structure 34 and conducting element are electrically conducted external electronic.
Therefore, the encapsulating structure of chip buried base plate of the present invention mainly is the stepped opening that semiconductor chip (or chip portfolio) at least is accommodated in loading plate, and the form that can amplify gradually by this stepped opening, make the material of dielectric layer fully be filled in the opening of this loading plate, with this semiconductor chip (or chip portfolio) is fixed in this opening, simultaneously can keep the planarization and the consistency on the loading plate dielectric layer surface of taking in semiconductor chip, and then promote the follow-up reliability that on dielectric layer, forms the circuit processing procedure.In addition, it is inequality (or identical to take in a plurality of functions in the present invention in the stepped opening of this loading plate, also or part identical) semiconductor chip, and these semiconductor chips are that connecing of next-door neighbour put on the ladder in this stepped opening, for follow-up on this semiconductor chip and loading plate pressing dielectric layer and when forming line layer, simultaneously can these semiconductor chips be electrically connected by this line layer, can make these electrical connection paths that are accommodated between semiconductor chip in the loading plate opening shorten, thereby can promote the transmission quality of these chip chamber electrical signals, reduce the distortion of received signal, can reach the purpose of signal high-speed transfer, form simultaneously and be integrated with the multi-chip module structure, meet the multi-functional needs of electronic product now.
Moreover, on the dielectric layer and line layer of the encapsulating structure of chip buried base plate of the present invention, also can carry out circuit and increase a layer processing procedure, be embedded with the multilayer wiring structure that forms high density and fine rule road on the loading plate of semiconductor chip at this, simultaneously can plant a plurality of conducting elements at the line construction outer surface, can directly be electrically connected to external device (ED) for the semiconductor chip that is embedded in the loading plate, therefore, but the present invention is the manufacturing and the encapsulation process of the bearing part of integrating semiconductor chip also, the big demand elasticity of client is provided and simplifies semiconductor industry processing procedure and interface coordination problem.
Claims (12)
1. the encapsulating structure of a chip buried base plate is characterized in that, the encapsulating structure of this chip buried base plate comprises:
One loading plate, and this loading plate has at least one stepped opening;
The semiconductor chip is accommodated in this stepped opening, and has a plurality of electronic padses on this semiconductor chip;
One dielectric layer is formed on this semiconductor chip and the loading plate, and is filled in the gap between this semiconductor chip and loading plate; And
One line layer is formed on this dielectric layer, and this line layer can be by being formed on the electronic pads that conductive structure in the dielectric layer is electrically connected to this semiconductor chip.
2. the encapsulating structure of chip buried base plate as claimed in claim 1, it is characterized in that, the encapsulating structure of this chip buried base plate also comprises at least one circuit layer reinforced structure that is formed on this dielectric layer and the line layer, and this circuit layer reinforced structure is to be electrically conducted this line layer.
3. the encapsulating structure of chip buried base plate as claimed in claim 2 is characterized in that, this circuit layer reinforced structure outer surface is to have planted a plurality of conducting elements, can be electrically connected to external electronic for this semiconductor chip.
4. the encapsulating structure of chip buried base plate as claimed in claim 1, it is characterized in that, this loading plate comprises first bearing bed, second bearing bed and the 3rd bearing bed, and this second bearing bed is to connect to place on this first bearing bed, this second bearing bed has at least one perforate that runs through, make this first bearing bed close a side of this perforate, the 3rd bearing bed is to have at least one perforate that runs through, this perforate is corresponding to the second bearing bed position of opening, and its bore size is the bore size greater than second bearing bed, forms this stepped opening that opening from bottom to top amplifies gradually in this loading plate.
5. the encapsulating structure of chip buried base plate as claimed in claim 1, it is characterized in that, this loading plate is holistic structure, by the corresponding in regular turn opening that forms different size in this loading plate, forms this from bottom to top stepped opening of amplifying gradually of opening size.
6. the encapsulating structure of chip buried base plate as claimed in claim 4 is characterized in that, this semiconductor chip is to connect to put at this first bearing bed and be accommodated in this stepped opening.
7. the encapsulating structure of chip buried base plate as claimed in claim 4 is characterized in that, in this first, second and third bearing bed one can be in insulating barrier, metal level, ceramic layer and the inner substrate that has formed line layer.
8. the encapsulating structure of chip buried base plate as claimed in claim 1 is characterized in that, this semiconductor chip is active or passive chip.
9. the encapsulating structure of a chip buried base plate is characterized in that, the encapsulating structure of this chip buried base plate comprises:
One loading plate, form by first bearing bed, second bearing bed and the 3rd bearing bed, this second bearing bed is to connect to put on this first bearing bed, and this second bearing bed has at least one perforate that runs through, the 3rd bearing bed has at least one perforate that runs through again, this perforate is corresponding to the second bearing bed tapping, and its bore size is the size greater than the second bearing bed perforate, in this loading plate, form the stepped opening that opening from bottom to top amplifies gradually, expose outside the face of putting that connects of first bearing bed, and the face of putting that connects that appears this second bearing bed part surface;
A plurality of semiconductor chips be accommodated in the face of putting that connects of first, second bearing bed in the stepped opening of this loading plate, and these semiconductor chips have a plurality of electronic padses;
One dielectric layer is formed on these semiconductor chips and the loading plate, and is filled in the gap between these semiconductor chips and loading plate; And
One line layer is formed on this dielectric layer, and this line layer can be electrically connected to the electronic pads of these semiconductor chips by being formed at conductive structure in the dielectric layer.
10. the encapsulating structure of chip buried base plate as claimed in claim 9, it is characterized in that, the encapsulating structure of this chip buried base plate also comprises at least one circuit layer reinforced structure that is formed on this dielectric layer and the line layer, and this circuit layer reinforced structure is to be electrically conducted this line layer.
11. the encapsulating structure of chip buried base plate as claimed in claim 10 is characterized in that, this circuit layer reinforced structure outer surface has also planted a plurality of conducting elements, is electrically connected to external device (ED) for these semiconductor chips.
12. the encapsulating structure of chip buried base plate as claimed in claim 9 is characterized in that, these semiconductor chips are to be chosen as initiatively and passive chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101234002A CN100424863C (en) | 2005-11-25 | 2005-11-25 | Chip buried base plate encapsulation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101234002A CN100424863C (en) | 2005-11-25 | 2005-11-25 | Chip buried base plate encapsulation structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1971895A true CN1971895A (en) | 2007-05-30 |
| CN100424863C CN100424863C (en) | 2008-10-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101234002A Expired - Fee Related CN100424863C (en) | 2005-11-25 | 2005-11-25 | Chip buried base plate encapsulation structure |
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| Country | Link |
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| CN (1) | CN100424863C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101950739B (en) * | 2009-06-05 | 2012-02-01 | 深圳华映显示科技有限公司 | circuit substrate |
| US8258623B2 (en) | 2009-05-12 | 2012-09-04 | Chunghwa Picture Tubes, Ltd. | Circuit layout of circuit substrate, light source module and circuit substrate |
| CN103945646A (en) * | 2013-01-21 | 2014-07-23 | 联想(北京)有限公司 | Circuit board |
| CN111816569A (en) * | 2020-07-28 | 2020-10-23 | 珠海越亚半导体股份有限公司 | Packaging frame, manufacturing method thereof and substrate |
| CN113643986A (en) * | 2021-08-10 | 2021-11-12 | 中国科学院微电子研究所 | Manufacturing method of structure for improving interconnection precision between embedded silicon bridge and chip |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3471111B2 (en) * | 1995-03-20 | 2003-11-25 | 三菱電機株式会社 | Semiconductor device |
| JP3744649B2 (en) * | 1997-05-26 | 2006-02-15 | ソニー株式会社 | Semiconductor package and manufacturing method thereof |
| US6838758B1 (en) * | 2000-05-10 | 2005-01-04 | Advanced Micro Devices, Inc. | Package and method for making an underfilled integrated circuit |
| US6709898B1 (en) * | 2000-10-04 | 2004-03-23 | Intel Corporation | Die-in-heat spreader microelectronic package |
| JP2003068901A (en) * | 2001-08-30 | 2003-03-07 | Murata Mfg Co Ltd | Electronic component |
| JP2004214258A (en) * | 2002-12-27 | 2004-07-29 | Renesas Technology Corp | Semiconductor module |
| TWI237885B (en) * | 2004-10-22 | 2005-08-11 | Phoenix Prec Technology Corp | Semiconductor device having carrier embedded with chip and method for fabricating the same |
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2005
- 2005-11-25 CN CNB2005101234002A patent/CN100424863C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8258623B2 (en) | 2009-05-12 | 2012-09-04 | Chunghwa Picture Tubes, Ltd. | Circuit layout of circuit substrate, light source module and circuit substrate |
| CN101950739B (en) * | 2009-06-05 | 2012-02-01 | 深圳华映显示科技有限公司 | circuit substrate |
| CN103945646A (en) * | 2013-01-21 | 2014-07-23 | 联想(北京)有限公司 | Circuit board |
| CN111816569A (en) * | 2020-07-28 | 2020-10-23 | 珠海越亚半导体股份有限公司 | Packaging frame, manufacturing method thereof and substrate |
| CN111816569B (en) * | 2020-07-28 | 2022-04-08 | 珠海越亚半导体股份有限公司 | Packaging frame, manufacturing method thereof and substrate |
| CN113643986A (en) * | 2021-08-10 | 2021-11-12 | 中国科学院微电子研究所 | Manufacturing method of structure for improving interconnection precision between embedded silicon bridge and chip |
| CN113643986B (en) * | 2021-08-10 | 2024-04-09 | 中国科学院微电子研究所 | Manufacturing method of structure for improving interconnection precision between embedded silicon bridge and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100424863C (en) | 2008-10-08 |
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