CN1967723A - Self-testing IC based on 3D memorizer - Google Patents

Abstract

The invention provides the self-test integrated circuit based on 3D-M. Three-Dimension Memory (3D-M) stacks above the integrated circuits under testing (CUT), and stores the testing data or seed data of CUT. After integrated with 3D-M, CUT can achieve self-testing. Meanwhile, since there is great bandwidth between 3D-M and CUT, the self-testing can support the same speed tests.

Description

Carry out the integrated circuit of self-test based on three-dimensional storage

The present invention is that application number is 02131089.0, the applying date is on September 30th, 2002, denomination of invention is divided an application for the application for a patent for invention of " three-D integrated memory ".

Technical field

The present invention relates to integrated circuit fields, or rather, relate to three-dimensional storage.

Background technology

Three dimensional integrated circuits (abbreviating 3D-IC as) is stacked in one or more three dimensional integrated circuits layers (abbreviating the 3D-IC layer as) on the substrate on the direction perpendicular to substrate mutually.The 3D-IC layer is made of on-monocrystalline (being polycrystalline or amorphous) semiconductor material, and it can have functions such as logic, storage, simulation.For the 3D-IC layer with logic and analog functuion, they are responsive to defective.Because the defect concentration of non-single crystalline semiconductor material is bigger, so the yield rate of this class 3D-IC is not high.Simultaneously, logic and analog functuion power consumption are higher, and they three-dimensional integrated faces bigger heat dissipation problem.By contrast, because general memory has the ability of repair-deficiency, it is more insensitive to defective; And it is low in energy consumption, does not have heat dissipation problem.So storer is suitable for three-dimensional integrated.

Three-dimensional storage (3-dimensional memory abbreviates 3D-M as) is stacked in one or more accumulation layers on the substrate circuitry on the direction perpendicular to substrate mutually.Shown in Figure 1A, 3D-M contains at least one and is stacked and placed on three-dimensional accumulation layer 100 on the Semiconductor substrate 0s, and many address selection lines (comprising word line 20a and bit line 30a) and a plurality of 3D-M (1aa of unit are arranged on each three-dimensional accumulation layer (as 100) ...).A plurality of transistors are arranged on the substrate 0s.Contact channels mouth (20av, 30av ...) be address selection line (20a, 30a ...) and substrate circuitry electrical connection is provided.3D-M can be divided into three-dimensional random access memory (3D-RAM) and 3 D ROM (3D-ROM).The circuit of 3D-RAM unit and conventional RAM unit are similar, and just it generally constitutes (Figure 1B) by thin film transistor (TFT) 1t.3D-ROM can be masking film program (3D-MPROM) or electricity programming (3D-EPROM comprises one-time programming or repeatedly programming, as 3D-flash, 3D-MRAM, 3D-FRAM, 3D-OUM etc.).The visible United States Patent (USP) 5,835,396 of its basic structure and other open file etc.It can use as the active component of thin film transistor (TFT) (TFT) 1t (Fig. 1 CA, Fig. 1 CB) and/or as the passive element (Fig. 1 DA-Fig. 1 E) of diode 1d.For the 3D-ROM unit that uses TFT, they can contain suspension grid 30fg (Fig. 1 CA) or have vertical-channel 25c (Fig. 1 CB).For the 3D-MPROM unit that uses diode, it contains the 3D-ROM film 22 (comprising accurate conductive membrane) with nonlinear resistance property, and come presentation logic " 1 " (Fig. 1 DA) with information opening 24 (being access opening) exist (or not existing of medium 26 is set), not the existing of information opening 24 existence of medium 26 (or be provided with) come presentation logic " 0 " (Fig. 1 DB).Here, medium 26 is set is meant medium between address selection line 20a, 30a, whether it exists the value of setting that determines this 3D-ROM unit.3D-EPROM for using diode can come presentation logic information (Fig. 1 E) by the integrality of anti-fuse 22af.

3D-M has advantages such as low cost, high density.But because it is generally based on non-single crystal semiconductor, the performance of 3D-M unit still be difficult to routine, the semi-conductive storage element of based single crystal compares.The 3D-M that separates (standalone) waits at aspects such as read or write speed, yield rate, programmability to improve.But this need make full use of the good integration of 3D-M.Integrated by three-dimensional, 3D-M can be integrated on the chip with the readable writable memory and/or the data processor of routine, thereby realizes three-D integrated memory (3DiM).The overall performance of 3DiM (as speed, yield rate, programmability and safety of data) is good far beyond the 3D-M that separates (standalone).But the present invention proposes the method for multiple raising 3D-M integration.Another important applied field of 3DiM is an integrated circuit testing: the 3D-M that is loaded with test data can integrate with tested circuit, thereby realizes its on-the-spot self-test and speed test together.

Summary of the invention

Fundamental purpose of the present invention provides an integrated circuit with self-testing capability.

Another object of the present invention provides an integrated circuit that has with fast power of test.

According to these and other purpose, the invention provides a kind of integrated circuit that carries out self-test based on three-dimensional storage (3D-M).

Compare with conventional memory, three-dimensional storage (3D-M) but sharpest edges are its integrations.Because 3D-M unit does not account for Substrate Area, therefore can utilize the semiconductor area on the substrate to form comparatively complicated substrate integrated circuit.The substrate integrated circuit can comprise conventional storer, data processor, mimic channel etc.The 3D-M System on Chip/SoC (3D-MSoC) that the integrated back of 3D-M and these substrate integrated circuit forms is called as three-D integrated memory (3-dimensional integrated memory abbreviates 3DiM as).3DiM can further improve speed, yield rate, programmability and the data security etc. of 3D-M.

In 3DiM, the substrate integrated circuit integrated with 3D-M can comprise embedded readable writable memory (embeddedRWM abbreviates eRWM as) and embedded data processor (embedded processor abbreviates eP as).3D-M and eRWM are each has something to recommend him: but 3D-M at integration and capacity/have superiority in price, eRWM is having superiority aspect speed and the writability.The integrated advantage that can bring into play separately between them is to reach the purpose of optimization system performance.Simultaneously,, then can in the 3DiM chip, handle the contained data of 3D-M as 3D-M and eP are integrated, thus the data security of raising 3D-M.

A typical eRWM is embedded RAM (embedded RAM abbreviates eRAM as).The time of visiting first of eRAM is very short, and it can be used as the data buffer (cache) of 3D-M, promptly deposits a backup of 3D-M data.EP arrives first among the eRAM and seeks when read data.As can not find, then in 3D-M, seek again.Can solve eP and the different problem of 3D-M data supply and demand speed like this.Another typical eRWM is Embedded ROM (embedded ROM abbreviates eROM as).EROM generally is nonvolatile memory (NVM), and its good performance able to programme remedies the limited programmability of 3D-M.EROM is the ideal carrier (referring to PCT application " three-dimensional storage " etc. in first to file) of storage 3D-M error correction data and upgrading sign indicating number.

3D-M and eP, eRWM are integrated, can realize single core computer (computer-on-a-chip abbreviates ConC as).ConC can finish the multiple function of computer nowadays.A typical C onC is single core player (player-on-a-chip abbreviates PonC as).PonC can be used for storage and broadcast data (as audio-video works, e-book, map etc.), and for they provide good copyright protection.For the technology of utilizing CD, conventional ROM to come data on file, the output signal that the bootlegger can be by monitoring data storage carrier or design (reverseengineering) to data storage carrier is counter and obtain source book.In PonC, 3D-M and data player (preferably containing D/A converter in a slice) are integrated in the chip, and its output signal is simulating signal and/or decoded signal.In use, source book can not output to outside the PonC in any form, and it duplicates with being difficult to be digitized, so PonC provides extremely strong copyright protection.

For using masked edit program 3D-M to store the 3DiM of data, the data of information opening representative are preferably enciphered data among the 3D-M.And, preferably contain decryption engine in a slice in the 3DiM, it is decrypted the 3D-M data, and the data after the deciphering are directly delivered to other functional block in the sheet.Like this, be difficult to obtain the contained data of 3D-M (comprising data and code) by peeling off anti-design meanses such as (de-layering).

But the present invention further improves the integration of 3D-M from the angle of memory construction.At first, preferably use storage element with simple structure, as three-dimensional read-only storage element (3D-ROM) based on diode, three dimensional mask program storage unit (3D-MPROM) etc. especially; Secondly, used higher temperature as the technological process of 3D-M, then the interconnection line system of substrate circuitry preferably is made of refractoriness conductor stable under this temperature (as the refractoriness metal) and heat stable dielectric (as monox, silicon nitride); Once more, preferably contain a plurality of address selection lines space in the 3D-M array, they make embedded lead-in wire can pass this 3D-M layer, thereby provide extraneous interface for the substrate integrated circuit; In addition, for high speed substrate integrated circuit, a screen layer is preferably being arranged between small part 3D-M layer and the substrate circuitry.

Another important applied field of 3DiM is an integrated circuit testing.Existing measuring technology is difficult to high speed integrated circuit is realized with speed test (at-speed test), and it costs an arm and a leg, and do not support the on-the-spot self-test and the diagnosis of integrated circuit.Along with 3D-M, the especially appearance of 3D-ROM, these problems can be resolved.3D-M can be integrated on the chip with tested circuit (CUT) as the carrier of test data.Be carried to tested circuit in when test with input test vector is from 3D-M under, then with its output and expected test vector ratio, to determine the performance of tested circuit.This self-test of carrying out based on three-dimensional storage (3DMST) has plurality of advantages: the first, and 3D-M and CUT integrate, and have very big bandwidth between them, can carry out with the speed test high speed integrated circuit at an easy rate; The second, the 3D-M cost is lower, and the fringe cost that embedding 3D-M causes in CUT is very low; The 3rd, use the chip of 3DMST can carry out on-the-spot self-test and diagnosis, and then improve the reliability of system; The 4th, 3D-M is very little to the layout design influence of CUT; The 5th, the 3D-M memory space is very big, and the test vector of its storage can provide higher test coverage to CUT.

Test vector is downloaded to tested circuit from three-dimensional storage can adopt serial to download or parallel download dual mode.In the serial downloading process, test vector is shifted in the shift-in test chain of flip-flops one by one.In parallel downloading process, test vector is inputed in the test trigger by parallel.The 3DMST integrated circuit is also supported parallel self-test, mixed signal circuit test, the system self-testing of printed circuit board, the functions such as compression and decompression of test data.The 3DMST test can also be used in the mixed type test, and promptly it can combine with other means of testing (as BIST test and extraneous sweep test), to optimize testing cost and testing reliability.

In the 3DMST test process, do not conform to the expected test vector as the output test vector, two kinds of possibilities are arranged: a kind of may be tested circuit defectiveness; Another kind may be the 3D-M defectiveness.Second kind of possible situation can cause the yield rate unnecessary loss.For fear of this situation, can use " reliable 3DMST test " or tested circuit is carried out the secondary examination." reliable 3DMST test " guarantees that the 3D-M data are errorless.It is after finishing the 3DMST test that secondary is screened, and unsanctioned chip is carried out once extraneous sweep test again.Still can not pass through this sweep test as this chip, it just is considered to waste product.The dual test that is otherwise known as of this test pattern.The time of extraneous sweep test when shortening dual test, when 3DMST tests, problem test vector (promptly exporting the test vector that test vector and expected test vector do not conform to) can be noted, when carrying out extraneous sweep test, can only carry out the test of problem test vector like this to chip.

But because its outstanding manufacturability and integration, masked edit program 3D-M (3D-MPROM) is considered to a kind of up-and-coming 3D-M.The invention provides multiple autoregistration 3D-MPROM.In the technological process of autoregistration 3D-MPROM, its 3D-ROM film and word line and the equal autoregistration of bit line promptly do not need an independent processing step to come the 3D-ROM film is carried out the figure conversion.These 3D-ROM films can be cylindricality, and promptly first length of side of 3D-ROM film equals the word line live width, and second length of side equals the bit line live width; Also can have the nature junction structure, promptly the 3D-ROM film forms naturally at word line and bit line intersection contact position.In addition, 3D-MPROM can also use nF opening mask to define its contained data.The openings of sizes of nF opening mask be the minimum dimension supported of present technique n doubly, so its cost is lower.Simultaneously, 3D-MPROM can also use cross one another accumulation layer to improve storage density.In cross one another accumulation layer, two adjacent accumulation layers are shared one deck address selection line.In addition, 3D-M, especially 3D-MPROM, address selection line can only constitute by a semiconductor material that mixes, and not containing metal film, alloy film or metallic compound film can further improve the manufacturability of 3D-M like this.

Description of drawings

Figure 1A is the skeleton view of a kind of 3D-M; Figure 1B-Fig. 1 CB represents the transistorized 3D-M of multiple based thin film unit; Fig. 1 DA, Fig. 1 DB represent a logical one and " 0 " 3D-MPROM unit respectively; Fig. 1 E represents a kind of 3D-EPROM unit.

Fig. 2 A-Fig. 2 C represents the block diagram of a kind of three-D integrated memory (3DiM) and substrate circuitry thereof.

Fig. 3 A-Fig. 3 D describes multiple single core computer (ConC).

Fig. 4 A-Fig. 4 B describes two kinds of single core players (PonC).

Fig. 5 AA-Fig. 5 CB represents the screen layer of multiple 3DiM.

Fig. 6 AA-Fig. 6 CB represents the interface structure of multiple 3DiM substrate integrated circuit.

Fig. 7 AA-Fig. 7 BC represents the multiple folding address decoder and the wiring layer of their uses.

Fig. 8 A-Fig. 8 B describes the integrated circuit testing mode that a kind of prior art is used.

Fig. 9 A-Fig. 9 C describes a kind of integrated circuit self-test based on 3D-M (3DMST).

Figure 10 AA-Figure 10 BD represents the mode that multiple test data is downloaded.

Figure 11 A-Figure 11 C is the various embodiments of parallel self-test, mixed signal test and printed circuit board system self-test.

Figure 12 AA-Figure 12 BB provides the method for multiple minimizing amount of test data.

Figure 13 represents a kind of " reliable 3DMST test ".

Figure 14 A-Figure 14 CB represents multiple embodiment with dual power of test.

1F that uses in more a kind of 3D-MPROM technological process of Figure 15 A-Figure 15 B and nF opening figure and with the relative position of address selection line graph.

Figure 16 A-Figure 16 C describes multiple autoregistration, cylindricality 3D-MPROM and technological process thereof.

Figure 17 A-Figure 17 ED describes multiple autoregistration, knot 3D-MPROM and technological process thereof naturally.

Figure 18 A-Figure 18 B represents two kinds of 3D-EPROM storage elements that use the metal-semiconductor address selection line.

Figure 19 AA-Figure 19 CB " expression multiple inverted U-shaped connection structure and technological process.

Be easy meter, in this manual,, represent that then on behalf of all, it have the figure of this suffix if figure number lacks due suffix.Refer to Figure 17 A-Figure 17 ED as Figure 17; Figure 17 E refers to Figure 17 EA-Figure 17 ED.

Embodiment

1. three-D integrated memory (3DiM)

Fig. 2 A is the sectional view of a three-D integrated memory (3DiM).3DiM integrates 3D-M array 0A and substrate circuitry 0s.3D-M array 0A contains one or more layers three-dimensional accumulation layer 100.Contain many address selection lines (20a, 30i in each three-dimensional accumulation layer 100 ...) and a plurality of 3D-M (1ai of unit ...).These address selection lines contain the semiconductor material of metal material and/or doping.Transistor 0T on the substrate and interconnection line 0I (0Ia, 0Ib ...) composition substrate circuitry 0s.From the angle of circuit, substrate circuitry 0s contains a substrate integrated circuit 0SC and address decoder 12,18/70 (Fig. 2 B).These address decoders 12,18/70 provide address decoding for 3D-M array 0A.Contact channels mouth (20av ...) be address selection line (20a ...) and substrate circuitry 0s (as address decoder) electrical connection is provided.

In some applications, the address selection line among the 3D-M uses poly semiconductor (referring to Figure 16-Figure 18).Adopt common process to generate the high temperature that polysilicon needs＞500 ℃ of processes.For fear of in these temperature time damage substrate circuitry, the 0I of its interconnection line system (comprising the insulating medium between the metal connecting line) is preferably by refractoriness conductor (as refractoriness metal, the polysilicon that mixes up, metal silicide etc.) and heat stable dielectric (as monox, silicon nitride) formation.Here, tungsten (W) is the candidate material of a good refractoriness conductor.Its technical maturity, conductance only are 5.2 μ Ω cm.Adopt the substrate integrated circuit of tungsten interconnection line can be competent at most of 3DiM application fully, especially can satisfy the requirement of audio-video player ability of data processing.

Fig. 2 B is the planimetric map of 3DiM substrate circuitry 0s.Because the storage element of 3D-M does not take Substrate Area, and the area that its address decoder 12,18/70 accounts on substrate 0s is little, the transistor on the most of area of substrate 0s can be used for forming various substrate integrated circuit 0SC.As described in Fig. 2 C, substrate integrated circuit 0SC contains embedded readable writable memory (embedded RWM abbreviates eRWM as) 80 and flush bonding processor (embedded processor abbreviates eP as) 88 etc.ERWM 80 can comprise embedded RAM (abbreviating eRAM as) and Embedded ROM (abbreviating eROM as).RAM among the eRAM can be SRAM or DRAM etc.; ROM among the eROM is nonvolatile memory (NVM) preferably, as MROM, EPROM, EEPROM, flash etc.EP 88 can comprise Embedded demoder, number-Mo (D/A) converter and decryption engine etc., and a typical eP is data (as phonotape and videotape) player (embeddedmedia-player abbreviates eMP as).Substrate integrated circuit 0SC can combine with 3D-M 0 and finish the data buffer (cache) that various functions: eRAM can be used as 3D-M; EROM can be used as redundant circuit and the software upgrading piece of 3D-M; EP can be used as and forms single core computer (computer-on-a-chip) and single core player (player-on-a-chip is referring to Fig. 3-Fig. 4).In above-mentioned application, substrate integrated circuit 0SC is 3D-M 0 service.On the other hand, 3D-M 0 also can be substrate integrated circuit 0SC service: it can be used as the carrier of integrated circuit testing vector, thereby realizes that self-test based on 3D-M is (referring to Fig. 9-Figure 14).

A. single core computer (ConC)

Fig. 3 A-Fig. 3 D represents the block diagram of multiple single core computer (computer-on-a-chip abbreviates ConC as).The substrate integrated circuit 0SC of ConC contains eRAM 82 and eP 88 etc.3D-M 0 and eRAM 82 form memory block 86.Data from 3D-M generally are stored among the eRAM earlier, and then are handled by eP.Can solve the eP problem different like this with the 3D-M reading speed.The specific embodiment of this method can be referring to Figure 17.This hierarchical structure of ConC (3D-M 0 → eRAM82 → eP 88) is similar to the hierarchical structure (HDD → RAM → CPU) of conventional computing machine.In conventional computing machine, because of hard-disk capacity is big, it is used as main memory carrier, but because of its visit first the time long (～ms), it needs RAM as its data buffer (cache).In ConC, the 3D-M capacity is big, and it also can be used as main memory carrier, and simultaneously, to visit the time first long slightly because of it, and it also needs eRAM 82 as its cache.But, because the time of visiting first of 3D-M (～us) short far beyond hard disk.So 3D-M required, to lack more than the required RAM of HDD as the eRAM of cache.

The software code of ConC is suitable for being stored among the 3D-M, and data generally can be stored among eRAM and/or the eROM.When the software code of ConC downloads to eRAM, it can with the same eRAM 82 of data sharing (Fig. 3 A) that is stored among the eRAM, or separate in two sector 82a, the 82b of eRAM 82 (as sector 82a storage code, sector 82b stores data) (Fig. 3 B).For being stored in data among the eROM 84, they can download to earlier among the eRAM 82, and then carry out there; Or directly execution (Fig. 3 C) in eROM 84.In order to simplify hardware design, ConC can also use the scheme (Fig. 3 D) of address translation.3D-M 0, eRWM 80 can form a unified storage space 86S.Address 86A from eP 88 at first is sent to an address spaces piece 86T, and this address spaces piece 86T is considered as this address 86A virtual address and is translated into physical address 86TA.This physical address 86TA is sent to the address decoder 164D of this storage and uniform space 86S.Then, according to this physical address 86TA decision reading of data from 3D-M 0 or eRWM 80.A specific embodiment of address spaces can apply for that " three-dimensional storage " etc. is in first to file referring to PCT.

At data (as e-book, map etc., especially audio-video works) storage aspect, ConC can be used for realizing single core player (player-on-a-chip abbreviates PonC as).PonC provides good copyright protection for data supplier.Existing data distribution is generally undertaken by CD (as CD, DVD etc.).Because of CD can not be integrated with data (as phonotape and videotape) player, the bootlegger can be at an easy rate steals source book from the interface of CD and data player.And shown in Fig. 4 A, in PonC, integrate as the 3D-M 0 and a data player eMP 88MP of data carrier.Demoder 88DP among the eMP 88MP to source book handle (as the decoding etc.).Even more ideal is that D/A converter 88DA is converted to simulation audio-video signal 89a with digital audio-video signal 89d in a slice.In addition; if source book be in processing factory, utilize masking film program or before sale by data supplier etc. by means " curing " such as electricity programmings in 3D-M; so source book in use not in any form by the two learn; it duplicates with being difficult to be digitized, so PonC can provide extremely strong copyright protection.PonC helps the miniaturization of " walkman ", " Knapsack computer (wearable computer) " etc., and they only need chip, battery and an output device (earplug or screen) from now on.

For the 3DiM that uses 3D-MPROM data on file or other sensitive data, in order to prevent that professional piracy person from stealing its contained data by peeling off anti-design (reverse engineering) means such as (de-layering) from the information opening figure, can encrypt the contained data of 3D-MPROM.Simultaneously, but can make full use of the good integration of 3D-M, in substrate integrated circuit 0SC, form in a slice crypto key memory 85 (Fig. 4 B) in the decryption engine 88DE and a slice.The contained information of 3D-MPROM is decrypted in sheet, and the data 89dd after the deciphering directly is sent on the substrate and handles among other integrated circuit block 0SCX.Like this, be difficult to design to 3D-MPROM is counter.

B. shielding

In 3DiM, when substrate circuitry during at high-speed cruising, it may can produce interference to the data read of 3D-M.For avoiding this interference, be necessary between substrate circuitry and data read line (as bit line), to form a screen layer 10S in some applications.Fig. 5 AA-Fig. 5 CB has described three kinds of screen layers.Fig. 5 AA and Fig. 5 AB are the sectional view of first kind of 3DiM with screen layer 10S and the planimetric map of screen layer 10S.The screen layer 10S of this embodiment one can cover the metallograph 0IS of most of substrate circuitry 0s.Fig. 5 BA and Fig. 5 BB are the sectional view of second kind of 3DiM with screen layer and the planimetric map of screen layer 10S.Among this embodiment, word line layer 20a separates remaining 3D-M 0 and substrate circuitry 0s.Because word line pitch is the minimum spacing of this technology, and word line 20a generally is in static state and (promptly only is in GND and V _RUnder two electromotive forces), so word line layer 20a can be used as screen layer 10S and the most of electromagnetic interference shield between substrate circuitry 0s and the 3D-M 0 is fallen.Fig. 5 CA and Fig. 5 CB are the sectional view of the third 3DiM with screen layer and the planimetric map of screen layer 10S.Because the power supply interconnection layer of substrate circuitry generally is positioned at the top layer of substrate circuitry, it can be as the screen layer 10S of substrate circuitry.In order to reduce the electromagnetic interference (EMI) between substrate circuitry 0s and the 3D-M 0, preferably can dwindle V as far as possible _DDThe interval d of interconnection line 0Ib1 and GND interconnection line 0Ib2.Notice that in Fig. 5 BA-Fig. 5 CB, ready-made wiring layer is used as screen layer, do not make a screen layer 10S so need not aim at shielding.

C. service wire

Fig. 6 AA represents a 3D-M storage array that designs according to a conventional method and is arranged in its contact channels mouth 20av-20hv all around.Fig. 6 AB is that it is along A ' A " sectional view.All around past from the substrate integrated circuit of storage array below, these contact channels mouth 20av-20hv and storage array form " intensive net " together.This road " intensive net " is difficult to and extraneous (chip is outer) interface the substrate integrated circuit.

Substrate integrated circuit and extraneous interface can use means such as embedded lead-in wire and/or address selection line bending for convenience.Fig. 6 BA-Fig. 6 BB describes a kind of embedded lead-in wire 20ei that utilizes.It is particularly suitable for encapsulation such as turning-over of chip (flip-chip), BGA.Here, leaving the gap between many address selection lines: between word line 20p and 20q, leave the first gap 20gp, between bit line 30p and 30q, leave the second gap 30gp (Fig. 6 BA).Space between the first gap 20gp and the second gap 30gp can be used for forming a platform pad (landing pad) 20lp1.Platform pad 20lp1 in the accumulation layer 100, the 20lp1 ' in the accumulation layer 200 and contact channels mouth 20lv1-20lv3 constitute embedded lead-in wire 20ei (Fig. 6 BB), and it provides interface for the substrate integrated circuit.Embedded lead-in wire 20ei almost can be distributed in the optional position of chip, and its length is shorter, and this helps to improve interface rate.

Fig. 6 CA-Fig. 6 CB describes a kind of method that substrate integrated circuit and extraneous interface are provided that bends by address selection line.Word line 20a-20h is divided into two groups: word line group A comprises word line 20a-20d; Word line group B comprises word line 20e-20h.Every group of word line bent (Fig. 6 CA), thereby forms interface channel 20gpb, 20gpb ' (Fig. 6 CB) between its contact channels mouth 20av-20dv, 20ev-20hv.The lead-in wire that these interface channels allow the substrate integrated circuit by and with extraneous interface.In addition, the spacing d of contact channels mouth _CvDesign more flexibly, it can be than the d of the 3D-M of conventional method design _Cv(the d of the 3D-M of conventional method design greatly _CvEqual the spacing d of address selection line _Al, referring to Fig. 6 AA), the layout design of this more convenient address of energy code translator.

D. address decoder is folding

A kind of method of the 3D-M of raising capacity is to improve its array efficiency.Array efficiency is the area of storage array and the ratio of entire chip area.Because the peripheral circuit and the storage array of conventional memory all are positioned in the substrate, peripheral circuit generally can only be positioned at storage array " outside ", so array efficiency generally～60%.On the other hand, because the storage array of 3D-M is higher than substrate, and peripheral circuit can be folded into the storage array below (referring to United States Patent (USP) 5 by wiring layer, 835, Figure 14 of 396), so storage array almost can occupy the whole area of chip, thereby obtain being bordering on desirable array efficiency.Simultaneously, for the integrated 3D-M of substrate circuitry, its wiring layer can utilize interconnection line layer ready-made on the substrate circuitry (Fig. 2 A), so be not required to be the extra interconnection line layer of wiring layer manufacturing, this can simplify technological process.Fig. 7 AA-Fig. 7 BC has described the wiring layer that multiple address decoder is folding and they use.

It is folding that Fig. 7 AA-Fig. 7 AC has described a kind of address decoder of private wiring layer that uses.This embodiment contains interconnection line 0R and storage array 0A.Interconnection line 0R contains four layers of wiring layer 0r1-0r4, and storage array 0A contains four layer address selection wire 20a ', 30a ', 20a, 30a.Every layer of wiring layer (30a, 20a, 30a ', 20a ') uses (Fig. 7 AA, Fig. 7 AB) for an address selection line layer (0r1-0r4) separately, so these wiring layers are called as private wiring layer.The code translator that wiring layer 0r2 will link to each other with word line 20a is folded under the storage array 0A; Wiring layer 0r1,0r3,0r4 also have similar functions.Correspondingly, peripheral circuit almost can be positioned over any position (Fig. 7 AC) under the storage array 0A: line decoder 12l, 12r can place its right and left; Column decoder 18t, the 18b both sides that can be placed on it down; Line decoder 12tl on the storage array angle (being connected with corresponding word line) by connecting line 0cw can be placed on storage array 0A slightly in the position below.Therefore, all peripheral circuits all can be positioned at storage array 0A.Clearly, the address selection line that private wiring layer support two ends drive (as word line and the bit line of 3D-EPROM, and the word line of 3D-MPROM).

Fig. 7 BA-Fig. 7 BC has described a 3D-M with shared wiring layer.Can know that from its title two-layer address selection line is shared a wiring layer, share wiring layer 0r1 ' as word line 20a and bit line 30a, word line 20a ' and bit line 30a ' share wiring layer 0r2 ' (Fig. 7 BA, Fig. 7 BB).Similarly, wiring layer 0r1 ', 0r2 ' are folded to (Fig. 7 BC) under the storage array 0A with code translator.It is fit to the address selection line of single-ended drive.

E. support the 3D-M of high-temperature operation

In some application of 3DiM, especially among the ConC, 3D-M may need to bear higher operating ambient temperature.At high temperature, use the 3D-M of polycrystalline or amorphous silicon may have bigger leakage current.In order to guarantee its normal operation, can in 3D-M, use to have gap length (band-gap) semiconductor material, as C, SiC _xDeng; Also can mix elements such as C, O, N at the semiconductor material that 3D-M uses by modes such as ion injections, these elements also can be regulated the gap length of semiconductor material among the 3D-M.Correspondingly, the 3D-ROM film 22 of Fig. 1 DA can contain a floor height gap length semiconductor material, as SiC _x(x＞0), SiO _y(y＞0), SiN _z(z＞0).

2. based on the self-test (3DMST) of 3D-M

In above-mentioned 3DiM, the substrate integrated circuit is the 3D-M service.On the other hand, 3D-M also can be the service of substrate integrated circuit.One of them exemplary is based on the self-test (3DMST) of 3D-M.

Trigger (muxed flip-flop the abbreviates Mux-FF as) series connection that " design that is easy to test (Design-for-test; abbreviate the DFT design as) " that existing integrated circuit adopts will have the multichannel selection function forms at least one scan chain (scan chain).In test process, at first with input test vector (input test vector, abbreviate ITV as) the immigration scan chain, then with operation result-output test vector (output test vector of tested circuit (abbreviating CUT as), abbreviate OTV as)-shift out scan chain, and compare with expected test vector (expected test vector abbreviates ETV as) in the tester (tester).If all OTV all conform to ETV, then this CUT is by this test.

Fig. 8 A is a typical C UT 0cut.It contains three pipeline stages (pipelined stage) S1-S3.Each level (for example S1) contains a plurality of triggers (01f, 02f) and a logical circuit network (1N), and the output of previous stage (S1) logical circuit network (1N) is the input X3 of back one-level (S2) trigger (03f).In this manual, all CUT are example with Fig. 8 A.

Fig. 8 B is the CUT that adopts conventional DFT.It is changed to Mux-FF01sf-04sf entirely with all the trigger 01f-04f among Fig. 8 A.Be easy meter, all logical circuit network 1N, 2N among Fig. 8 A are merged into a circuit network 12N.Input D, the SI of Mux-FF is by " scanning useful signal (SE) " control: when SE when low, the trigger among the mux-FF uses conventional input D; As SE when being high, its uses scanning input SI.Here, Mux-FF 01sf-04sf joins end to end and forms the one scan chain; ITV 002 is by input end SI 00si input, and OTV 006 is exported by output terminal SO 00so.In this embodiment, the width of ITV 002 is 3, and the width of OTV 006 is 2.

A.3DMST Ce Shi notion

Existing measuring technology is difficult to high speed integrated circuit is realized with speed test (at-speed testing).Tester costs an arm and a leg, and does not support on-the-spot test and field diagnostic.Along with 3D-M, the especially appearance of 3D-ROM, industry member has had a kind of high capacity, cheap storer.Sort memory is the ideal carrier of test data (as ITV and ETV).What is more important, 3D-M can be integrated on the chip with CUT at an easy rate.In fact, this integrated 3D-M and CUT are a kind of 3DiM (referring to Fig. 2 A), and its integration mode is to the layout design influence very little (referring to Fig. 2 B) of CUT.After integrated, very big bandwidth (referring to Figure 17) is arranged between 3D-M and the CUT, so can easily realize with the speed test.Clearly, 3D-M supports the on-the-spot self-test of CUT.Correspondingly, this means of testing is called as the self-test (3D-M-basedself-test abbreviates 3DMST as) based on 3D-M.

In fact, the 3D-M array not necessarily will cover the chip area of whole C UT.Do not have cabling requirement as the adjacent two layers interconnection line in some zone of CUT, then can in this zone, form the 3D-M array.Like this, the introducing of 3D-M might not need to increase new interconnection line layer, thereby reduces fringe cost.On the other hand, when the CUT operate as normal, 3D-M there is no need in running order; It only just needs work when test.So when the CUT operate as normal, can utilize State Control end 6E to force 3D-M to enter " soft disconnection " pattern (referring to Figure 14 DD), to cut down the consumption of energy.

Fig. 9 A is the block diagram of a kind of 3DMST integrated circuit (abbreviating 3DMST-IC as), and Fig. 9 B is a kind of process flow diagram of 3DMST test.3DMST-IC contains CUT 0cut, 3D-M 0 and test vector buffer zone (test-vector buffer abbreviates TVB as) 206.3D-M 0 storage its test data (as ITV and ETV).TVB 206 contains ITV buffer zone 202 and ETV buffer zone 208.3D-M 0 contained test vector 206td at first downloads in the test vector buffer zone 206.It comprises the step that ITV 002 is downloaded to ITV buffer zone 202 (step 222) and ETV002 is downloaded to ETV buffer zone 208 (step 224).CUT 0cut obtains OTV 006 (step 223) after with ITV 002 computing.Comparer 210 is OTV 006 and ETV 008 relatively.As conform to (step 226), or do not conforming to but need further diagnose or prepare secondary and screen under the situation of (step 225), produce a new 3D-M address, and repeating step 222-226, up to 3DMST test finish (step 227); Under other situation, can think that CUT is not by test (step 228).

Fig. 9 C describes the structure of the 3D-ROM array 0A and the TVB 206 that are loaded with a test data in detail.They can finish the step 222,224 among Fig. 9 A-Fig. 9 B.Contain many word lines (20a) and multiple bit lines (30b) among the 3D-ROM array 0A, and the diode of a plurality of representative test datas (1ab-1aj).In this embodiment, be loaded with two test vectors (006,006 ') on the word line (20a).They all contain 5 bit test data, comprise 3 ITV and 2 ETV.Based on row address 2 and column address 2c, test vector 006 is sent among the TVB 206.In TVB 206, trigger 1f1-1f3 constitutes ITV buffer zone 202, and trigger 1f4-1f5 constitutes ETV buffer zone 208.

Integrate because 3D-M 0 and TVB 206 are the forms with three-dimensional, test vector contained among the 3D-M can transfer among the TVB 206 abreast by a large amount of contact channels mouths, so the interface between them has very big bandwidth.Add that the trigger 1f1-1f5 among the TVB 206 is high speed flip flop, so support with speed (at a high speed) test with the integrated CUT of this form.In Fig. 9 C, test vector 006 is directly delivered among the TVB 206 through column decoder 70.Another kind may be earlier test vector 006 to be copied among the eRAM, it is delivered to TVB 206 (referring to Figure 17) from eRAM again.

Figure 10 AA-Figure 10 BC describes two kinds of methods that test data contained among the 3D-M 0 are downloaded to CUT: a kind of is that (Figure 10 AA-Figure 10 AD) downloaded in serial, and promptly test vector is shifted in the shift-in test chain of flip-flops one by one; Another kind is parallel download (Figure 10 BA-Figure 10 BC), and promptly test vector is inputed in the test trigger by parallel.

Figure 10 AA is an embodiment of serial test trigger (serial test flip-flop abbreviates SL-TFF as), and it is identical with the Mux-FF that uses among Fig. 8 B.Figure 10 AB is a 3DMST-IC (serial-load3DMST-IC abbreviates SL-3DMST-IC as) who uses serial to download.Compare with Fig. 8 B, the input SI 00si of the first SL-TFF 01sf is the ITV 002 that comes from ITV buffer zone 202; The output SO 00so of position, end SL-TFF 04sf directly compares with the ETV 008 that comes from ETV buffer zone 208; Gained CO 00co is as a result delivered to rear end discriminator circuit 00pp, whether passes through this test with decision CUT.ITV buffer zone 202 all contains parallel input, serial IOB (parallel-in-serial-outmodule abbreviates PISO as) with ETV buffer zone 208.Their output 202i, 208o carries out under the driving of buffer zone clock CKI 202c, CKO 208c respectively, and input 202td, 208td carry out under the control of parallel input control signal PEI 202p, PEO 208p respectively.When beginning 3DMST test, reset signal 00cl is with counter 00ctr zero setting.Then, along with the arrival of each clock CKT00ct, counter 00ctr provides the new address of a 3D-M.

Figure 10 AC is a kind of sequential chart of SL-3DMST-IC.In this embodiment, CK, CKI, CKO use identical clock source, and PEI, PEO use identical clock source.In clock period T1-T3, serial downloading control signal SE 00s is high, and n input test vector ITV (n) is shifted among the shift-in SL-TFF 01sf-03sf one by one.When clock period T4, SE 00s step-down, SL-TFF 03sg-04sf are accepted conventional input X3, X4.These conventional input X3, X4 are the operation result of ITV (n) in circuit network 12N, i.e. OTV (n).OTV (n) is shifted out when clock period T5-T6 one by one, and compares with ETV 208o.Here, these steps of input, computing and output need 4 clock period altogether, and they form a test period STC.Because of the width of OTV is 2, only the comparative result CO 00co in clock period T5-T6 is just effective, so T5-T6 is called as effective OTV clock period.Notice that the ETV (n) corresponding with ITV (n) in first test period (T1-T4) just is read out in second test period (T5-T8).

Figure 10 AD represents a kind of rear end discriminator circuit 00pp of this 3DMST-IC.In this embodiment, as long as, do not conform to ETV (being that 00co is " 1 ") as OTV in the clock period at any one effective OTV, then the output P/F00pf of discriminator circuit 00pp is latched as " 1 ".This rear end discriminator circuit 00pp also contains storer 208pn, counter 208etr and comparer 208lt, and they determine whether the CO in the clock cycle at this moment is effective comparative result.Wherein, the width of storer 208pn storage OTV; Counter 208ctr is recorded in a test period and begins the clock number of back experience; Comparer 208lt compares this two number, if clock number less than the width of OTV, then comparative result is effective.

Figure 10 BA-Figure 10 BB is two embodiment of parallel testing trigger (parallel test flip-flop abbreviates PL-TFF as).PL-TFF 01pf has relatively output terminal CO of a desired value input end ER and.Compare with the data of exporting Y from trigger from the data of ER, its result is exported by CO.Data selecting side PE decision trigger 0f catches conventional input D or from the test data PI of 3D-M.Figure 10 BA also has a switch 00sw.When normal operation circuit, switch 00sw separates comparator circuit 00xo and CUT; In test process, switch 00sw just connects.

Figure 10 BC is the 3DMST-IC (parallel-load 3DMST-IC abbreviates PL-3DMST-IC as) of the parallel download of a use.Here, TVB 206 is a simple buffer zone, and its input is carried out under the control of clock CKP ', and output is carried out under the control of clock CKP.Test vector in TVB 206 (202a-202c, 208a-208b) is by parallel inputing among the PL-TFF 01pf-04pf of while.Because PL-TFF 01pf-02pf is the first order S1 of CUT streamline, they are processing signals (referring to Fig. 8 A) not, and they do not have corresponding desired value, so only need the comparative result 00co of PL-TFF 03pf-04pf is delivered to the rear end discriminator circuit.

The operation of PL-3DMST-IC can illustrate in conjunction with the sequential chart among Figure 10 BD.Under the control of clock CKP,, the test data 206td among the 3D-M is delivered among the TVB 206 at moment tx.In clock period Ta, parallel input control signal PE puts height, and all test vectors are downloaded among the PL-TFF 01pf-04pf by parallel.Then, obtain OTV as a result after the ITV 202a-202c process CUT computing.In clock period Tb, PE puts low, and at this moment OTV is caught and assesses by the PL-TFF of streamline next stage.Correspondingly, a test period PTC contains 2 clock period.

B.3DMST Ce Shi application

In actual applications, 3DMST can use parallel self-test (Figure 11 A), and it also can be applied to mixed signal test (Figure 11 BA-Figure 11 BC), system self-testing situations such as (Figure 11 C).

Most of logical circuits contain the multi-strip scanning chain.Figure 11 A describes the 3DMST-IC of the parallel self-test of a support.In this embodiment, test vector 206tda, 206tdb are downloaded to ITV 206a, 206b respectively.This download step is parallel carrying out.Like this, can parallel testing to two CUT 0euta, 0cutb, thus shorten the test duration.

Mixed signal circuit contains simulating signal.Because number-Mo (D/A) conversion is fast more a lot of than analog-to-digital conversion, so when simulating signal is tested, can convert ITV and/or ETV to simulating signal where necessary.Figure 11 BA describes the 3DMST-IC of a support mixed signal test.In this embodiment, the input 002a of CUT 0cutm contains simulating signal, and output 006 is digital signal entirely.Simulating signal emulator 0sg converts ITV 002d to simulating signal 002a in a slice, and delivers to CUT 0cutm.Figure 11 BB represents a kind of simulating signal emulator 0sg.It comprises a D-A converter 0dac and a frequency mixer (mixer) 0sm.D-A converter 0dac converts ITV 002d to a simulating signal 002a '; Frequency mixer 0sm mixes it with a carrier wave 002cw, thereby produces required test signal 002a.On the other hand, the 0cutm output among Figure 11 BC comprises simulating signal 006 then can convert ETV 008 to simulating signal 008a by D-A converter 0dac ', and at analog comparator 210a place relatively, to obtain comparative result 00co.Analog comparator 210a can contain just like the differential amplifier of 17C and an integrator.

Figure 11 C describes the 3DMST-IC of support printed circuit board (PCB) system self-testing.This PCB 268 also contains chip 264,266 etc. except that containing a 3DMST-IC chip 262.The 3D-M of 3DMST-IC262 not only is loaded with the test vector of 3DMST-IC262, also is loaded with the test vector of chip 264,266.3DMST-IC 262 can support the system self-testing to whole PCB268 like this.Because the 3D-M capacity is big, the coverage of this system self-testing is wider.

In the embodiment of Figure 11 C, first interface 269 is PCB system 268 and extraneous standard interface, and second interface 261 can be used to 3DMST-IC262 is tested separately.The purpose of test is the 3D-M inerrancy that guarantees among this 3DMST-IC262 separately.This test is a memory test, and it can be finished by middle low speed tester.In case 3DMST-IC262 is by this independent test, then the PCB system self-testing can carry out at high speed.

C. reduce amount of test data

In order to reduce the amount of test data that is stored among the 3D-M, can use test data compression (Figure 12 AA-Figure 12 AB), or mixed type test (Figure 12 BA-Figure 12 BB).

Figure 12 AA is the 3DMST-IC of use compression verification data.With Fig. 9 A relatively, at the input end of CUT one input reduction of data device 0dc (data de-compressor) is arranged, at output terminal one output data compressor reducer 0cp is arranged.The seed data 002c of 3D-M 0 storage ITV, it produces ITV 002 through input reduction of data device 0dc.The 006c of operation result 006 after output data compressor reducer 0cp compression just compares with ETV 008.

Figure 12 AB represents a kind of input reduction of data device 0dc.It is a LFSR generator 0dc.Before test, control signal SL 0sl puts height, and seed data 002c is downloaded among the trigger 01if-03if.In test process, SL 0sl puts low, and LFSR generator 0dc produces quasi random number.Output data compressor reducer 0cp can use characteristic analyzer (signatureanalyzer).In actual applications, can adopt in the above test data compression scheme one or both according to circumstances.

Figure 12 BA-Figure 12 BB describes two kinds of mixed type method of testings.The mixed type test is meant uses at least two kinds of means of testing in test process, comprise 3DMST, built-in self-test (BIST test), extraneous sweep test (external scan test abbreviates the EST test as) etc.The mixed type test makes full use of these means of testing speciality separately.Shown in Figure 12 BA, the basic circuit piece (as RAM etc.) the BIST test can be adopted.In the circuit design of a high level (as the function/structured testing of chip level) can adopt 3DMST test.And for example shown in Figure 12 BB, can use 3DMST and/or BIST test, the EST test is then adopted in the middle low speed test of circuit the high speed test of circuit.Can reduce the integrated testability cost like this.Moreover, can test important test vector (test vector of promptly in chip operation, makeing mistakes easily) with 3DMST, and test the general test vector with EST.Like this, find that the possibility of run-time error is bigger during self-test.The mixed type test can be optimized testing cost and testing reliability.

D.3DMST Ce Shi Reliability

In the 3DMST test process, do not conform to ETV as OTV, two kinds of possibilities are arranged: a kind of may be the CUT defectiveness; Another kind may be the 3D-M defectiveness.Second kind of possible situation can cause the yield rate unnecessary loss.In order to improve the confidence level of 3DMST test, can use " reliable 3DMST test ", guarantee that promptly 3D-M is error-free, wrong 3D-M is carried out error correction (Figure 13); Or CUT carried out " secondary screen (being dual test) ", promptly the chip by the 3DMST test is not carried out an EST test (Figure 14 A-Figure 14 D) again.

Figure 13 describes one and uses the process flow diagram of " reliable 3DMST tests ".This test guarantees with the 3D-M that is loaded with test vector error-free.Correspondingly, before the 3DMST test, need test (step 231) to 3D-M 0.This test can be finished by low speed tester in, and its testing expense is comparatively cheap.As 3D-M 0 by test (step 232), then to the error correction (step 234) of should trying one's best of the mistake of its discovery.As error correction unsuccessful (step 235), then CUT is carried out EST test (step 236) and/or dual test (step 237 is seen Figure 14).

Figure 14 A-Figure 14 CB describes multiple integrated circuit (DTC-IC) with dual test function (dual-testing capacity abbreviates DTC as).DTC-IC can also support the EST test except supporting the 3DMST test.Shown in Figure 14 A, when dual test, CUT is carried out " secondary examination ", promptly the chip of not testing by 3DMST is carried out an EST test (step 230) again.Still can not test by EST as this chip, then it is considered to waste product.The time of EST test when shortening dual test, when 3DMST tests, problem test vector (questionable test vector abbreviates QTV as, i.e. the ITV that do not conform to of OTV and ETV) can be noted (step 229).When EST tests, can only carry out test (step 229C) to QTV 004.

Figure 14 BA describes a SL-3DMST-IC with DTC function.It has increased MUX 00m1,00m2 separately at the two ends of SL-TFF chain 00sfc.The ITV of MUX 00ml decision input SL-TFF chain 00sfc is from the ITV 202i of 3D-M 0 or the test data ESI 00esi of the tester that comes from the outside.On the other hand, MUX 00m2 determines that the data 00eo that exports is comparative result CO 00co or OTV SO 00so from SL-TFF chain 00sfc.

Figure 14 BB is the rear end discriminator circuit 00pp ' of this SL-3DMST-IC.With Figure 10 AD difference is that it contains a QTV storer 204.This QTV storer 204 contains a plurality of QTV address register 204a-204d, and a plurality of comparative result register 204af-204df.QTV address 2QA can comprise the address 2 and the position 208n of position in OTV that do not conform to of 3D-M 0.Here, the position that do not conform to be meant do not conform among OTV and the ETV, it can help to find the defective of CUT.As an effective comparative result CO 00co is " 1 ", and then 2QA is sent to a QTV address register 204a, and former 2QA is displaced to next QTV register successively.In case output 00pf is " 1 ", it represents that this CUT does not test by 3DMST.

Figure 14 CA-Figure 14 CB describes a PL-3DMST-IC with DTC function.It is changed to parallel serial test trigger (parallel-serial test flip-flop abbreviates PS-TFF as) 01df-04df with all the PL-TFF 01pf-04pf among Figure 10 BC.These PS-TFF01df-04df form a PS-TFF chain 00dfc.Each PS-TFF is at control signal DE[0:1] control of 00de makes decision and catch one from following three input: conventional input D; Come from ITV ESI extraneous scanner, that serial is downloaded; From ITV PI 3D-M 0, parallel download.Its embodiment is represented by Figure 14 CB, answers its operation of easy to understand for being familiar with this professional personage.

3.3D-ROM structure

Because it is simple in structure, be easy to make, very likely become first kind of mass-produced 3D-M based on the three-dimensional read-only storage element (3D-ROM) of diode.Simultaneously, but the good integration of 3D-ROM can be widely used among the ConC/PonC it.The present invention has done further perfect to the 3D-ROM structure.

A.3D-MPROM

In various 3D-ROM, masked edit program 3D-M (3D-MPROM) technology especially is easy to realize.Whether 3D-MPROM distinguishes logical zero and " 1 " by the existence of access opening.Correspondingly, these access openings are also referred to as the information opening.The 3D-MPROM chip cost comprises address selection line (word line and bit line) photoetching cost and information opening photoetching cost.Address selection line photoetching cost is not high.This be because: the address selection line graph has very strong repeatability, can use phase shift mask version (PSM) and the maturation photoetching technique; Simultaneously, the address selection line mask can be used in the 3D-MPROM chip of One's name is legion, so the address selection line mask cost that each 3D-MPROM chip is shared is lower.Comparatively speaking, information opening photoetching cost is higher.Fortunately, can use nF opening mask and photoetching programmed technology to reduce its cost.Figure 15 A-Figure 15 B has compared 1F opening mask and nF opening mask and the application in 3D-MPROM technology thereof.

Figure 15 A represents conventional 1F opening figure and the relative position of address selection line graph on silicon chip in the 3D-MPROM technology.Because access opening drops in the intersection region of word line and bit line, thereby the size of routine information opening (as 1ca) preferably is less than or equal to the live width of address selection line (as 20c, 30a), i.e. 1F.In fact, 3D-MPROM can use opening with large-size (referring to Figure 16-Figure 17).Figure 15 B represents nF information opening figure and the relative position of address selection line graph on silicon chip among the 3D-MPROM.Here, n=2 refers to that promptly information opening (as 1ca+) is of a size of 2 times of address selection line (as 20c, 30a) live width.For the 3D-MPROM of the 0.25 μ m technology of use, information opening mask can be used 0.5 μ m technology.In addition, because adjacent 2F information opening may be incorporated in together, and mask is lower with the alignment precision requirement of its INFERIOR GRAPH during photoetching, and the photoetching cost of information opening can greatly be reduced.The embodiment of Figure 16-Figure 17 all uses nF opening mask.Certainly, they also can use 1F opening mask.

Figure 16 A-Figure 16 C describes multiple autoregistration, cylindricality 3D-MPROM (self-aligned pillar-shaped3D-MPROM abbreviates SP 3D-MPROM as) and technological process thereof.In the technological process of SP 3D-ROM, there is not an independent 3D-ROM film etch step, the 3D-ROM film forms in word line etch step and bit line etch step naturally.In SP 3D-MPROM, the 3D-ROM film is a cylindricality, and its first length of side equals the word line live width, and second length of side equals the bit line live width.Accumulation layer is intersected mutually among the embodiment of Figure 16 A-Figure 16 BD, and accumulation layer is isolated mutually among Figure 16 C.

Figure 16 A represents the 3D-MPROM (inter-digitated SP 3D-MPROM abbreviates ISP3D-MPROM as) that an interlayer intersects.In this embodiment, accumulation layer is intersected and adjacent accumulation layer shared address selection wire mutually, as accumulation layer ML 100 and accumulation layer ML 200 shared word line 20a.The address selection line of sharing requires the diode polarity of adjacent accumulation layer opposite, be the film reversed in order of storage element: the hierarchy of supposing the 3D-ROM film 22 among the accumulation layer ML 100 is N+, N-, P+ (arranging by the sequencing that forms), and then the hierarchy of the 3D-ROM film 22 ' among the accumulation layer ML 200 is P+, N-, N+.For the storage element between word line 20a and bit line 30c, have one deielectric-coating 23 is set between word line and the bit line, it isolates word line and bit line, so this storage element is represented logical zero; For the storage element between word line 20a and bit line 30b, an information opening 24 is arranged between word line and the bit line, electric current can flow to bit line from word line, so this storage element is represented logical one.Notice that owing to used nF opening mask, along on the direction of high-rise address selection line (word line 20a), the length of side of information opening 24 is greater than the live width of lower-layer addresses selection wire (bit line 30b).

When reading ISP 3D-ROM (as accumulation layer ML200), on word line 20a, add and read voltage V _R, go up the detection read current at bit line 30a '-30c '.Simultaneously,, go,, add V on the 30a-30c as on 20a ', adding 0V thereby avoid read current to flow in these accumulation layers to adding a bias voltage on address selection line 20a ', the 30a-30c on other accumulation layer _R

Figure 16 BA-Figure 16 BD is a kind of process chart of ISP 3D-MPROM.At first, form a bit line film and a 3D-ROM film 22 continuously, utilize first etching etching bit line film 30a and a 3D-ROM film 22 successively then, form bit line bar.Between bit line bar, fill low layer medium 26, re-use method such as CMP with its complanation and expose a 3D-ROM film 22 (Figure 16 BA).The another kind of scheme of bit line bar is to form bit line film 30a and a 3D-ROM film 22 backs formation one bit line buffer film 26e (Figure 16 BA ') continuously.That this bit line buffer film preferably conducts electricity and the shaping that when first etching, is etched.This scheme can be used to form seamless 3D-ROM unit (seeing " method that improves yield rate ").

After this, formation is provided with deielectric-coating 23 on the low layer medium 26 after the complanation.As use nF opening mask, deielectric-coating 23 best and low layer medium 26 employing different medium materials then are set.For example, deielectric-coating 23 is set and uses silicon nitride or SiN _x/ SiO ₂Sandwich construction (SiN _xAt SiO ₂Below), and low layer medium 26 uses monox.Afterwards, nF opening mask is carried out photoetching.The logical zero storage element (as with bit line 30a infall) the photoresist 23pr that locates stays; The logical one storage element (as with bit line 30b infall) resist exposure located is removed so that form information opening 24 (Figure 16 BB).

To being set, deielectric-coating 23 carries out second etching after the photoetching.This second etching is preferably to being provided with deielectric-coating 23 and low layer medium 26 has etching selection ratio preferably, promptly it quickly etching deielectric-coating 23 is set, but can stop on the low layer medium 26.Here, on the x direction, the length of side of information opening 24 is greater than the live width of lower-layer addresses selection wire (bit line 30b), and this can't influence the function of 3D-MPROM.After second etching, form word line film 20a and the 2nd 3D-ROM film 22 ' (Figure 16 BC) continuously.Then, utilize the 3rd etching etching the 2nd 3D-ROM film 22 ', word line film 20a and a 3D-ROM film 22 (stopping on the 3rd etching line film on the throne 30a) successively, (Figure 16 BD represents the sectional view of its y-z to form the word line bar.Notice that Figure 16 BA-Figure 16 BC is the sectional view of x-z).

Above-mentioned technological process does not use an independent etch step to define 3D- ROM film 22, and 3D-ROM film 22 forms when first etch step and the 3rd etching step naturally.Correspondingly, it and word line and bit line are self aligned.3D-ROM film 22 is a cylindricality, and first length of side 22wx of this cylindricality equals bit line live width 30w (Figure 16 A), and second length of side 22wy equals word line live width 20w (Figure 16 BD).

Figure 16 C represents SP 3D-MPROM (separate SP3D-MPROM the abbreviates SSMMPROM as) sectional view that an interlayer separates.In this embodiment, separate by inter-level dielectric 27 between the accumulation layer and shared address selection wire not.

Figure 17 A-Figure 17 ED describes multiple autoregistration, knot 3D-MPROM (self-aligned natural-junction3D-MPROM abbreviates SN 3D-MPROM as) and technological process thereof naturally.In SN 3D-ROM, there is not an independent 3D-ROM film.Diode junction and similar knot nature are formed on the intersection contact position of word line and bit line, and the part of 3D-ROM film is positioned at word line, and another part is positioned at bit line.Accumulation layer is intersected mutually among the embodiment of Figure 17 A-Figure 17 CD, and accumulation layer is isolated mutually among the embodiment of Figure 17 D-Figure 17 ED.

Figure 17 A represents the SN 3D-MPROM (inter-digitated SN 3D-MPROM abbreviates ISN3D-MPROM as) that an interlayer intersects.Its similar is ISP 3D-MPROM in Figure 16 A, and just ISN 3D-MPROM does not have an independent 3D-ROM film 22.Figure 17 BA-Figure 17 BD represents multiple ISN 3D-MPROM unit.Two storage element 1nj, 110 are arranged in each figure, and wherein storage element 1nj is stacked on the storage element 1l0, and they share an electrode 20a.Storage element 1nj represents logical one, and storage element 110 is represented logical zero.

Figure 17 BA describes a natural P+/N-/N+ diode junction.For storage element 1nj, word line 20a (containing P+ polysilicon or other semiconductor material) and bit line 30a ' (containing N+ polysilicon 30al ', N-polysilicon 30a2 ', N-polysilicon 30a3 ') are in contact with one another and form a natural P+/N-/N+ diode junction at infall, thereby represent logical one.Simultaneously, N-polysilicon 30a3 ' can form another with the word line 20a ' of last layer and tie (referring to Figure 17 A, omit and do not draw) naturally herein.For storage element 1l0,, can not form the nature knot between them, so this storage element is represented logical zero owing to exist one deielectric-coating 23 is set between word line 20a and the bit line 30a (containing N-polysilicon 30a1, N+ polysilicon 30a2).Notice that in this embodiment, address selection line only is made of a semiconductor material that mixes, and not containing metal film, alloy film or metallic compound film, can further improve the manufacturability of 3D-M like this.

Storage element among Figure 17 BA can utilize the common process flow process to form: address selection line 30a, 20a, 30a ' are formed by the standard polysilicon process; After forming all address selection lines, a high-temperature annealing step activates impurity and forms good natural diode junction.Because use higher temperature, the interconnection line of substrate circuitry preferably uses the refractoriness conductor, such as, the polysilicon of doping, refractory metal and alloy thereof or compound.

Figure 17 BB compares with Figure 17 BA, and its word line 20a contains metal material, as tungsten, platinum etc.Form a natural schottky diode 1nj ' at its word line 20a and bit line 30a ' intersection contact position.Similarly, this storage element also can use the common process flow process to form.

Figure 17 BC compares with Figure 17 BA, and its word line and bit line have added one deck metallic material film at least.In this embodiment, bit line 30a ' contains: N-polysilicon 30a2 ', N+ polysilicon 30a5 ', metallic material film 30a4 ', N+ polysilicon 30a6 ', N-polysilicon 30a3 '; Word line 20a contains: P+ polysilicon 20a2, metal material 20a1, P+ polysilicon 20a3.Metallic material film 30a4 ', 20a1,30a3 can reduce the series connection dead resistance of address selection line, improve read rate.In addition, can also have only an address selection line to contain metal material, and another address selection line still use polysilicon (semiconductor).

Similarly, the polycrystalline bit line among Figure 17 BB also can contain metallic material film 30a3,30a4 ', and this represents in Figure 17 BD.The another kind of method that reduces address selection line series connection dead resistance is the polycrystalline address selection line among Figure 17 BA or Figure 17 BB to be carried out metallic ion inject (metal ion implant).Correspondingly, contain certain metal ingredient in the address selection line, so can reduce the series connection dead resistance of address selection line.This method does not need independent metal level, can simplify technological process.

Figure 17 CA-Figure 17 CD is a kind of process chart of ISN 3D-MPROM.This technological process is very similar to the technological process among Figure 16 BA-Figure 16 BD.Figure 17 CA be form bit line bar and with layer in sectional view behind the dielectric planarization.Figure 17 CB is the sectional view after formation is provided with deielectric-coating 23 and nF opening mask carried out photoetching.Figure 17 CC is to the sectional view after deielectric-coating 23 carries out figure conversion and forms the word line film is set.Figure 17 CD carries out y-z sectional view (Figure 17 CA-Figure 17 CC is the x-z sectional view) after etching and the complanation to word line.The technological process of ISN 3D-MPROM is very simple.For the storage element of Figure 17 BA and Figure 17 BB, its address selection line only contains a kind of material, so its etching is easier to implement.

Figure 17 D is the sectional view of the SN 3D-MPROM (separate SN 3D-MPROM abbreviates SSN3D-MPROM as) of interlayer separation.It contains the accumulation layer ML 100 and the ML 200 of two separation, is separated by inter-level dielectric 27 between them.

Figure 17 EA-Figure 17 ED represents the structural drawing of several SSN 3D-MPROM unit.Because adjacent accumulation layer does not have shared word line and bit line in SSN 3D-MPROM, so its structure simple in structure than among Figure 17 BA-Figure 17 BD.Figure 17 EA represents a natural P+/N-/N+ diode junction 1nj who forms between word line 20a and bit line 30b.Figure 17 EB is illustrated in the natural Schottky diode junction 1nj ' that forms between word line 20a and the bit line 30b.The difference of Figure 17 EC and Figure 17 EA is to have added metallic material film 20a1,30b3 in its word line and bit line.Similarly, also can only in an address selection line (especially word line), add metallic material film.The difference of Figure 17 ED and Figure 17 EB is to have added among the bit line 30b metallic material film 30b3.These metallic material film 20a1,30b3 can reduce the parasitic series resistance of address selection line, thereby improve read rate.The another kind of method that reduces address selection line series connection dead resistance is the polycrystalline address selection line among Figure 17 EA or Figure 17 EB to be carried out metallic ion inject (metal ion implant).

B.3D-EPROM first

Figure 18 A-Figure 18 B represents two 3D-EPROM units that use metal-poly semiconductor address selection line.It has used the scheme of Figure 17 BC-Figure 17 BD and Figure 17 EC-Figure 17 ED: added metallic material film 20a1,30c3 in the polycrystalline address selection line, or it has been carried out metallic ion inject (metal ion implant).Can reduce the parasitic series resistance of address selection line like this.Under same program conditions, can the bigger program current of conducting in the address selection line, so the more fast and reliable of programming.Simultaneously, because RC postpones to shorten, reading speed also can accelerate.Anti-fuse film 22af can be clipped in (Figure 18 A, Figure 18 B) between N+ polysilicon 30c2 and the N-polysilicon 30c1, also can be clipped between the P+ polysilicon 20a2 and N-polysilicon 30c1 of Figure 18 A, or be clipped between the word line 20a and N-polysilicon 30c1 of Figure 18 B.

C. inverted U-shaped connection

A lot of address selection lines (as the 30a ' among Figure 17 BA-Figure 17 BD) are complex lines among Figure 16-Figure 18.Complex line contains a high conductive layer and an end low-doped (semiconductor) layer.From its title as can be known, end low doped layer is positioned at the bottom of this complex line.For the access opening of desiring to link to each other with this complex line, adopt mode (referring to Fig. 2 A) conventional, that contact from the below as it, then it is difficult to and end low doped layer formation Ohmic contact.In order to realize Ohmic contact, preferably utilize inverted U-shaped connection from the top and/or the side directly to the contact of the high conductive layer the complex line.Figure 19 AA-Figure 19 CB " expression multiple inverted U-shaped connection structure and technological process.

Figure 19 AA-Figure 19 AB represents two kinds of inverted U-shaped connections to first complex line 30.First complex line 30 is two-layer structures, and it contains low doped layer (end low doped layer) 30lda that a high conductive layer 30mc and is positioned at the bottom.In Figure 19 AA, access opening 30v utilizes the first inverted U-shaped connection 30uc to realize Ohmic contact from the top to first complex line 30.In Figure 19 AB, access opening 30v utilizes the second inverted U-shaped connection 30bc from top and side first complex line 30 to be realized Ohmic contact.

Figure 19 BA-Figure 19 BB represents two kinds of inverted U-shaped connections to second complex line 30 '.Second complex line 30 ' is a three-decker, and it also contains low doped layer (top low doped layer) 30ldb who is positioned at the top, and high conductive layer 30mc is between 30lda, 30ldb.Access opening 30v can utilize the 3rd inverted U-shaped connection 30uc ' to realize Ohmic contact (Figure 19 BA) from the top to second complex line 30 '; Or utilize the 4th inverted U-shaped connection 30bc ' second complex line 30 ' to be realized Ohmic contact (Figure 19 BB) from top and side.Notice that a part of top low doped layer 30ldb is etched away and has exposed a part of high conductive layer 30mc.

Figure 19 CA-Figure 19 CC represents a kind of technological process of the first inverted U-shaped connection 30uc.After access opening 30v is shaped, form complex line 30, and deposit one deck medium 30vd (Figure 19 CA).At this moment, 30 of access opening 30v and complex lines are contactless.In medium 30vd, form two opening 30v1,30v2.Wherein, opening 30v1 exposes access opening 30v, and opening 30v2 exposes (Figure 19 CB) with a part of complex line 30 from the top.Then, in these openings, fill conductor 30uc ' (Figure 19 CC).Afterwards, carry out metallization step again one time, promptly form the structure among Figure 19 AA.

The technological process of the technological process of Figure 19 AB and Figure 19 AA is similar.Just its opening 30v3 also exposes (Figure 19 CB ') with the sidewall of complex line 30, so that complex line 30 is contacted with the side from top.

The technological process of the technological process of Figure 19 BA and Figure 19 BB and Figure 19 AA and Figure 19 AB is similar.Just when forming opening 30v2, preferably a part of top low doped layer 30ldb can be etched away, and expose a part of high conductive layer 30mc.Simultaneously, it can also adopt dual complanation to fill technology such as (dual damascene).Figure 19 CB " the expression one inverted U-shaped sectional view that is connected before conductor filled that uses that dual complanation fills.Except that opening 30v1,30v2, in medium 30vd, also formed a raceway groove 30t.

Though above instructions has specifically described examples more of the present invention, those skilled in the art should understand, under prerequisite not away from the spirit and scope of the present invention, can change form of the present invention and details, for example, 3DMST embodiment in this instructions is all based on Mux-FF, and in fact, it can also be based on LSSD etc.This does not hinder them to use spirit of the present invention.Therefore, except the spirit according to additional claims, the present invention should not be subjected to any restriction.

Claims (10)

1. integrated circuit that carries out self-test based on three-dimensional storage (3D-M) is characterized in that containing:

One substrate circuitry (0s), this substrate circuitry contain a tested circuit (CUT) (0CUT);

At least one 3D-M layer (0), this 3D-M is stacked to be placed to the described CUT of small part top, and by a plurality of contact channels mouths (20av, 30av...) and this CUT coupling, this 3D-M layer is stored to test data (002) or the seed data (002c) of the described CUT of small part.

2. integrated circuit according to claim 1, its feature also is: described 3D-M is 3 D ROM (3D-ROM).

3. integrated circuit according to claim 1, its feature also is: described 3D-ROM is three-dimensional masking film program storer (3D-MPROM) or three-dimensional electric programming storer (3D-EPROM).

4. integrated circuit according to claim 1, its feature also is: described test data is to download among this CUT with serial or parallel mode.

5. integrated circuit according to claim 1, its feature also is:

Described CUT contains a CUT piece (0cuta) and the 2nd CUT piece (0cutb);

Described substrate circuitry also contains one first test vector buffer zone (206a) and one second test vector buffer zone (206b), and the described first and second test vector buffer zones are stored to the test data of the described first and second CUT pieces of small part respectively.

6. integrated circuit according to claim 1, its feature also be, its substrate circuitry also contains at least a in following (A)-(E) structure:

(A) number-Mo conversion block (0dac), the described digital test vector of this number-near small part of Mo conversion block is converted to simulating signal;

(B) data decompressor (0dc), the compressed input test vector of the near small part of this data decompressor decompresses;

(C) data compressor (0cp), the near small part output of this data compressor test vector compresses;

(D) MUX (00m1), this MUX decision input test vector come from the outside tester or 3D-M;

(E) parallel serial test trigger (01df-04df), the input of this parallel serial test trigger is from routine input, extraneous scanner and 3D-M.

7. integrated circuit according to claim 1, its feature are that also its method of testing comprises the steps:

(a) from 3D-M (0), read input test vector and expected test vector (step 222,224);

(b) input test vector is delivered to tested integrated circuit (CUT) and obtain exporting test vector (step 223);

(c) will export test vector and expected test vector ratio (step 210);

(d) compared result is analyzed: if conform to, produce a new 3D-M address, and repeat above step, until self-test finish (step 226).

8. integrated circuit according to claim 7, its feature are that also its method of testing also contains following steps:

(e), CUT is diagnosed or secondary examination (step 225) if do not conform to.

9. integrated circuit according to claim 8, its feature are that also its method of testing also contains following steps:

(f) in this secondary is screened (step 225), CUT is carried out extraneous sweep test (EST) (step 229C), described EST step is only carried out the test vector that output test vector and expected test vector are not inconsistent.

10. integrated circuit according to claim 1, its feature also is: this integrated circuit (IC) chip (262) that contains 3D-M (0) is positioned on the printed circuit board (268), this printed circuit board also contains another integrated circuit (IC) chip (264), and this 3D-M stores the test data or the seed data of this another integrated circuit (IC) chip (264).

Images