CN1967548A - Method for building time domain space mathematical model of tree interconnection circuit - Google Patents

Method for building time domain space mathematical model of tree interconnection circuit Download PDF

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CN1967548A
CN1967548A CN 200610029523 CN200610029523A CN1967548A CN 1967548 A CN1967548 A CN 1967548A CN 200610029523 CN200610029523 CN 200610029523 CN 200610029523 A CN200610029523 A CN 200610029523A CN 1967548 A CN1967548 A CN 1967548A
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CN100405380C (en
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胡志华
袁宝国
周政新
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Shanghai Polytechnic University
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Shanghai Polytechnic University
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Abstract

A time-domain state-space mathematical model to establish interconnected tree circuit, its features is the establishment of time-domain state-space mathematical model including resistance, inductance, capacitance, conductance interconnected tree circuit, and the steps include: step (a), according to the topology structure of the interconnection line trunks and branches of the actual territory, establish the circuit model of pi-resistance, inductance, capacitance, conductance of the interconnection line tree; step (b), determine the trunk and branches cascading number of the circuit model established in the step (a); step (c), according to steps (a) and (b), determine time-domain state-space mathematical model by Kirchhoff voltage law and Kirchhoff current law. The invention introduces conductivity in the mathematical model, making the model closer to reality, and the coefficient matrix form derived from mathematical models is concise, operation fast and results accurate.

Description

Set up the method for the time domain space mathematical model of tree interconnection circuit
Technical field
The present invention relates to a kind of method of setting up mathematical model, particularly a kind of method of setting up the time domain space mathematical model of tree interconnection circuit.
Background technology
Along with the appearance of 0.18 micron integrated circuit processing technique, from the interconnection load time-delay obviously increase.For the standard block ASIC (special IC) that adopts 90 nanometer technologies to realize, the time-delay ratio of circuit unit and interconnection is near 2: 8.That is to say that along with the development of very large scale integration technology, the time delay of interconnection line (interconnect) has become the key factor of decision-making circuit speed.The method for designing of core that traditional with the device is changes to the method for designing that the sequential that with the interconnection line is core drives (Timing Driven).
High speed integrated circuit designing requirement front end comprehensively and between placement-and-routing's instrument in downstream repeatedly designs repeatedly, to obtain timing closure.The quality assessment of layout intermediate result and the adjustment of layout result all require in time time delay to be made assessment at layout stage.If sequential estimate with actual placement-and-routing after the delay situation come in and go out bigger and exist timing conflict, the design number of occurrence from the front end to the rear end to increase greatly, the required workload of acquisition timing closure will be increased widely.
Along with the raising of working frequency of chip and the increase of integrated scale, new requirement is proposed constantly for time delay estimation for accuracy and speed.The appearance of SOC (system on a chip) (SoC) is had higher requirement to the time-delay estimation precision and the speed of model.
Therefore, to satisfy the quick and accurate interconnection line time delay method of high speed circuit design needs are problems that need to be resolved hurrily at present ultra-large high speed integrated circuit (the 0.18 micron following technology) design in foundation.It for the layout design of time delay checking, gate level simulation and performance driving have important significance for theories and practice significance.
The key of time delay appraisal procedure is to manage to set up the various time delay models of interconnection line.From the angle of circuit, the resistance R of only considering interconnection line itself and the RC model of capacitor C are over the ground arranged; The RLC model of considering the interconnection line inductance L is arranged; But immediate with the high speed circuit of reality should be to consider electric over the ground RLCG model of leading G again.
Formerly in the technology, inventor Xu Qin defends, and Li Zhengfan and Chen Wen provide a kind of efficient numerical method " electronic letters, vol, 1999,27 (11): 114-116 " that is used to simulate high-speed interconnect line transient response.It adopts distribution parameter, tries to achieve the analytic solution or the numerical solution of transient response by partial differential equation.Handle in this way single interconnection line still can, but there is certain degree of difficulty in the large-scale tree of handling interconnection line.
The interconnection line model also can adopt lumped parameter.When being tending towards infinite, the exponent number of lumped parameter model can approach distributed parameter model.But this moment, the scale of model must be very huge.Express more complicated (as containing hyperbolic function) when each element of model, the calculating of this high-order model will be very consuming time.In addition, the complexity of calculating is relevant with the bifurcated progression of interconnection line tree again, generally adopts for bifurcated to iterate algorithm, and its computation process more can't be stood.In order to save the operation time of extensive tree construction, people have proposed the method for many model simplifications (model reduction), are similar to original high-order model with the model of low order.Though lower-order model is quick, exists than mistake, error and be not easy to control and a series of problems such as instability.
Formerly in the technology, the interconnection line lumped parameter model of research delay character mainly is along the Elmore time delay, as W.C, Elmore, The Transient Response of Damped Linear Network withParticular Regard to Wideband Amplifiers (about the transient response of broad band amplifier damping Linear Network) " the Journal of Applied Physics that provides, 19 (1): 55-63,1948 ", square coupling (moment matching) is as Ismail, Y.I., the Equivalent Elmore delay for RLCtrees that E.G.Friedman and J.L.Neves. provides (the equivalent Elmore time delay of RLC tree) " IEEE Trans, 2000, CAD 19 (1): 83-97 ", this thinking development, model embarks from the frequency domain transition function mostly.Be transformed into time domain again from frequency domain and carry out speed and the precision that the time delay estimation unavoidably will influence estimation.
Summary of the invention
The objective of the invention is in order to overcome existing problem in the above-mentioned technology formerly, the method that provides a kind of high-order resistance, inductance, electric capacity, electricity of setting up time domain space to lead the interconnection tree-model,
To achieve these goals, the technical solution used in the present invention is: a kind of method of setting up the time domain space mathematical model of tree interconnection circuit, it is characterized in that setting up a kind of resistance, inductance, electric capacity, electricity of comprising and lead the time domain space mathematical model of tree interconnection circuit, the method step of foundation is:
(a) at first, the circuit model of foundation interconnection tree, the π type of setting up interconnect trees according to trunk and the topological structure that divides branch road of actual domain interconnection tree comprises the circuit model that resistance, inductance, electric capacity, electricity are led;
(b) determine the cascade number of trunk and each minute branch road in the circuit model: determine the circuit model trunk set up in the above-mentioned steps (a) and the cascade number of each branch road;
(c) set up time domain space mathematical model: according to kirchhoff (Kirchhoff) voltage law and kirchhoff current law based on above-mentioned (a) (b) result of step set up time domain space mathematical model and be:
x · ( t ) = Ax ( t ) + Bu ( t )
y(t)=Cx(t)+Du(t)
Wherein: A comprises the matrix that resistance R, inductance L, capacitor C, electricity are led G, and B is the matrix that comprises inductance L, and C is 0 and 1 matrix of forming, and D is zero;
X is the vector of 2m dimension, value of each dimension be the electric current I of trunk circuit and each each cascade of bifurcated branch road and tandem node voltage V alternately, wherein m be trunk and each subcircuits the cascade number and;
Each is tieed up time t differentiate for x (t) vector;
U (t) is an input voltage;
Y (t) is an output voltage.
The present invention has many advantages compared with the prior art:
(1) model A matrix of the present invention has only diagonal line three row elements basically, and form is succinct, express in time domain again, thereby the computing in time domain of estimated signal time delay needn't change, and speed is very fast, carries out the emulation of step response at MATLAB, and moment can finish;
(2) the present invention has introduced electricity and has led G in circuit model, makes more closing to reality of model;
(3) matrix size only is directly proportional with 1 power of branch road number, can directly use high-order model for general complicated interconnection line circuit, thereby the result is more accurate;
(4) the present invention compares the result of single interconnect wire, has provided the General Result of complicated interconnection line tree, and more general, practicality is stronger.
Description of drawings
Fig. 1 is the RLCG circuit model of the single interconnect wire of not band signal source and load;
Fig. 2 is the RLCG circuit model of the single interconnect wire in band signal source;
Fig. 3 is the RLCG circuit model of load-carrying single interconnect wire;
Fig. 4 is the RLCG circuit model of 2 grade of 2 bifurcated interconnect trees;
Fig. 5 is the RLCG of bifurcated interconnect trees more than 4 a grades circuit model;
Fig. 6 is the coefficient A matrix structure of state equation of the RLCG circuit model of bifurcated interconnect trees more than 4 grades;
Fig. 7 is the RLCG circuit model of any bifurcated interconnect trees;
Fig. 8 is a chip layout that is used for the embodiment of actual operation;
Fig. 9 is a circuit model of setting up the π type RLCG of embodiment among Fig. 8.
R is that resistance, L are that inductance, C are that electric capacity, G are that electricity is led
Embodiment
Below in conjunction with accompanying drawing, further specify characteristics of the present invention.
Fig. 1 is the RLCG circuit model of the single interconnect wire of not band signal source and load, and circuit is led G by π type resistance R, inductance L, capacitor C and electricity and formed, and R and L are the resistance and the inductance of interconnection line itself, and C and G are that interconnection line electric capacity and electricity over the ground led.Each grade resistance is connected with inductance; Electric capacity is led in parallel with electricity.The crossing node of forming of the end that the junction of the resistance of inductance at the corresponding levels and back level and electric capacity electricity at the corresponding levels are led.The node of entire circuit is respectively node 1, node 2 from left to right ... up to node n-1, node n.
According to the RLCG circuit model of the single interconnect wire of not band signal source that Fig. 1 constituted and load, try to achieve the cascade number of this circuit model.
The Derivation of Mathematical Model of the time domain space of the single interconnect wire of band signal source and load is not as follows:
For each node of Fig. 1 circuit, have according to kirchhoff (Kirchhoff) voltage law and kirchhoff current law:
After the arrangement:
Be expressed as state-space model
x · ( t ) = Ax ( t ) + Bu ( t )
y(t)=Cx(t)+Du(t)
In the formula
x · = dI 1 dt dV 1 dt dI 2 dt dV 2 dt . . . dI n - 1 dt d V n - 1 dt dI n dt dV n dt T , x · ∈ R 2 n
x=[I 1?V 1?I 2?V 2?…?I n-1?V n-1?I n?V n] T,x∈R 2n
y=V out=V n,y∈R
u=V in,u∈R
A, and B, C, D} is respectively
B 2 n × 1 = 1 L 0 0 0 · · · 0 0 0 0 T
C 1×2n=[0?0?0?0?…?0?0?0?1]
D=0,
ABCD} matrix of coefficients feature:
A matrix matrix size is 2n * 2n, and n is the cascade number of circuit model.Upper left to 3 diagonal angle oblique lines of bottom right symmetry except at matrix, all the other elements are 0.A upper right diagonal angle oblique line is by a 12, a 23A (2n-2), (2n-1)And a (2n-1), 2nForm Deng 2n-1 element, their value is respectively With Alternately, promptly a 12 = - 1 L , a 23 = - 1 C , a 34 = - 1 L , a 45 = - 1 C · · · · · · a ( 2 n - 2 ) , ( 2 n - 1 ) = - 1 C With a ( 2 n - 1 ) , 2 n = - 1 L . Middle diagonal angle oblique line is by a 11, a 22A (2n-1), (2n-1)And a 2n, 2nForm Deng 2n element, their value is respectively With
Figure A20061002952300114
Alternately, promptly a 11 = - R L , a 22 = - G C , a 33 = - R L , a 44 = - G C · · · · · · a ( 2 n - 1 ) , ( 2 n - 1 ) = - R L With a 2 n , 2 n = - G C . The diagonal angle oblique line in lower-left is by a 21, a 32A (2n-1), (2n-2)And a 2n, (2n-1)Form Deng 2n-1 element, their value is respectively With
Figure A20061002952300119
Alternately, promptly a 21 = 1 C , a 32 = 1 L , a 43 = 1 C , a 54 = 1 L , · · · · · · a ( 2 n - 2 ) , ( 2 n - 1 ) = 1 L With a 2 n , ( 2 n - 1 ) = 1 C .
B matrix matrix size is 2n * 1, and n is the cascade number of circuit model.Except the 1st behavior
Figure A200610029523001113
Outward, all the other are 0.
C matrix matrix size is 1 * 2n, and n is the cascade number of circuit model.Classify as 1 except last, all the other are 0.
D matrix D=0
Fig. 2 is the RLCG circuit model of the single interconnect wire in band signal source, signal source voltage Vs, signal source internal resistance Rs.
According to the RLCG circuit model of the single interconnect wire in the band signal source that Fig. 2 constituted, try to achieve the cascade number of this circuit model.
The time domain space model of the RLCG circuit model of the single interconnect wire in band signal source except in the A matrix because signal resistance R sWith the resistance R in first cascade be series relationship, a 11 = - R S + R L Outward, all the other are all identical with the time domain space model of the single interconnect wire RLCG circuit model of not band signal source and load.
Fig. 3 is the RLCG circuit model of load-carrying single interconnect wire, has load capacitance C L, pull-up resistor R L
According to the RLCG circuit model of the load-carrying single interconnect wire that Fig. 3 constituted, try to achieve the cascade number of this circuit model.
The time domain space model of load-carrying single interconnect wire except in the A matrix because pull-up resistor R LLeading G with the electricity in last cascade is relation in parallel and load capacitance C LWith the capacitor C in last cascade is relation in parallel, makes a ( 2 n ) , ( 2 n ) = - G + R L - 1 C + C L With a ( 2 n ) , ( 2 n - 1 ) = 1 C + C L Outside, all the time domain space model with the single interconnect wire model of not band signal source and load is identical for all the other.
Fig. 4 is the RLCG circuit model of 2 grade of 2 bifurcated interconnect trees, and 2 grade of 2 bifurcated circuit promptly has the branch road as 2 bifurcateds of the 1st grade behind the 0th grade of trunk circuit.
The trunk circuit model is identical with the single interconnect wire circuit model in band signal source, signal source Vs, and the signal source internal resistance is Rs; The bifurcated circuit model is identical with load-carrying single interconnect wire circuit model, and load capacitance, resistance are respectively C L1, C L2And R L1, R L2。Output terminal is located at a nethermost bifurcated, i.e. the 2nd bifurcated branch road end.
Trunk and bifurcated branch road all are that the π type RLCG circuit by the n cascade constitutes.Each grade of trunk circuit resistance, inductance, electric capacity and electricity are led and are respectively R 0, L 0, C 0And G 0The 1st each grade of bifurcated subcircuits resistance, inductance, electric capacity and electricity are led and are respectively R 1, L 1, C 1And G 1The 2nd each grade of bifurcated subcircuits resistance, inductance, electric capacity and electricity are led and are respectively R 2, L 2, C 2And G 2
Each node name of circuit is as follows.The trunk circuit node is node 1, node 2 ... up to node n-1, node n, the 1st bifurcated branch node is node 11,12 ... up to node 1 (n 1-1), 1n 1, the 2nd bifurcated branch node is node 21,22 ... up to node 2 (n 2-1), 2n 2
According to the RLCG circuit model of 2 grade of 2 bifurcated interconnect trees that Fig. 4 constituted, try to achieve the cascade number of this circuit model.
The Derivation of Mathematical Model of 2 grade of 2 bifurcated circuit time domain space is as follows:
For each node of circuit, have according to kirchhoff (Kirchhoff) voltage law and kirchhoff current law:
Figure A20061002952300131
After the arrangement
Be expressed as state space equation
x · ( t ) = Ax ( t ) + Bu ( t )
y(t)=Cx(t)+Du(t)
In the formula
x · = dI 1 dt dV 1 dt · · · dI n dt dV n dt dI 11 dt dV 11 dt · · · dI 1 n 1 dt dV 1 n 1 dt dI 21 dt dV 21 dt · · · dI 2 n 2 dt dV 2 n 2 dt T , x · ∈ R 2 m .
x = dI 1 dV 1 · · · dI n dV n dI 11 dV 11 · · · dI 1 n 1 dV 1 n 1 dI 21 dV 21 · · · dI 2 n 2 dV 2 n 2 T , x ∈ R 2 m
y = V out = V 2 n 2 , y ∈ R
u=Vs,u∈R
B 2 m × 1 = 1 L 0 0 0 0 · · · 0 0 0 0 T
C 1×2m=[0?0?0?0?…?0?0?0?1]
D=0
M=n+1n in each variable subscript 1+ 2n 2, n, 1n 1, 2n 2Be respectively the cascade number of trunk and two bifurcated subcircuits models.
The state variable feature:
The A matrix
The A matrix size is 2m * 2m, m=n+1n 1+ 2n 2, n, 1n 1, 2n 2Be respectively the cascade number of trunk and two bifurcated subcircuits models.For each branch road (comprising trunk), generally can use the circuit model of identical cascade number, i.e. n=1n 1=2n 2, m=kn is then arranged, k is branch road (comprising a trunk) number, for this 2 grade of 2 bifurcated circuit, k=3, then the A matrix size is 6n * 6n.
Trunk and bifurcated branch road are respectively formed the submatrix of a 2n * 2n.Because trunk circuit initiating terminal has increased signal source Vs, the signal source internal resistance is Rs, so the form of trunk submatrix is with the single interconnect wire model in band signal source; Because two bifurcated branch road ends have increased pull-up resistor R respectively L1And R L2And load capacitance C L1And C L2, therefore the form of two bifurcated branch road submatrixs is with load-carrying single interconnect wire model.The submatrix diagonal angle that above-mentioned trunk and bifurcated branch road are formed rearranges the diagonal angle submatrix.Order is followed successively by trunk submatrix, the 1st bifurcated branch road submatrix and the 2nd bifurcated branch road submatrix.Except the diagonal angle submatrix, also has following non-0 element: have in last column of trunk submatrix and the 1st infall that is listed as of two bifurcated branch road submatrixs With
Figure A20061002952300163
It is element a 2 n , ( 2 n + 1 ) = - 1 C 1 , a 2 n , ( 4 n + 1 ) = - 1 C 2 ; Have at last row of trunk submatrix and the 1st infall of going of two bifurcated branch road submatrixs With It is element a ( 2 n + 1 ) , 2 n = 1 L 1 , a ( 4 n + 1 ) , 2 n = 1 L 2 . All the other elements are 0.
The B matrix
The B matrix size is 2m * 1, m=n+1n 1+ 2n 2, n, 1n 1, 2n 2Be respectively the cascade number of trunk and two bifurcated subcircuits models.Work as n=1n 1=2n 2The time, the B matrix size is 6n * 1.Except the 1st behavior In addition, all the other are 0.
The C matrix
The C matrix size is 1 * 2m, and the m meaning is the same.Work as n=1n 1=2n 2The time, the C matrix size is 1 * 6n.Except last row (i.e. 6n row) are 1, all the other are 0.
The D matrix
D=0。
Fig. 5 is the interconnection line RLCG circuit model of a bifurcated more than 4 grades, loaded impedance Z among the figure LBe pull-up resistor R LWith load capacitance C LIn parallel.The interconnection line circuit model of bifurcated more than 4 grades is special any bifurcated interconnection line circuit model.General any bifurcated interconnection line circuit model can copy this special any bifurcated interconnection line circuit model to obtain.
The trunk of circuit and each bifurcated branch road use the single interconnect wire circuit model of n cascade, and the n of trunk and each bifurcated branch road can be identical, also can be different.Trunk l, after 3 the 1st grade of sub-bifurcateds are arranged, be respectively l 1, l 2And l 3l 1After 2 the 2nd grade of sub-bifurcated: l are arranged 11And l 12l 2After 2 the 2nd grade of sub-bifurcated: l are also arranged 21And l 22l 21After 3 the sub-bifurcated of 3rd level: l are arranged 211, l 212And l 213L 22The back does not have bifurcated again.l 3After do not have bifurcated.Comprise that trunk has 11 branch roads.
With 2 grade of 2 bifurcated circuit, at the initial termination signal source Vs of trunk circuit, the signal source internal resistance is Rs; End at every bifurcated branch road connects loaded impedance respectively.Output terminal is located at below bifurcated branch road, i.e. l 3End.
According to the interconnection line RLCG circuit model of the bifurcated more than 4 grades that Fig. 5 constituted, try to achieve the cascade number of trunk circuit of this circuit model and the cascade number of branch circuit respectively.
Imitative 2 grade of 2 bifurcated circuit asked for the method for the mathematical model of time domain space can be in the hope of the mathematical model of the time domain space of the interconnection line circuit of this bifurcated more than 4 grades, form is consistent with the mathematical model of the time domain space of 2 grade of 2 bifurcated circuit, and difference is the form of A, B, C, four matrix of coefficients of D:
The A matrix constitutes: each composition size of trunk and each bifurcated branch road is the submatrix of 2n * 2n, and n is the cascade number of each trunk circuit or each bifurcated circuit, and the cascade of each submatrix is counted n and can not waited.The submatrix diagonal angle is arranged and is constituted the diagonal angle submatrix, and order is l, l 1, l 11, l 12, l 2, l 21, l 211, l 212, l 213, l 22And l 3
The submatrix of trunk l adopts the A matrix of the single interconnect wire model in band signal source, middle bifurcated branch road l 1, l 2, l 21Submatrix adopt the not A matrix of the single interconnect wire model in band signal source and load, terminal bifurcated branch road l 11, l 12, l 211, l 212, l 213, l 22And l 3Submatrix adopt the A matrix of load-carrying single interconnect wire model.
Last column that each father does increases element with the point of crossing of the 1st row that son is done K is the branch road subscript; First row that each son is done increases element with last row point of crossing that the father does K is the branch road subscript, and its version as shown in Figure 6.
The interconnection line circuit of this bifurcated more than 4 grades comprises the total way n of trunk b=11, it is identical that n is counted in the cascade of getting each trunk and branch road, and the A matrix size is (2n bN) * (2n bN)=and 22n * 22n, the A matrix size is directly proportional with a trunk and a way.
The B matrix size is (2n bN) * 1=22n * 1, B = 1 L 0 0 0 0 · · · 0 0 0 0 T
The C matrix size is 1 * (2n bN)=1 * 22n.C=[0?0?0?0?…?0?0?0?1]
D=0
Fig. 7 is any bifurcated interconnection line RLCG circuit model.
With bifurcated circuit more than 4 grades, at the initial termination signal source Vs of trunk circuit, the signal source internal resistance is Rs; End at every bifurcated branch road connects loaded impedance respectively.Output terminal is located at the end of the bifurcated branch road in below.
According to any bifurcated interconnection line RLCG circuit model that Fig. 7 constituted, try to achieve the cascade number of trunk circuit of this circuit model and the cascade number of branch circuit respectively.
The mathematical model of the time domain space of bifurcated interconnection line RLCG circuit model can be for each node of circuit arbitrarily; obtain according to kirchhoff (Kirchhoff) voltage law and kirchhoff current law; its form is consistent with the mathematical model of the time domain space of the interconnection line circuit of bifurcated more than 4 grades, its matrix constitute can according to the interconnection line circuit of 2 grade of 2 bifurcated circuit and bifurcated more than 4 grades analogize for:
The A matrix constitutes: size be the capable 2m row of 2m, m be trunk and each subcircuits the cascade number with; Each composition size of trunk and each bifurcated branch road is the submatrix of 2n * 2n, and n is the cascade number of each trunk circuit or each bifurcated circuit, and the cascade of each submatrix is counted n and can not waited.The submatrix of trunk circuit adopts the A matrix of the single interconnect wire RLCG model in band signal source, the submatrix of middle bifurcated branch road adopts the not A matrix of the single interconnect wire RLCG model in band signal source and load, and the submatrix of terminal bifurcated branch road adopts the A matrix of load-carrying single interconnect wire RLCG model; The A matrix size is 2m * 2m, the A matrix size is directly proportional with the number of trunk and branch road, each submatrix rearranges the diagonal angle submatrix by diagonal line, the principle that submatrix puts in order is with bifurcated circuit more than 4 grades, promptly press in the circuit diagram from left to right, from top to bottom, about prior to choosing the bifurcated branch road principle of (comprising trunk) up and down.The point of crossing of the 1st row of last column of the dried submatrix of each father and sub dried submatrix increases element C is the electric capacity among the branch road k, and k is the branch road subscript; First row of each sub dried matrix increases element with the point of crossing of last row of the dried matrix of father
Figure A20061002952300192
L is the inductance among the branch road k, and k is the branch road subscript, and other elements all are 0;
The B matrix size is 2m * 1, B = 1 L 0 0 0 0 · · · 0 0 0 0 T , L 0Inductance for each cascade in the trunk circuit;
The C matrix size is 1 * 2m, and C[0 000 ... 000 1];
D=0。
For the A matrix that obtains, B matrix, C matrix can be by making matrix similarity transformation or make depression of order, obtain new matrix form.
Fig. 8 is a chip layout that is used for the embodiment of actual operation, and as shown in Figure 8: dotted line is a grid, and unit is 1 μ m * 1 μ m.
G0 is a signal sending end, and 0-1 is trunk l, after to meet one 2 bifurcated branch: 1-2 be the l of branch 11-3 is the l of branch 2,, l 2After bifurcated: 3-4 is arranged again is the l of branch 21, l 21Terminal G 213-5 is the l of branch 22, l 22Terminal G 22
Fig. 9 is a circuit model of setting up the π type RLCG of embodiment among Fig. 8, and the cascade of trunk and subcircuits model is counted n and got 100.
As shown in Figure 8, the length of trunk and branch is respectively l=3 μ m, l 1=2 μ m, l 2=3 μ m, l 21=1 μ m, l 22=4 μ m.
Signal source internal resistance R S=500 Ω, receiving end load capacitance C L=0.15Pf, pull-up resistor R L=∞.
The electrical parameter of interconnection line unit length is: r 0=0.067 Ω/μ m, l 0=0.70pH/ μ m, c 0=0.062fF/ μ m, g 0=0.Obtain:
R 0=0.00201Ω,L 0=0.021pH,C 0=0.00186fF,G 0=0;
R 1=0.00134Ω,L 1=0.014pH,C 1=0.00124fF,G 1=0;
R 2=0.00201Ω,L 2=0.021pH,C 2=0.00186fF,G 2=0;
R 21=0.00067Ω,L 21=0.007pH,C 21=0.00062fF,G 21=0;
R 22=0.00268Ω,L 22=0.028pH,C 22=0.00248fF,G 22=0。
For each node of circuit, obtain the state-space model of this time domain according to kirchhoff (Kirchhoff) voltage law and kirchhoff current law:
x · ( t ) = Ax ( t ) + Bu ( t )
y(t)=Cx(t)+Du(t)
In the formula
X (t)=[I 0,1V 0,1I 0,2V 0,2I 0,99V 0,99I 0,100V 0,100I 1,1V 1,1I 1,2V 1,2I 1,99V 1,99I 1,100V 1,100I 2,1V 2,1I 2,2V 2,2I 2,99V 2,99I 2,100V 2,100I 21,1V 21,1I 21,2V 21,2I 21,99V 21,99I 21,100V 21,100I 22,1V 22,1I 22,2V 22,2I 22,99V 22,99I 22,100V 22,100] T(I Ij, V IjBe the electric current of trunk and each each node ground capacitance of bifurcated Zhi Ganzhong and the voltage of each node.i=0、1、2、21、22;j=1、2、…99、100)
Figure A20061002952300202
For x (and t) vector to time t differentiate.
u(t)=V S;y(t)=V out
The A matrix size is 1000 * 1000, is made up of following element:
a 11 = - R S - R 0 L 0 = - 2.38 × 10 4 ; a 12 = - 1 L 0 = - 4.76 × 10 13 ; a 13=0;……a 1,1000=0;
a 21 = 1 C 0 = 5.38 × 10 17 ; a 22 = - G 0 C 0 = 0 ; a 23 = - 1 C 0 = - 5.38 × 10 17 ; a 24=0;……a 2,1000=0;
a 31=0; a 32 = 1 L 0 = 4 . 76 × 10 13 ; a 33 = - R 0 L 0 = - 9.57 × 10 10 ; a 34 = - 1 L 0 = - 4.76 × 10 13 ; a 35=0;……a 3,1000=0;
……
a 198,1=0;……a 198,196=0; a 198,197 = 1 C 0 = 5.38 × 10 17 ; a 198,198 = - G 0 C 0 = 0 ; a 198,199 = - 1 C 1 = - 5.38 × 10 17 ; a 198,200=0;……a 198,1000=0
a 199,1=0;……a 199,197=0; a 199,198 = 1 L 0 = 4.76 × 10 13 ; a 199,199 = - R 0 L 0 = - 9.57 × 10 10 ; a 199,200 = - 1 L 0 = - 4.76 × 10 13 ; a 199,201=0;……a 199,1000=0;
a 200,1=0;……a 200,198=0; a 200,199 = 1 C 0 = 5.38 × 10 17 ; a 200,200 = - G 0 C 0 = 0 ; a 200,201 = - 1 C 1 = - 8.06 × 10 17 ; a 200,202=0;……a 200,400=0; a 200,401 = - 1 C 2 = - 5.38 × 10 17 ; a 200,402=0;……a 200,1000=0
a 201,1=0;……a 201,199=0; a 201,200 = 1 L 1 = 7.14 × 10 13 ; a 201,201 = - R 1 L 1 = - 9.57 × 10 10 ; a 201,202 = - 1 L 1 = - 7.14 × 10 13 ; a 201,203=0;……a 201,1000=0;
a 202,1=0;……a 202,200=0; a 202,201 = 1 C 1 = 8.06 × 10 17 ; a 202,202 = - G 1 C 1 = 0 ; a 202,203 = - 1 C 1 = - 8.06 × 10 17 ; a 202,204=0;……a 202,1000=0
a 203,1=0;……a 203,201=0; a 203,202 = 1 L 1 = 7.14 × 10 13 ; a 203,203 = - R 1 L 1 = - 9.57 × 10 10 ; a 203,204 = - 1 L 1 = - 7.14 × 10 13 ; a 203,205=0;……a 203,1000=0;
……
a 398,1=0;……a 398,396=0; a 398,397 = 1 C 1 = 8.06 × 10 17 ; a 398,398 = - G 1 C 1 = 0 ; a 398,399 = - 1 C 1 = - 8.06 × 10 17 ; a 398,400=0;……a 398,1000=0
a 399,1=0;……a 399,397=0; a 399,398 = 1 L 1 = 7.14 × 10 13 ; a 399,399 = - R 1 L 1 - 9.57 × 10 10 ; a 399,400 = - 1 L 1 = - 7.14 × 10 13 ; a 399,401=0;……a 399,1000=0;
a 400,1=0;……a 400,398=0; a 400,399 = 1 C 1 + C L 1 = 6.67 × 10 12 ; a 400,400 = - G 1 - R l 1 - 1 C 1 + C L 1 = 0 ; a 400,401=0;……a 400,1000=0
a 401,1=0;……a 401,199=0; a 401,200 = 1 L 2 = 4.76 × 10 13 ; a 401,201=0;……a 401,400=0; a 401,401 = - R 2 L 2 = - 9.57 × 10 10 ; a 401,402 = - 1 L 2 = - 4.76 × 10 13 ; a 401,403=0;……a 401,1000=0;
a 402,1=0;……a 402,400=0; a 402,401 = 1 C 2 = 5.38 × 10 17 ; a 402,402 = - G 2 C 2 = 0 ; a 402,403 = - 1 C 2 = - 5.38 × 10 17 ; a 402,404=0;……a 402,1000=0
a 403,1=0;……a 403,401=0; a 403,402 = 1 L 2 = 4.76 × 10 13 ; a 403,403 = - R 2 L 2 = - 9.57 × 10 10 ; a 403,404 = - 1 L 2 = - 4.76 × 10 13 ; a 403,405=0;……a 403,1000=0;
……
a 598,1=0;……a 598,596=0; a 598,597 = 1 C 2 = 5.38 × 10 17 ; a 598,598 = - G 2 C 2 = 0 ; a 598,599 = - 1 C 2 = - 5.38 × 10 17 ; a 598,600=0;……a 598,1000=0
a 599,1=0;……a 599,597=0; a 599 , 598 = 1 L 2 = 4.76 × 10 13 ; a 599 , 599 = - R 2 L 2 = - 9.57 × 10 10 ; a 599,500 = - 1 L 2 = - 4.76 × 10 13 ; a 599,501=0;……a 599,1000=0;
a 600,1=0;……a 600,598=0; a 600 , 599 = 1 C 2 = 5.38 × 10 17 ; a 600 , 600 = - G 2 C 2 = 0 ; a 600 , 601 = - 1 C 21 = - 1 . 61 × 10 18 ; a 600,602=0;……a 600,800=0; a 600 , 801 = - 1 C 22 = - 4 . 03 × 10 17 ;
a 600,802=0;……a 600,1000=0
a 601,1=0;……a 601,599=0; a 601,600 = 1 L 21 = 1.42 × 10 14 ; a 601,601 = - R 21 L 21 = - 9.57 × 10 10 ; a 601,602 = - 1 L 21 = - 1.42 × 10 14 ; a 601,603=0;……a 601,1000=0;
a 602,1=0;……a 602,600=0; a 602,601 = 1 C 21 = 1.61 × 10 18 ; a 602,602 = - G 21 C 21 = 0 ; a 602,603 = - 1 C 21 = - 1.61 × 10 18 ; a 602,604=0;……a 602,1000=0
a 603,1=0;……a 603,601=0; a 603,602 = 1 L 21 = 1.42 × 10 14 ; a 603,603 = - R 21 L 21 = - 9.57 × 10 10 ; a 603,604 = - 1 L 21 = - 1.42 × 10 14 ; a 603,605=0;……a 603,1000=0;
……
a 798,1=0;……a 798,796=0; a 798,797 = 1 C 21 = 1.61 × 10 18 ; a 798,798 = - G 21 C 21 = 0 ; a 798,799 = - 1 C 21 = - 1.61 × 10 18 ; a 798,800=0;……a 798,1000=0
a 799,1=0;……a 799,797=0; a 799,798 = 1 L 21 = 1.42 × 10 14 ; a 799,799 = - R 21 L 21 = - 9.57 × 10 10 ; a 799,800 = - 1 L 21 = - 1.42 × 10 14 ; a 799,801=0;……a 799,1000=0;
a 800,1=0;……a 800,798=0; a 800,799 = 1 C 21 + C L 21 = 6.67 × 10 12 ; a 800,800 = - G 21 - R L 21 - 1 C 21 + C L 21 = 0 ; a 800,801=0;……a 800,1000=0
a 801,1=0;……a 801,599=0; a 801,600 = 1 L 22 = 3.57 × 10 13 ; a 801,601=0;……a 801,800=0; a 801,801 = - R 22 L 22 = - 9.57 × 10 10 ; a 801,802 = - 1 L 22 = - 3.57 × 10 13 ; a 801,803=0;……a 801,1000=0;
a 802,1=0;……a 802,800=0; a 802,801 = 1 C 22 = 4.03 × 10 17 ; a 802,802 = - G 22 C 22 = 0 ; a 802,803 = - 1 C 22 = - 4.03 × 10 17 ; a 802,804=0;……a 802,1000=0
a 803,1=0;……a 803,801=0; a 803,802 = 1 L 22 = 3.57 × 10 13 ; a 803,803 = - R 22 L 22 = - 9.57 × 10 10 ; a 803,804 = - 1 L 22 = - 3.57 × 10 13 ; a 803,805=0;……a 803,1000=0;
……
a 998,1=0;……a 998,996=0; a 998,997 = 1 C 22 = 4.03 × 10 17 ; a 998,998 = - G 22 C 22 = 0 ; a 998,999 = - 1 C 22 = - 4.03 × 10 17 ; a 998,1000=0;
a 999,1=0;……a 999,997=0; a 999,998 = 1 L 22 = 3.57 × 10 13 ; a 999,999 = - R 22 L 22 = - 9.57 × 10 10 ;
a 999,1000 = - 1 L 22 = - 3.57 × 10 13 ;
a 1000,1=0;……a 1000,998=0; a 1000,999 = 1 C 22 + C L 22 = 6.67 × 10 12 ;
a 1000,1000 = - G 22 - R L 22 C 22 + C L 22 = 0 .
The B matrix size is 1000 * 1, B = 1 L 0 0 0 0 · · · 0 0 0 0 T , Except the 1st row element b 11 = 1 L 0 = 4.76 × 10 13 Outward, all the other all are 0.
The C matrix size is 1 * 1000, and C=[0 00 ... 00 1], except the 1000th column element C 1000,1Outside=1, all the other all are 0.
The D matrix is 0.

Claims (8)

1. a method of setting up the time domain space mathematical model of tree interconnection circuit is characterized in that setting up a kind of resistance, inductance, electric capacity, electricity of comprising and leads the time domain space mathematical model of tree interconnection circuit, and the method step of foundation is:
(a) at first, set up the circuit model of interconnection tree, according to the trunk of actual domain interconnection tree with divide branch road
The π type that topological structure is set up interconnect trees comprises the circuit model that resistance, inductance, electric capacity, electricity are led;
(b) determine the cascade number of trunk and each minute branch road in the circuit model: determine the circuit model trunk set up in the above-mentioned steps (a) and the cascade number of each branch road;
(c) set up time domain space mathematical model: according to kirchhoff (Kirchhoff) voltage law and kirchhoff current law based on above-mentioned (a) (b) result of step set up time domain space mathematical model and be:
x · ( t ) = Ax ( t ) + Bu ( t )
y(t)=Cx(t)+Du(t)
Wherein: A comprises the matrix that resistance R, inductance L, capacitor C, electricity are led G, and B is the matrix that comprises inductance L, and C is 0 and 1 matrix of forming, and D is zero;
X (t) is the vector of 2m dimension, value of each dimension be the electric current I of trunk circuit and each each cascade of bifurcated branch road and tandem node voltage V alternately, wherein m be trunk and each subcircuits the cascade number and;
Figure A2006100295230002C2
Each is tieed up time t differentiate for x (t) vector;
U (t) is an input voltage;
Y (t) is an output voltage.
2. a kind of method of setting up the time domain space mathematical model of tree interconnection circuit as claimed in claim 1, it is characterized in that: described A matrix is at the circuit model of setting up during for the RLCG circuit model of the single interconnect wire of band signal source and load not, matrix size is the capable 2n row of 2n, n is the cascade number of circuit model, upper left to 3 diagonal angle oblique lines of bottom right symmetry except at matrix, all the other elements are 0; A upper right diagonal angle oblique line is by a 12, a 23A (2n-2), (2n-1)And a (2n-1), 2n2n-1 element form, their value is respectively With
Figure A2006100295230002C4
Alternately, promptly a 12 = - 1 L , a 23 = - 1 C , a 34 = - 1 L , a 45 = - 1 C · · · · · · a ( 2 n - 2 ) , ( 2 n - 1 ) = - 1 C With a ( 2 n - 1 ) , 2 n = - 1 L ; Middle diagonal angle oblique line is by a 11, a 22A (2n-1), (2n-1)And a 2n, 2n2n element form, their value is respectively With
Figure A2006100295230003C2
Alternately, promptly a 11 = - R L , a 22 = - G C , a 33 = - R L , a 44 = - G C · · · · · · a ( 2 n - 1 ) , ( 2 n - 1 ) = - R L With a 2 n , 2 n = - G C ; The diagonal angle oblique line in lower-left is by a 21, a 32A (2n-1), (2n-2)And a 2n, (2n-1)2n-1 element form, their value is respectively With
Figure A2006100295230003C7
Alternately, promptly a 21 = 1 C , a 32 = 1 L , a 43 = 1 C , a 54 = 1 L , · · · · · · a ( 2 n - 2 ) , ( 2 n - 1 ) = 1 L With a 2 n , ( 2 n - 1 ) = 1 C .
3. a kind of method of setting up the time domain space mathematical model of tree interconnection circuit as claimed in claim 1, it is characterized in that: described A matrix, when the circuit model of setting up is the RLCG circuit model of single interconnect wire in band signal source, matrix size is the capable 2n row of 2n, n is the cascade number of circuit model, upper left to 3 diagonal angle oblique lines of bottom right symmetry except at matrix, all the other elements are 0; A upper right diagonal angle oblique line is by a 12, a 23A (2n-2), (2n-1)And a (2n-1), 2n2n-1 element form, their value is respectively
Figure A2006100295230003C11
With
Figure A2006100295230003C12
Alternately, promptly a 12 = - 1 L , a 23 = - 1 C , a 34 = - 1 L , a 45 = - 1 C · · · · · · a ( 2 n - 2 ) , ( 2 n - 1 ) = - 1 C With a ( 2 n - 1 ) , 2 n = - 1 L ; Middle diagonal angle oblique line is by a 11, a 22A (2n-1), (2n-1)And a 2n, 2n2n element form, their value is respectively
Figure A2006100295230003C15
With
Figure A2006100295230003C16
Alternately, promptly a 11 = - Rs + R L , a 22 = - G C , a 33 = - R L , a 44 = - G C · · · · · · a ( 2 n - 1 ) , ( 2 n - 1 ) = - R L With a 2 n , 2 n = - G C ; The diagonal angle oblique line in lower-left is by a 21, a 32A (2n-1), (2n-2)And a 2n, (2n-1)2n-1 element form, their value is respectively With
Figure A2006100295230003C21
Alternately, promptly a 21 = 1 C , a 32 = 1 L , a 43 = 1 C , a 54 = 1 L , · · · · · · a ( 2 n - 2 ) , ( 2 n - 1 ) = 1 L With a 2 n , ( 2 n - 1 ) = 1 C .
4. a kind of method of setting up the time domain space mathematical model of tree interconnection circuit as claimed in claim 1, it is characterized in that: described A matrix, when the circuit model of setting up is the RLCG circuit model of load-carrying single interconnect wire, matrix size is the capable 2n row of 2n, n is the cascade number of circuit model, upper left to 3 diagonal angle oblique lines of bottom right symmetry except at matrix, all the other elements are 0; A upper right diagonal angle oblique line is by a 12, a 23A (2n-2), (2n-1)And a (2n-1), 2n2n-1 element form, their value is respectively With
Figure A2006100295230003C26
Alternately, promptly a 12 = - 1 L , a 23 = - 1 C , a 34 = - 1 L , a 45 = - 1 C · · · · · · a ( 2 n - 2 ) , ( 2 n - 1 ) = - 1 C With a ( 2 n - 1 ) , 2 n = - 1 L ; Middle diagonal angle oblique line is by a 11, a 22A (2n-1), (2n-1)And a 2n, 2n2n element form, their value is respectively
Figure A2006100295230004C1
With
Figure A2006100295230004C2
Alternately, promptly a 11 = - R L , a 22 = - G C , a 33 = - R L , a 44 = - G C · · · · · · a ( 2 n - 1 ) , ( 2 n - 1 ) = - R L With a 2 n , 2 n = - G + R L - 1 C + C L ; The diagonal angle oblique line in lower-left is by a 21, a 32A (2n-1), (2n-2)And a 2n, (2n-1)2n-1 element form, their value is respectively
Figure A2006100295230004C6
With Alternately, promptly a 21 = 1 C , a 32 = 1 L , a 43 = 1 C , a 54 = 1 L , · · · · · · a ( 2 n - 2 ) , ( 2 n - 1 ) = 1 L With a 2 n , ( 2 n - 1 ) = 1 C + C L .
5. a kind of method of setting up the time domain space mathematical model of tree interconnection circuit as claimed in claim 1, it is characterized in that: when described A matrix is the RLCG circuit model of multistage many bifurcateds interconnection line arbitrarily at circuit model, size is the capable 2m row of 2m, m be trunk and each subcircuits the cascade number and, the submatrix that the main body of principal matrix is produced by trunk submatrix and each bifurcated branch road is arranged on diagonal line and is constituted the diagonal angle submatrix; The A matrix form of the RLCG circuit model gained of the solid wire interconnection line that wherein said trunk submatrix is the band signal source; Described bifurcated branch road submatrix, at branch road is the A matrix form of RLCG circuit model gained of the single interconnect wire of not band signal source and load during for middle branch, is the A matrix form of the RLCG circuit model gained of load-carrying single interconnect wire at branch road during for end branch; The 1st row point of crossing of last column of the dried submatrix of each father and sub dried submatrix increases element C is the electric capacity among the branch road k, and k is the branch road subscript; First row of each sub dried submatrix increases element with last row point of crossing of the dried submatrix of father L is that the electricity among the branch road k is led, and k is the branch road subscript; Other elements all are 0.
6. a kind of method of setting up the time domain space mathematical model of tree interconnection circuit as claimed in claim 1 is characterized in that: described B matrix size is capable 1 row of 2m, except the 1st row equals
Figure A2006100295230004C13
Other element is 0, wherein m be trunk and each subcircuits the cascade number and, L 0Be each the cascade inductance in the trunk circuit.
7. a kind of method of setting up the time domain space mathematical model of tree interconnection circuit as claimed in claim 1, it is characterized in that: described C matrix size is 1 row 2m row, except last row equal 1, other element is 0, wherein m be trunk and each subcircuits the cascade number and.
8. a kind of method of setting up the time domain space mathematical model of tree interconnection circuit as claimed in claim 1 is characterized in that: described D matrix size is 1 row, 1 row, D=0.
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Publication number Priority date Publication date Assignee Title
CN102915385A (en) * 2011-08-03 2013-02-06 复旦大学 Interconnection line model reduction method based on time-domain trapezoidal method difference
CN103226166A (en) * 2013-03-21 2013-07-31 天津大学 Shielded twisted pair RLCG model and computational method of transfer characteristic thereof
CN106569978A (en) * 2016-11-09 2017-04-19 深圳国泰安教育技术股份有限公司 Method for calculating current flowing through electrical appliance in circuit

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US6567960B2 (en) * 2001-10-09 2003-05-20 Hewlett-Packard Development L.P. System for improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance values
CN1555091A (en) * 2003-12-27 2004-12-15 复旦大学 Tree interlinking circuit analogue method based on transmission line model
CN100517339C (en) * 2005-01-18 2009-07-22 王胜国 Transfer function recurrence methods of RLC interconnect and transmission line model and model predigestion

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102915385A (en) * 2011-08-03 2013-02-06 复旦大学 Interconnection line model reduction method based on time-domain trapezoidal method difference
CN103226166A (en) * 2013-03-21 2013-07-31 天津大学 Shielded twisted pair RLCG model and computational method of transfer characteristic thereof
CN103226166B (en) * 2013-03-21 2015-05-27 天津大学 Computational method of transfer characteristic of shielded twisted pair RLCG
CN106569978A (en) * 2016-11-09 2017-04-19 深圳国泰安教育技术股份有限公司 Method for calculating current flowing through electrical appliance in circuit

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