CN1964464A - A device to process inserting frame and processing method - Google Patents
A device to process inserting frame and processing method Download PDFInfo
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Abstract
The related interpolation frame processing method with connected devices comprises: the sequential control information generator generates three pieces of sequence control information according to input information; the mapping table buffer device labels the area past by next/last motion vector as the visible/barrier area according to the input motion vector; the interpolation frame buffer device processes the video information into candidate data according to former labeled information; and the interpolation frame calculator calculates the result data.
Description
Technical field
The present invention relates to a kind of interleave processing unit and processing method, especially a kind of processing unit and the processing method that can carry out interleave at any time.
Background technology
For discontinuous motion picture is done smoothing processing, need do interleave and handle.In interleave is handled,, solve the motion occlusion issue in order effectively to remove owing to blocking the motion noise information that forms.
H.264, the multi-mode motion estimation algorithm that existing MPEG-4 AVC/ITU-T is adopted in the video encoding standard, though increased code efficiency and performance, but but give exercise estimator such as the mode decision equal pressure, particularly the hardware exercise estimator brings very large computational complexity.
And can adopt mode decision algorithm and the spatial-temporal prediction of obtaining optimal mode by the method for adjacent block motion vector relatively to obtain initial search point, and the fast motion estimation algorithm that carries out local full search, though these two kinds of algorithms have reduced computational complexity, accelerated the process of coding, reduce simultaneously hard-wired difficulty to a certain extent again, but can't consider the processing of blocked area.
Existing interleave processing unit is taken all factors into consideration the precision of hardware cost and estimation, designs the accurate full search method device of a kind of layering.On the basis of serial input, further adopt the mode of parallel processing structure and pipeline processes, and combine the thought of hierarchical search with the hardware configuration of 100% efficient parallel processing.Employed hardware resource is 1/4th of a full search method, has reduced system clock.Data storage device when being a kind of parallel processing though saved on-chip memory, can't be implemented in the pointwise interleave of any time.
In sum, above-mentioned interleave processing unit and processing method though all adopt the mode of video flowing, are not to consider that blocked area and the motion vector that appears the district come pointwise to generate the interleave data simultaneously at any time.
Summary of the invention
The objective of the invention is deficiency at existing interleave processing unit and processing method, a kind of interleave processing unit and processing method are provided, can realize the interleave of any time, and come pointwise to generate the interleave data by blocked area and the motion vector that appears the district at any time simultaneously.
For achieving the above object, the invention provides a kind of interleave processing unit, comprising:
One sequential control information maker is used for mating according to the sequential between the data time sequence information reconciliation data flow;
One mapping table buffer is connected with described sequencing control information maker, is used for according to motion vector mark blocked area and appears the district;
One interleave buffer is connected with the mapping table buffer with described sequencing control information maker, is used for according to the blocked area and appears district's label information video data is processed into the interleave candidate data;
One interleave arithmetic unit is connected with the interleave buffer with described sequencing control information maker, is used for going out interleave result data and corresponding interleave credible result degree according to interleave candidate data information calculations.
Described interleave buffer comprises:
One interleave strategic control module links with described sequencing control information maker, is used for obtaining the interleave parameter constantly according to interleave;
One reference address computing module is connected the reference address that is used to calculate the blocked area He appears the district with described interleave strategic control module;
One motion vector tag address computing module is connected with described interleave strategic control module, is used for the calculating kinematical vector tag address;
One address validity control module is connected with described mapping table buffer, interleave strategic control module and motion vector tag address computing module, is used for calculated address validity mark;
One buffer address calculation module is connected with described reference address computing module, motion vector tag address computing module and address validity control module, is used to calculate the buffer address;
One address decoding module is connected with described buffer address calculation module, is used for the calculated address sign indicating number;
One interleave data conversion module is connected with described interleave strategic control module, is used to calculate the interleave data in next moment and the interleave data of previous moment;
One interleave cache module is connected with described interleave arithmetic unit, address decoding module and interleave data conversion module, is used to calculate the interleave candidate data.
The present invention also provides a kind of interleave processing method, may further comprise the steps:
Described step 3 is specially:
Step 31, interleave strategic control module obtain the interleave parameter constantly according to the interleave of input, i.e. the fixed phase used of interleave, and in input reference address computing module, motion vector tag address computing module and the address validity control module;
Step 32, described reference address computing module obtain the blocked area according to described interleave parameter and appear the reference address in district, and in the input buffer address calculation module;
Step 33, described motion vector tag address computing module obtain the motion vector tag address according to the motion vector and the described interleave parameter of input, and import in described address validity control module and the buffer address calculation module;
Step 34, described address validity control module obtain address validity mark according to motion vector, mapping table state, described interleave parameter and the described motion vector tag address of input, and transmission and described buffer address calculation module;
Step 35, described buffer address calculation module calculate the buffer address information according to described reference address, motion vector tag address and address validity mark, and transmission and address decoding module;
Step 36, described address decoding module obtain address code by the buffer address information, and transmission and interleave cache module;
Step 37, interleave data conversion module obtain the interleave data in next moment and the interleave data of previous moment according to the video data in interleave next moment constantly and the video data and the interleave parameter of previous moment, and transmission and interleave cache module;
Step 38, described interleave cache module obtain the interleave candidate data with address code, the video data in next moment and the interleave Refresh Data of previous moment.
Described step 38 is specially:
Step 381, described interleave cache module judge the interleave position whether have simultaneously constantly next of interleave constantly video data and the video data of previous moment, if having simultaneously then take out interleave next video data constantly constantly, execution in step 382; If have only one of them interleave data constantly, then take out the video data in this moment, execution in step 382;
Step 382, the video data of above-mentioned taking-up and the video data that had before write that has had in this position are compared, if the video data of above-mentioned taking-up is interleave next video data constantly constantly, and the video data that had before write is the interleave video data of previous moment constantly, then next video data constantly of the interleave moment is substituted the video data of the interleave moment previous moment that has had; If the video data of above-mentioned taking-up is the interleave video data of previous moment constantly, and the video data for next moment in the interleave moment that has had does not then substitute; If be the video data of synchronization, video data and the existing video data that relatively takes out then, the video data reservation that weight is big.
Described step 4 is specially the interleave arithmetic unit and goes out the interleave result data according to interleave candidate data weighted average calculation.
In the described step 4, the interleave arithmetic unit also will calculate interleave credible result degree according to the interleave candidate data.
The method of described calculating interleave credible result degree is, whether described interleave arithmetic unit judges described candidate data greater than a default value, and if greater than would be judged as credible, if less than would be judged as insincere.
Therefore, the present invention has the following advantages:
1, the interleave processing unit adopts pipelined cache device structure, has realized the sliding window of variable length, thereby has realized the interleave of any time.
2, the interleave processing method reaches the effect of video flowing with the blocked area with appear district's parallel processing.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 is the structural representation of interleave processing unit of the present invention.
Fig. 2 is the structural representation of the interleave buffer of interleave processing unit of the present invention.
Fig. 3 is the flow chart of interleave processing method of the present invention.
Fig. 4 is the flow chart of the processing candidate data of interleave processing method of the present invention.
Fig. 5 is the schematic diagram of interleave processing method of the present invention.
Fig. 6 is the flow chart that interleave processing method of the present invention is calculated the interleave candidate data.
Embodiment
Interleave processing unit of the present invention is the hardware unit that a kind of ASIC of being used for realizes.This device can be realized the interleave of any time, and can solve the motion occlusion issue, and algorithm reaches half-pixel accuracy, is widely used in the motion process of the film mode and the television mode of video flowing, can improve frame per second simultaneously to reach better video effect.
As shown in Figure 1, structural representation for interleave processing unit of the present invention, comprise: sequencing control information maker 4 is connected with mapping table buffer 3 with interleave arithmetic unit 2 with the interleave buffer 1, interleave arithmetic unit 2 and the mapping table buffer 3 that are connected with sequencing control information maker 4, interleave buffer 1.
Each module effect is as follows:
Interleave arithmetic unit 2 is used for going out interleave result data and corresponding interleave credible result degree according to interleave candidate data information calculations;
Sequencing control information maker 4 is used for mating according to the sequential between the data time sequence information reconciliation data flow.
As shown in Figure 2, be the structural representation of interleave buffer; Comprise and sequencing control information maker 4 joining interleave strategic control modules 10, reference address computing module 11, be connected with interleave strategic control module 10; Motion vector tag address computing module 12 is connected with interleave strategic control module 10; Address validity control module 13 is connected with mapping table buffer 3, interleave strategic control module 10 and motion vector tag address computing module 12; Buffer address calculation module 14 is connected with reference address computing module 10, motion vector tag address computing module 12 and address validity control module 13; Address decoding module 15 is connected with buffer address calculation module 14; Interleave data conversion module 16 is connected with interleave strategic control module 10; Interleave cache module 17 is connected with interleave arithmetic unit 2, address decoding module 15 and interleave data conversion module 16.
Each module effect:
Interleave strategic control module 10 is used for obtaining the interleave parameter constantly according to interleave;
Reference address computing module 11, the reference address that is used to calculate the blocked area He appears the district;
The motion vector tag address is calculated 12 of moulds, is used for the calculating kinematical vector tag address;
Address validity control module 13 is used for calculated address validity mark;
Buffer address calculation module 14 is used to calculate the buffer address;
Address decoding module 15 is used for the calculated address sign indicating number;
Interleave data conversion module 16 is used to calculate the interleave data in next moment and the interleave data of previous moment;
Interleave cache module 17 is used to calculate the interleave candidate data.
As shown in Figure 3, be the flow chart of interleave processing method of the present invention, the step of this method is as follows:
Suppose that this device initial moment of operation is 0, then the initial moment of operation of mapping table buffer and interleave buffer is 0; According to the hunting zone of motion vector of input, and the length of interleave time information and row, calculate the finish time of mapping table according to formula 1;
Length+max(abs(round(-m)*(1-phase)))，abs(round(-m)*(1-phasetb))))(1)
Calculate the finish time of input buffer according to formula 2;
Length+2*max(abs(round(-m)*(1-phase)))，abs(round(-m)*(1-phasetb))))+max(abs(round(-n)*phase))，abs(round((-n)*phasetb)))(2)
Calculate the initial moment of interleave arithmetic unit according to formula 3;
max(abs(round(-m)*(1-phase)))，abs(round(-m)*(1-phasetb))))+max(abs(round(-n)*phase))，abs(round((-n)*phasetb)))+1(3)
Calculate the finish time according to formula 4;
Length+max(abs(round(-m)*(1-phase)))，abs(round(-m)*(1-phasetb))))+max(abs(round(-n)*phase))，abs(round((-n)*phasetb)))+1(4)
Wherein, the Length in the formula 1,2,3 and 4 is the length of row, and max is for getting macrooperation, round is complementation, and abs is the computing that takes absolute value, and phase is the interleave moment, phasetb be the interleave derived of phase with reference to constantly, the hunting zone of motion vector is [m, n].
If candidate data is arranged, then candidate data is done weighted average, obtain the interleave result data, and mark interleave credible result degree is 1; If there is not candidate data, then mark interleave credible result degree is 0; Whether the interleave arithmetic unit judges described candidate data greater than a default value, and if greater than would be judged as credible, if less than would be judged as insincere.
Because the tag address parametrization can realize that variable length slides, so realized carrying out at any time interleave; Simultaneously, because can appear district and blocked area by while mark on buffer, guaranteed that this device can move in the mode of streamline, reaches the effect of video flowing.
As shown in Figure 4, be the method flow diagram of step 103 of the present invention, and referring to shown in Figure 5, among the figure,
Mv: motion vector;
Vd: video data;
Futr: next constantly;
Prev: previous moment;
Interp: interleave;
Top: lastrow
Mid: middle row
Bot: next line
ABS: take absolute value
Round: round
Max: get maximum
Hunting zone in previous moment delegation: [m, n]
Appear district's (by the mark of next motion vector constantly) scope at the interleave place: [Round (m* (1-phase)), Round (n* (1-phase)]
Blocked area (by the motion vector of previous moment mark) scope at the interleave place: [Round (n*phase), Round (m*phase)]
12 kinds of situations in the moment of interleave (phase):
1/3，1/2，2/3，1/4，3/4，1/5，2/5，3/5，4/5，1/6，5/6?and?0
Illustrated is that interleave is 1/2 o'clock situation (the demand maximum of buffer resource at this moment) constantly;
Illustrated is in certain interleave situation during phase constantly;
Mapping table buffer size: m+n+2=60
Interleave buffer size: m+n+2+ (n+1)/2=75;
Step 231, interleave strategic control module obtain the interleave parameter constantly according to the interleave of input, i.e. the fixed phase used of interleave, and in input reference address computing module, motion vector tag address computing module and the address validity control module;
The interleave of input is phase constantly, and the video data type of input is that (=1, expression is video to is_video;=0, expression is film), then, obtain interleave parameter p hasetb according to interleave strategy (condition selection logic), (if phase=1/2, phasetb=0; Under the video pattern, if phase＜1/2, if pahsetb=2*phasetb is phase＞1/2, then phasetb=2*phase-1; Phasetb is phase under the film pattern;
Step 232, described reference address computing module obtain the blocked area according to described interleave parameter and appear the reference address in district, and in the input buffer address calculation module;
If the starting point of mark interleave buffer is 0, the reference address that then appears the district is calculated by formula 5, and the reference address of blocked area is calculated by formula 6:
max(round(n*(1-phase))，round(n*(1-phase))) (5)
max(round(n*(1-phase))，round(n*(1-phase)))+m+1 (6)
Step 233, described motion vector tag address computing module obtain the motion vector tag address according to the motion vector and the described interleave parameter of input, and import in described address validity control module and the buffer address calculation module;
Write down the motion vector mv_futr in a moment, the motion vector mv_prev of previous moment, these two motion vectors have directivity, be symbolic number, the motion vector tag address that appears the district is: mv_futr* (1-phasetb), and the motion vector tag address of blocked area is: mv_prev* (1-phasetb), according to the motion vector tag address that appears the district, marking on the mapping table buffer promptly puts 1;
Step 234, described address validity control module obtain address validity mark according to motion vector, mapping table state, described interleave parameter and the described motion vector tag address of input, and transmission and described buffer address calculation module;
According to the flag bit of the corresponding row of being exported by mapping table, if the mark mistake, then the motion vector tag address of Dui Ying blocked area is invalid, if unmarked mistake, then the address is effective;
Step 235, described buffer address calculation module calculate the buffer address information according to described reference address, motion vector tag address and address validity mark, and transmission and address decoding module;
If the address is effective, then appears the tag address of district on buffer and be: the reference address+mv_futr* (1-phasetb) that appears the district; The tag address of blocked area on buffer is: the reference address+mv_prev* of blocked area (1-phasetb); If the address is invalid, corresponding address mark is a particular value, as ff;
Step 236, described address decoding module obtain address code by the buffer address information, and transmission and interleave cache module;
The triplex row motion vector in next moment of corresponding input and the triplex row motion vector of previous moment, appear district tag address and three blocked area tag address to three and decipher, i.e. the bit position 1 of this address correspondence, all the other are 0, if particular value, then all bits are 0;
Step 237, interleave data conversion module obtain the interleave data in next moment and the interleave data of previous moment according to the video data in interleave next moment constantly and the video data and the interleave parameter of previous moment, and transmission and interleave cache module;
With this video data constantly, and interleave parameter (weight, interleave is with reference to information such as the moment) is combined into the data structure in the buffer accordingly, obtains being substituted into the interleave data in the buffer;
Step 238, described interleave cache module obtain the interleave candidate data with address code, the video data in next moment and the interleave Refresh Data of previous moment.
Herein, the method for calculating the interleave candidate data is many, and as shown in Figure 6, wherein concrete a kind of is:
Step 381, described interleave cache module judge whether the interleave position has the video data in interleave next moment constantly and the video data of previous moment simultaneously, if having simultaneously then execution in step 382; If have only one of them constantly the interleave data execution in step 383;
Step 382, taking-up interleave be next video data constantly constantly, execution in step 384;
Step 383, take out the video data in this moment, execution in step 384;
Step 384, with the video data of above-mentioned taking-up with compare with the video data that had before write in this position through having, if the video data of above-mentioned taking-up is interleave next video data constantly constantly, and the video data that had before write is the interleave video data of previous moment constantly, and then execution in step 385; If the video data of above-mentioned taking-up is the interleave video data of previous moment constantly, and the video data for next moment in the interleave moment that has had, then execution in step 386; If be the video data of synchronization, then execution in step 387;
Step 385, then with interleave constantly next video data constantly substitute the interleave that the had video data of previous moment constantly;
Step 386, then do not substitute;
Step 387, the video data and the existing video data that relatively take out, the video data that weight is big keeps.
In sum, because the tag address parametrization can realize that variable length slides, so realized carrying out at any time interleave; Simultaneously, because can appear district and blocked area by while mark on buffer, guaranteed that this device can move in the mode of streamline, reaches the effect of video flowing.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit and scope of technical solution of the present invention.
Claims (8)
1, a kind of interleave processing unit, comprising:
One sequential control information maker is used for mating according to the sequential between the data time sequence information reconciliation data flow;
One mapping table buffer is connected with described sequencing control information maker, is used for according to motion vector mark blocked area and appears the district;
One interleave buffer is connected with the mapping table buffer with described sequencing control information maker, is used for according to the blocked area and appears district's label information video data is processed into the interleave candidate data;
One interleave arithmetic unit is connected with the interleave buffer with described sequencing control information maker, is used for going out interleave result data and corresponding interleave credible result degree according to interleave candidate data information calculations.
2, interleave processing unit according to claim 1, wherein said interleave buffer comprises:
One interleave strategic control module links with described sequencing control information maker, is used for obtaining the interleave parameter constantly according to interleave;
One reference address computing module is connected the reference address that is used to calculate the blocked area He appears the district with described interleave strategic control module;
One motion vector tag address computing module is connected with described interleave strategic control module, is used for the calculating kinematical vector tag address;
One address validity control module is connected with described mapping table buffer, interleave strategic control module and motion vector tag address computing module, is used for calculated address validity mark;
One buffer address calculation module is connected with described reference address computing module, motion vector tag address computing module and address validity control module, is used to calculate the buffer address;
One address decoding module is connected with described buffer address calculation module, is used for the calculated address sign indicating number;
One interleave data conversion module is connected with described interleave strategic control module, is used to calculate the interleave data in next moment and the interleave data of previous moment;
One interleave cache module is connected with described interleave arithmetic unit, address decoding module and interleave data conversion module, is used to calculate the interleave candidate data.
3, a kind of according to the described interleave processing method of above-mentioned arbitrary claim, comprising the following step poly-
Step 1, sequencing control information maker generate the first sequencing control information according to the time sequence information of importing, and input mapping table buffer generates the second sequencing control information, and input interleave buffer generates the 3rd sequencing control information, in the input interleave arithmetic unit;
Step 2, described mapping table buffer are according to the motion vector of importing, the zone marker that constantly next of interleave motion vector is constantly passed is for appearing the district, zone that the motion vector of interleave previous moment is constantly passed and the zone marker that is not passed by next motion vector constantly are the blocked area, and blocked area and the label information that appears the district are sent and the interleave buffer;
Step 3, described interleave buffer are processed into the interleave candidate data according to blocked area and the label information that appears the district with video data, and transmission and interleave arithmetic unit;
Step 4, described interleave arithmetic unit calculate the interleave result data according to the interleave candidate data.
4, interleave processing method according to claim 3, wherein said step 3 is specially:
Step 31, interleave strategic control module obtain the interleave parameter constantly according to the interleave of input, i.e. the fixed phase used of interleave, and in input reference address computing module, motion vector tag address computing module and the address validity control module;
Step 32, described reference address computing module obtain the blocked area according to described interleave parameter and appear the reference address in district, and in the input buffer address calculation module;
Step 33, described motion vector tag address computing module obtain the motion vector tag address according to the motion vector and the described interleave parameter of input, and import in described address validity control module and the buffer address calculation module;
Step 34, described address validity control module obtain address validity mark according to motion vector, mapping table state, described interleave parameter and the described motion vector tag address of input, and transmission and described buffer address calculation module;
Step 35, described buffer address calculation module calculate the buffer address information according to described reference address, motion vector tag address and address validity mark, and transmission and address decoding module;
Step 36, described address decoding module obtain address code by the buffer address information, and transmission and interleave cache module;
Step 37, interleave data conversion module obtain the interleave data in next moment and the interleave data of previous moment according to the video data in interleave next moment constantly and the video data and the interleave parameter of previous moment, and transmission and interleave cache module;
Step 38, described interleave cache module obtain the interleave candidate data with address code, the video data in next moment and the interleave Refresh Data of previous moment.
5, interleave processing method according to claim 4, wherein said step 38 is specially:
Step 381, described interleave cache module judge the interleave position whether have simultaneously constantly next of interleave constantly video data and the video data of previous moment, if having simultaneously then take out interleave next video data constantly constantly, execution in step 382; If have only one of them interleave data constantly, then take out the video data in this moment, execution in step 382;
Step 382, the video data of above-mentioned taking-up and the video data that had before write that has had in this position are compared, if the video data of above-mentioned taking-up is interleave next video data constantly constantly, and the video data that had before write is the interleave video data of previous moment constantly, then next video data constantly of the interleave moment is substituted the video data of the interleave moment previous moment that has had; If the video data of above-mentioned taking-up is the interleave video data of previous moment constantly, and the video data for next moment in the interleave moment that has had does not then substitute; If be the video data of synchronization, video data and the existing video data that relatively takes out then, the video data reservation that weight is big.
6, according to claim 3,4 or 5 described interleave processing methods, wherein said step 4 is specially the interleave arithmetic unit and goes out the interleave result data according to interleave candidate data weighted average calculation.
7, according to claim 3,4 or 5 described interleave processing methods, in the wherein said step 4, the interleave arithmetic unit also will calculate interleave credible result degree according to the interleave candidate data.
8, interleave processing method according to claim 7, wherein said calculating interleave credible result degree is specially: described interleave arithmetic unit judges that whether described candidate data is greater than a default value, if greater than would be judged as credible, if less than would be judged as insincere.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101656825B (en) * | 2008-08-19 | 2012-03-28 | 美国博通公司 | Method and system for processing signals |
| CN112770015A (en) * | 2020-12-29 | 2021-05-07 | 紫光展锐(重庆)科技有限公司 | Data processing method and related device |
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| US4663665A (en) * | 1985-01-07 | 1987-05-05 | Nippon Hoso Kyokai | TV system conversion apparatus |
| JP2578859B2 (en) * | 1987-12-25 | 1997-02-05 | 日本電気株式会社 | Television signal format converter |
| GB9214218D0 (en) * | 1992-07-03 | 1992-08-12 | Snell & Wilcox Ltd | Motion compensated video processing |
| JP3224514B2 (en) * | 1996-08-21 | 2001-10-29 | シャープ株式会社 | Video encoding device and video decoding device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101656825B (en) * | 2008-08-19 | 2012-03-28 | 美国博通公司 | Method and system for processing signals |
| CN112770015A (en) * | 2020-12-29 | 2021-05-07 | 紫光展锐(重庆)科技有限公司 | Data processing method and related device |
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