CN1964304A - Readable and writable serial interface bus communication controller with SPI interface - Google Patents
Readable and writable serial interface bus communication controller with SPI interface Download PDFInfo
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Abstract
The invention discloses a readable and writable serial interface bus communication controller with an SPI interface. The device comprises a communication component, a data buffer processing unit 1, an interface controller, an SPI interface and an EEPROM; the communication assembly comprises a bus part and a communication logic control part; the bus part comprises a bus end serial asynchronous receiving and transmitting unit and a data buffer processing unit 2 connected with the bus end serial asynchronous receiving and transmitting unit; the communication logic control part comprises a communication control unit, an error counting and processing circuit and a carrier sense multiple access collision monitoring circuit. The invention simplifies the control logic of the equipment CPU by utilizing the characteristics of simple protocol and high speed of the SPI interface while realizing serial bus communication, provides greater convenience for equipment users and manufacturers, and can reduce the resource occupation of the equipment CPU. The user can conveniently modify the working state of the chip communication controller by sending an instruction. Has better universality.
Description
Technical field
The present invention relates to the control device that a kind of Control Network is used, the control device that particularly a kind of Control Network is used with interface and communication function.
Background technology
Single-chip microcomputer in the past and single-chip microcomputer, or the multiple access communication of single-chip microcomputer and PC personal computer generally is to utilize parallel interface to carry out serial bus communication.Used bus communication controller (claiming the bus communication control chip again) in communication substantially all is by the design of synchronous communication working method, is used for industry more.It is fast that this parallel interface bus communication controler has data transmission bauds, and antijamming capability is strong, and fault tolerance is strong, and the reliability height can be than the characteristics of working under the adverse circumstances.But the cost of manufacture of this bus communication controller is higher.In present home control system, controlling object is various electrical equipment (as TV, refrigerator, microwave oven etc.) that single-chip microcomputer is housed or by the electrical equipment (as by the electric light under the Single-chip Controlling, electric furnace, socket etc.) of single-chip microcomputer centralized monitor, system environments is better relatively, and is lower to the requirement of transfer of data.In the control system of home control system or similar application environment, use this parallel interface bus communication controler, obviously on function, have redundancy and cost higher.In the existing in addition home control system, the parallel port of the single-chip microcomputer on each controlling object all requires occupied because of internal control basically, therefore adopt this parallel interface bus communication controler, also to transform under many situations existing controlling object, this transformation had both increased the cost of home control system, made troubles for again controlling object manufacturer.Adopt parallel interface bus communication controler line more besides, complicated again.
For addressing the above problem, the applicant provides a kind of communication controller of serial interface bus in No. 02140851.3 patent application.This bus communication controller is to use serial line interface to carry out bus communication, and it both can significantly reduce the cost of manufacture of bus communication controller and the total cost of home control system; Can satisfy the communicating requirement of home control system again, adapt to existing controlling object, and the resource of existing controlling object is more made full use of.But there is the problem of the control logic more complicated of equipment CPU in this bus communication controller when using.For the equipment in the Control Network, if its CPU control logic more complicated may cause certain burden to the user and the manufacturer of equipment.In addition, complicated control logic, also the resource of CPU being used also has certain influence.Besides, this bus communication controller is when using, and initial work maybe needs to revise the state of communication controler, all must finish by special peripheral equipment.Therefore, desirable not enough on versatility.
Summary of the invention
The objective of the invention is to, a kind of read-write communication controller of serial interface bus of the SPI of having interface is provided.It is one and is integrated in the integrated circuit (IC) chip that one has communications component, data buffering processing unit, interface controller, SPI (Serial Peripheral Interface (SPI)) interface and EEPROM.This chip is when realizing communication, and control logic that can simplified apparatus CPU for the user and the manufacturer of equipment provides bigger convenience, and can reduce the resource occupation to equipment CPU; The user can revise the operating state of chip easily.This chip has better generality.
Technical scheme of the present invention.The read-write communication controller of serial interface bus of SPI interface is arranged, it is characterized in that: its formation comprises communications component, data buffering processing unit 1, interface controller, SPI interface and EEPROM; Communications component comprises bus portion and communication logic control section; The data buffering processing unit 2 that the formation of bus portion comprises bus end asynchronous serial Transmit-Receive Unit and joins with it; The communication logic control section comprises communication control unit, error count and fault processing circuit, carrier sense multiple access conflict monitoring circuit.
In the above-mentioned read-write communication controller of serial interface bus that the SPI interface is arranged, the formation of described bus end asynchronous serial Transmit-Receive Unit comprises bus end asynchronous serial transceiver, join with it also-string change-over circuit and string-and change-over circuit; The formation of described data buffering processing unit 2 comprises that bus sends data buffer zone and bus reception data buffer; Described communication control unit comprises, the transmit control register heap, and the cyclic redundancy code generation circuit receives the control register heap, address check circuit, CRC circuit, time-out check circuit.The formation of described data buffering processing unit 1 comprises that interface reception data buffer and interface send the data buffer zone.
In the aforesaid read-write communication controller of serial interface bus that the SPI interface arranged, described bus sends the data buffer zone and comprises data buffer zone 3, bus buffer district control circuit 1; The bus reception data buffer comprises data buffer zone 4, bus buffer district control circuit 2; Receive the control register heap and comprise that frame tagged word register file 2, interface transmit control register heap, bus receive control register heap, answering circuit 2 and answering circuit 4; The transmit control register heap comprises that frame tagged word register file 1, interface receive control register heap, bus transmit control register heap, answering circuit 1 and answering circuit 3; Interface end asynchronous serial transceiver comprises that interface asynchronism transceiver, frame format packeting circuit 1, frame format unpack circuit 1; Bus end asynchronous serial transceiver comprises that bus asynchronism transceiver, frame format packeting circuit 2, frame format unpack circuit 2.Described interface reception data buffer comprises data buffer zone 1, interface buffer control circuit 1, and interface sends the data buffer zone and comprises data buffer zone 2, interface buffer control circuit 2.
In the aforesaid read-write communication controller of serial interface bus that the SPI interface arranged, described interface controller comprises that frame packetization logic, frame unpack logic, frame control word and analyze actuating logic, add up and generate, add up and check logic is formed.
In the aforesaid read-write communication controller of serial interface bus that the SPI interface arranged, the frame packetization logic comprises frame packeting circuit and also-string change-over circuit, and frame unpacks logic and comprises that frame unpacks circuit and string-and change-over circuit.
The present invention is one and is integrated in the chip that one has communications component, data buffering processing unit, interface controller, SPI interface and EEPROM.Control logic of the present invention is that hardware is realized fully.The present invention is when realizing serial bus communication, utilize the agreement of SPI interface simple, fireballing characteristics, simplified the control logic of equipment CPU,, and can reduce resource occupation equipment CPU for the user and the manufacturer of equipment provides bigger convenience.The user not only can the slave unit end but also can by the mode that sends instructions the EEPROM in the chip have been read and write from bus end, can revise the operating state of communication controler easily.Has better generality.
Description of drawings
Accompanying drawing 2 is circuit structure Fig. 2 that the read-write communication controller of serial interface bus of SPI interface is arranged;
Accompanying drawing 3 is circuit structure Fig. 3 that the read-write communication controller of serial interface bus of SPI interface is arranged.
Embodiment
Embodiment.As shown in Figure 1, there is the formation of the read-write communication controller of serial interface bus of SPI interface to comprise communications component, data buffering processing unit 1, interface controller, programmable I/O, EEPROM and SPI (Serial Peripheral Interface (SPI)) interface; Communications component comprises bus portion and communication logic control section; The data buffering processing unit 2 that the formation of bus portion comprises bus end asynchronous serial Transmit-Receive Unit and joins with it; The communication logic control section comprises communication control unit, error count and fault processing circuit, carrier sense multiple access conflict monitoring circuit.As shown in Figure 2, the formation of bus end asynchronous serial Transmit-Receive Unit comprises bus end asynchronous serial transceiver, join with it also-string change-over circuit and string-and change-over circuit; The formation of data buffering processing unit 2 comprises that bus sends data buffer zone and bus reception data buffer; Communication control unit comprises, the transmit control register heap, and the cyclic redundancy code generation circuit receives the control register heap, address check circuit, CRC circuit, time-out check circuit.The formation of described data buffering processing unit 1 comprises that interface reception data buffer and interface send the data buffer zone.As shown in Figure 3, bus transmission data buffer zone comprises data buffer zone 3, bus buffer district control circuit 1; The bus reception data buffer comprises data buffer zone 4, bus buffer district control circuit 2; Receive the control register heap and comprise that frame tagged word register file 2, interface transmit control register heap, bus receive control register heap, answering circuit 2 and answering circuit 4; The transmit control register heap comprises that frame tagged word register file 1, interface receive control register heap, bus transmit control register heap, answering circuit 1 and answering circuit 3; Interface end asynchronous serial transceiver comprises that interface asynchronism transceiver, frame format packeting circuit 1, frame format unpack circuit 1; Bus end asynchronous serial transceiver comprises that bus asynchronism transceiver, frame format packeting circuit 2, frame format unpack circuit 2.Described interface reception data buffer comprises data buffer zone 1, interface buffer control circuit 1, and interface sends the data buffer zone and comprises data buffer zone 2, interface buffer control circuit 2.
Interface controller mainly unpacks logic, frame control word by frame packetization logic, frame and analyzes actuating logic, adds up and generate, add up and check logic is formed, the frame packetization logic comprises frame packeting circuit and also-string change-over circuit, and frame unpacks logic and comprises that frame unpacks circuit and string-and change-over circuit.The groundwork of interface controller is control command and the data that receive bus end by communications component, or the control command of receiving equipment CPU and data, remove to control and be provided with communications component and the inner EEPROM of read-write chip in the chip according to the command type that receives then.
The frame packetization logic: the task of frame packetization logic be interface send in the buffering area data through also-be packaged into behind the string change-over circuit contain initial symbol, data length, control command word, source address, data block, verification and and the frame sequence of end mark, supply equipment CPU reads by the SPI interface.And the data that from EEPROM, read, be packaged into contain initial symbol, data length, control command word, destination address, data block (programmable I/O state information or the data that read from EEPROM), verification and and the sequence frame of end mark deposit interface reception data buffer 1 in the form of parallel data.
Frame unpacks logic: be task that frame unpacks logic be the frame sequence that sends from the SPI interface module is unpacked after go here and there-and change-over circuit become parallel data and deposit interface data buffering area 1 in; The frame control word that frame control word in the frame sequence is given in the interface controller is analyzed actuating logic simultaneously, analyzes actuating logic by the frame control word and determines corresponding operation.And interface is sent frame sequence in the buffering area unpack data message and write EEPROM; The frame control word that frame control word in the frame sequence is given in the interface controller is analyzed actuating logic simultaneously, analyzes actuating logic by the frame control word and determines corresponding operation.
The frame control word is analyzed actuating logic: the task that the frame control word is analyzed actuating logic is that the frame control word that analysis is sent here is determined that the execution data communication still is read-write EEPROM, and sent corresponding concrete operations order.
Add up and generate, add up and check logic: add up and the function of formation logic be generate one add up and, supply equipment CPU checks whether the frame sequence of receiving from the SPI interface transmits errorless.Add up and the function of check logic be check the frame sequence sent by the SPI interface add up and whether specified data is transmitted errorless.
By the operation of bus interface and SPI interface: after interface controller is received a control command by bus end or from the SPI interface end to EEPROM, interface controller is defined as the EEPROM operational order after resolving, interface controller just produces corresponding EEPROM operation signal according to control command, the data of receiving are write EEPROM, or the data of certain memory cell or certain several memory cell among the EEPROM are read out, become frame sequence to send to bus these packing data or deliver to equipment CPU through the frame packetization logic.
By SPI interface and total line traffic control communications component: after receiving a control command from SPI interface end (or bus end), inform interface controller, interface controller is that interface controller will produce control signal corresponding and remove to be provided with communications component or data are sent to bus end (or SPI interface end) to order being set or sending data command of communications component through being defined as after resolving.
The read-write communication controller of serial interface bus of the whole SPI of having interface can be made into an integrated circuit (IC) chip.Can realize error count and fault processing function with the fatal error testing circuit shown in the accompanying drawing 3 during concrete the making, and-string change-over circuit and string-and change-over circuit can merger unpack in the circuit in frame format packeting circuit and frame format.
The operation principle that the read-write communication controller of serial interface bus of SPI interface is arranged: equipment CPU adopts the communication mode of SPI interface to contain the SPI command word to the transmission of the SPI of chip interface, initial symbol, data length, destination address, the control command word, data block, the frame sequence of end mark, through the string of interface controller-and change-over circuit become parallel data and deposit interface data buffering area 1 in.Simultaneously, send and add up and checking circuit, determine whether the transmission data are correct, send the transmit control register heap the result.The transmit control register heap extracts control command word, destination address and transmission data from the interface reception data buffer, and deposit bus in and send the data buffer zone, add local address, by the cyclic redundancy code generation circuit check code is deposited in check field simultaneously, and organize the bus transfer frame.(the bus transfer frame is the frame sequence with initial symbol, destination address, local address, control command word, length, data block, check field and end mark.) according to different control word decisions data to be sent to bus be to adopt the broadcast mode or the mode of intelligence transmission for transmit control register heap, start to send.The signal that collision detection provides according to carrier sense multiple access when being the bus free time, allows to send, and then starts to send.Bus sends the data buffer zone and data is sent also-gone here and there change-over circuit to form serial sequence.Send bus transfer frame through asynchronous serial bus interface BTX to communication bus by bus end asynchronous serial transceiver at last.Adopting the mode of " listening while saying " to determine whether to send successfully in the process of transmitting, specifically is that BRX by the asynchronous serial bus interface receives more whether the bit sequence of the bit sequence that sends to bus and transmission is input to the carrier sense multiple access collision detection circuit consistent.If consistent, then continue to send; If inconsistent then notify transmit control register heap and error count fault processing circuit immediately, stop transmission.If error count is overflowed, then carry out fault processing, stop to send, producing mismark etc.
On the contrary,, at first be input to bus end asynchronous serial transceiver, be reduced to 8 bit stream, send serial-parallel conversion circuit, CRC circuit, time-out check circuit through asynchronous serial bus interface BRX if communication bus is sent a transmission frame sequence.String-also then deposit the bus reception data buffer in after the conversion; The cyclic redundancy check circuit obtains sending reception control register heap behind the result, determines whether transmission frame is effective; The signal whether the time-out check circuit then provides frame sequence to finish can accurately reset whole receiving circuit, enters new wait accepting state.The address check circuit then extracts DAF destination address field and local address relatively from the bus reception data buffer, determine to mail to local transmission frame.Destination address, control command word and data block deposit interface transmission data buffer zone in the control register heap copy bus reception data buffer by receiving.Simultaneously by add up and generative circuit obtain verification and, also deposit interface in and send the data buffer zone.After data deposit reception data buffer in, receive the control register heap and produce a signalisation interface controller, at this moment interface controller will be provided with the state of accepting state register, and produce a signal simultaneously and remove announcement apparatus CPU, after equipment CPU responds this signal, the data of receiving from bus end through the packing in the interface controller and also-go here and there change-over circuit, convert serial data to, equipment CPU just can read in frame sequence by the SPI interface.
Frame tagged word register file 2 is the results that unpack according to frame, stores the tagged word of representative frame into the relevant register heap, as command word, frame length, source address, destination address, local update address, local update control register etc.Interface transmit control register heap is when control interface transmission interface buffering area control circuit 2 starts work; Judge that interface sends condition, start to send; Control adds up and generates (adding up and generation module); Control interface frame format packing (frame format packing 1).It is that the verification received frame is corrected errors that bus receives the control register heap. judge frame head, postamble, judge cyclic redundancy code (CRC module), judge information bit length, judge receive time-out (time-out check module), by source address, destination address, the judgment frame sending direction; The audit interface state judges whether to move frame information to interface; When control bus reception data buffer control module 2 starts work.The result that frame tagged word register file module 2 unpacks according to frame stores the tagged word of representative frame into the relevant register heap, as command word, frame length, source address, destination address, local update address, local update control register etc.It is that the verification received frame is corrected errors that interface receives the control register heap, judges frame head, postamble, judges and add up and (add up and check module) that judgment frame length is judged receive time-out (time-out check module); The supervision bus state judges whether to the bus translation frame information; When control interface buffering area control circuit 1 starts work.Bus transmit control register heap is when control bus buffering area control module 1 starts work; Judge that bus sends condition, start to send; The Control Circulation redundant code generates (cyclic redundancy code generation module); Control bus frame format packing (frame format packetization module).The data buffer zone comprises the interface reception data buffer, interface sends data buffer zone, bus reception data buffer, bus transmission data buffer zone 4 block RAMs, and every block size is 8*32bit.The buffering area control circuit is used to produce read-write control signal, the read/write address of data buffer zone (RAM) and empties the buffering area signal.The frame structure parse module is the characteristics according to dissimilar frame structures, and frame data are unpacked.The frame structure packetization module is the characteristics according to dissimilar frame structures, and frame data are packed.Asynchronism transceiver (UART) module is to receive and the standard of transmission start-stop type charcter topology start bit, 8 bit data positions and a position of rest.If the charcter topology mistake, interface end abandons automatically; The fatal error of then carrying out bus end detects (fatal error detection module) and replys judge module: the acknowledgement frame that receives is handled accordingly; Check results to non-acknowledgement frame is replied processing accordingly; Chip is provided with frame is replied and warm reset (having only interface that this function is arranged); Start transmission transmission acknowledgement frame (having only bus that this function is arranged) according to bus acknowledge situation control interface.Carrier sense, collision detection module are used for the real-time listening bus, and address priority is judged in collision detection.Sample frequency is 16 times of interface baud rate.The fatal error testing circuit is the charcter topology when set form when containing one or more non-tagmeme, then detects a form error, produces bus error (fatal error) when being accumulated to 128 form errors.And control interface transmit control register heap starts interface transmission transmission fatal error frame.
Wherein for equipment through SPI interface transmission frame sequence that send or that bus end is sent, interface controller is defined as the EEPROM operational order after resolving, interface controller just produces corresponding EEPROM operation signal according to control command, the data of receiving are write EEPROM or the data of certain memory cell or certain several memory cell among the EEPROM are read out, send to bus by after the interface controller packing, or deliver to equipment through the SPI interface.
Control Network of the present invention is meant a kind of local area network (LAN) that personal computer, household electrical appliance, water power hot air heating table, illuminator and safety system etc. in family's category are linked together.Its major function is various electric equipments and local area network (LAN) inserted external network in the centralized control local area network (LAN).
Claims (5)
1, the read-write communication controller of serial interface bus of SPI interface is arranged, it is characterized in that: its formation comprises communications component, data buffering processing unit 1, interface controller, SPI interface and EEPROM; Communications component comprises bus portion and communication logic control section; The data buffering processing unit 2 that the formation of bus portion comprises bus end asynchronous serial Transmit-Receive Unit and joins with it; The communication logic control section comprises communication control unit, error count and fault processing circuit, carrier sense multiple access conflict monitoring circuit.
2, the read-write communication controller of serial interface bus that the SPI interface is arranged according to claim 1, it is characterized in that: the formation of described bus end asynchronous serial Transmit-Receive Unit comprises bus end asynchronous serial transceiver, join with it also-string change-over circuit and string-and change-over circuit; The formation of described data buffering processing unit 2 comprises that bus sends data buffer zone and bus reception data buffer; Described communication control unit comprises, the transmit control register heap, and the cyclic redundancy code generation circuit receives the control register heap, address check circuit, CRC circuit, time-out check circuit; The formation of described data buffering processing unit 1 comprises that interface reception data buffer and interface send the data buffer zone.
3, the read-write communication controller of serial interface bus that the SPI interface is arranged according to claim 2 is characterized in that: described bus sends the data buffer zone and comprises data buffer zone 3, bus buffer district control circuit 1; The bus reception data buffer comprises data buffer zone 4, bus buffer district control circuit 2; Receive the control register heap and comprise that frame tagged word register file 2, interface transmit control register heap, bus receive control register heap, answering circuit 2 and answering circuit 4; The transmit control register heap comprises that frame tagged word register file 1, interface receive control register heap, bus transmit control register heap, answering circuit 1 and answering circuit 3; Interface end asynchronous serial transceiver comprises that interface asynchronism transceiver, frame format packeting circuit 1, frame format unpack circuit 1; Bus end asynchronous serial transceiver comprises that bus asynchronism transceiver, frame format packeting circuit 2, frame format unpack circuit 2; Described interface reception data buffer comprises data buffer zone 1, interface buffer control circuit 1, and interface sends the data buffer zone and comprises data buffer zone 2, interface buffer control circuit 2.
4, according to claim 1, the 2 or 3 described read-write communication controller of serial interface bus that the SPI interface is arranged, it is characterized in that: described interface controller comprises that frame packetization logic, frame unpack logic, the frame control word is analyzed actuating logic, added up and generate, add up and the check logic composition.
5, the read-write communication controller of serial interface bus that the SPI interface is arranged according to claim 4 is characterized in that: the frame packetization logic comprises frame packeting circuit and also-string change-over circuit, and frame unpacks logic and comprises that frame unpacks circuit and string-and change-over circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2005100032802A CN1964304A (en) | 2005-11-11 | 2005-11-11 | Readable and writable serial interface bus communication controller with SPI interface |
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| CNA2005100032802A CN1964304A (en) | 2005-11-11 | 2005-11-11 | Readable and writable serial interface bus communication controller with SPI interface |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103246588A (en) * | 2013-05-16 | 2013-08-14 | 中国电子科技集团公司第四十一研究所 | Controller and implementation method for self-checking serial bus |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103246588A (en) * | 2013-05-16 | 2013-08-14 | 中国电子科技集团公司第四十一研究所 | Controller and implementation method for self-checking serial bus |
| CN103246588B (en) * | 2013-05-16 | 2015-03-25 | 中国电子科技集团公司第四十一研究所 | Controller and implementation method for self-checking serial bus |
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