CN1964303A - Read-write programmable I/O interface controller/communication controller - Google Patents
Read-write programmable I/O interface controller/communication controller Download PDFInfo
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- CN1964303A CN1964303A CNA200510003279XA CN200510003279A CN1964303A CN 1964303 A CN1964303 A CN 1964303A CN A200510003279X A CNA200510003279X A CN A200510003279XA CN 200510003279 A CN200510003279 A CN 200510003279A CN 1964303 A CN1964303 A CN 1964303A
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Abstract
A read-write programmable I/O interface controller/communication controller. The device comprises a communication component, a data buffer processing unit 1, an interface controller, a programmable I/O and an EEPROM; the communication assembly comprises a bus part and a communication logic control part; the bus part comprises a bus end serial asynchronous receiving and transmitting unit and a data buffer processing unit 2 connected with the bus end serial asynchronous receiving and transmitting unit; the communication logic control part comprises a communication control unit, an error counting and processing circuit and a carrier sense multiple access collision monitoring circuit. The invention does not need to process the information of the control object in advance, can further reduce the total cost of the control network, further improve the reliability of communication and increase the control function. The user can easily modify the operating state of the communication controller. Has better universality. The invention is suitable for controlling lighting, safety alarm equipment, entrance guard intercom equipment, holder equipment, motor control equipment and other equipment in a control network.
Description
Technical field
The present invention relates to the control device that a kind of Control Network is used, the control device that particularly a kind of Control Network is used with interface and communication function.
Background technology
Single-chip microcomputer in the past and single-chip microcomputer, or the multiple access communication of single-chip microcomputer and PC personal computer generally is to utilize parallel interface to carry out serial bus communication.Used bus communication controller (claiming the bus communication control chip again) in communication substantially all is by the design of synchronous communication working method, is used for industry more.It is fast that this parallel interface bus communication controler has data transmission bauds, and antijamming capability is strong, and fault tolerance is strong, and the reliability height can be than the characteristics of working under the adverse circumstances.But the cost of manufacture of this bus communication controller is higher.In present home control system, controlling object is various electrical equipment (as TV, refrigerator, microwave oven etc.) that single-chip microcomputer is housed or by the electrical equipment (as by the electric light under the Single-chip Controlling, electric furnace, socket etc.) of single-chip microcomputer centralized monitor, system environments is better relatively, and is lower to the requirement of transfer of data.In the control system of home control system or similar application environment, use this parallel interface bus communication controler, obviously on function, have redundancy and cost higher.In the existing in addition home control system, the parallel port of the single-chip microcomputer on each controlling object all requires occupied because of internal control basically, therefore adopt this parallel interface bus communication controler, also to transform under many situations existing controlling object, this transformation had both increased the cost of home control system, made troubles for again controlling object manufacturer.Adopt parallel interface bus communication controler line more besides, complicated again.
For addressing the above problem, the applicant provides a kind of communication controller of serial interface bus in No. 02140851.3 patent application.This bus communication controller is to use serial line interface to carry out bus communication, and it both can significantly reduce the cost of manufacture of bus communication controller and the total cost of home control system; Can satisfy the communicating requirement of home control system again, adapt to existing controlling object, and the resource of existing controlling object is more made full use of.But self does not possess controlled function this communication controler, the controlling object that application is information-based, for not informationalized controlling object, need do information-based the processing earlier after, could use.And the switching value controlling object more single to some function ratio, equipment such as for example illumination, security alarm device, gate inhibition's talk back equipment, The Cloud Terrace equipment and Electric Machine Control, handle if carry out informationization (increase single-chip microcomputer) earlier, can increase equipment cost and make the control procedure complexity.This besides bus communication controller is when using, and initial work maybe needs to revise the state of communication controler, all must finish by external dedicated equipment.Therefore, desirable not enough on versatility.
Summary of the invention
The objective of the invention is to, a kind of read-write programming I/O interface controller/communication controller is provided.It is one and is integrated in the control device that one has communications component, interface controller, programmable I/O and SPI (Serial Peripheral Interface (SPI)) interface.Control logic of the present invention is that hardware is realized fully.The present invention both can be used as interface controller and had used, and can be used as communication controler again and used.The present invention has further reduced the total cost of home control system, has also further improved the reliability of communication and has increased controlled function.
Technical scheme of the present invention.Read-write programming I/O interface controller/communication controller, it is characterized in that: its formation comprises communications component, data buffering processing unit 1, interface controller, programmable I/O and EEPROM; Communications component comprises bus portion and communication logic control section; The data buffering processing unit 2 that the formation of bus portion comprises bus end asynchronous serial Transmit-Receive Unit and joins with it; The communication logic control section comprises communication control unit, error count and fault processing circuit, carrier sense multiple access conflict monitoring circuit.
In the above-mentioned read-write programming I/O interface controller/communication controller, the formation of described bus end asynchronous serial Transmit-Receive Unit comprises bus end asynchronous serial transceiver, join with it also-string change-over circuit and string-and change-over circuit; The formation of described data buffering processing unit 2 comprises that bus sends data buffer zone and bus reception data buffer; Described communication control unit comprises, the transmit control register heap, and the cyclic redundancy code generation circuit receives the control register heap, address check circuit, CRC circuit, time-out check circuit.The formation of described data buffering processing unit 1 comprises that interface reception data buffer and interface send the data buffer zone.
In the aforesaid read-write programming I/O interface controller/communication controller, described bus sends the data buffer zone and comprises data buffer zone 3, bus buffer district control circuit 1; The bus reception data buffer comprises data buffer zone 4, bus buffer district control circuit 2; Receive the control register heap and comprise that frame tagged word register file 2, interface transmit control register heap, bus receive control register heap, answering circuit 2 and answering circuit 4; The transmit control register heap comprises that frame tagged word register file 1, interface receive control register heap, bus transmit control register heap, answering circuit 1 and answering circuit 3; Interface end asynchronous serial transceiver comprises that interface asynchronism transceiver, frame format packeting circuit 1, frame format unpack circuit 1; Bus end asynchronous serial transceiver comprises that bus asynchronism transceiver, frame format packeting circuit 2, frame format unpack circuit 2.Described interface reception data buffer comprises data buffer zone 1, interface buffer control circuit 1, and interface sends the data buffer zone and comprises data buffer zone 2, interface buffer control circuit 2.
In the aforesaid read-write programming I/O interface controller/communication controller, described interface controller comprises that frame packetization logic circuit, frame unpack logical circuit and the frame control word is analyzed execution logic circuit.
In the aforesaid read-write programming I/O interface controller/communication controller, the frame packetization logic comprises frame packeting circuit and also-string change-over circuit, and frame unpacks logic and comprises that frame unpacks circuit and string-and change-over circuit.
The present invention is one and is integrated in the chip that one has communications component, interface controller, programmable I/O, EEPROM.The present invention both can be used as interface controller and had used, and can be used as communication controler again and used.Control logic of the present invention is that hardware is realized fully, for the more single switching value controlling object of some function ratio, uses the present invention, need not carry out informationization to controlling object earlier and handle, and also can not increase equipment cost and use complicated control command.Therefore, can further reduce the total cost of Control Network, also further improve the reliability of communication and increased controlled function.The user can read and write the EEPROM in the chip by the mode that sends instructions, and can revise the operating state of communication controler easily, has better generality.The present invention is applicable to Equipment Control such as the illumination in the Control Network, security alarm device, gate inhibition's talk back equipment, The Cloud Terrace equipment and Electric Machine Control is used.
Description of drawings
Accompanying drawing 2 is circuit structure Fig. 2 of read-write programming I/O interface controller/communication controller;
Accompanying drawing 3 is circuit structure Fig. 3 of read-write programming I/O interface controller/communication controller.
Embodiment
Embodiment.As shown in Figure 1, the formation of read-write programming I/O interface controller/communication controller comprises communications component, data buffering processing unit 1, interface controller, programmable I/O and EEPROM; Communications component comprises bus portion and communication logic control section; The data buffering processing unit 2 that the formation of bus portion comprises bus end asynchronous serial Transmit-Receive Unit and joins with it; The communication logic control section comprises communication control unit, error count and fault processing circuit, carrier sense multiple access conflict monitoring circuit.As shown in Figure 2, the formation of bus end asynchronous serial Transmit-Receive Unit comprises bus end asynchronous serial transceiver, join with it also-string change-over circuit and string-and change-over circuit; The formation of data buffering processing unit 2 comprises that bus sends data buffer zone and bus reception data buffer; Communication control unit comprises, the transmit control register heap, and the cyclic redundancy code generation circuit receives the control register heap, address check circuit, CRC circuit, time-out check circuit.The formation of described data buffering processing unit 1 comprises that interface reception data buffer and interface send the data buffer zone.As shown in Figure 3, bus transmission data buffer zone comprises data buffer zone 3, bus buffer district control circuit 1; The bus reception data buffer comprises data buffer zone 4, bus buffer district control circuit 2; Receive the control register heap and comprise that frame tagged word register file 2, interface transmit control register heap, bus receive control register heap, answering circuit 2 and answering circuit 4; The transmit control register heap comprises that frame tagged word register file 1, interface receive control register heap, bus transmit control register heap, answering circuit 1 and answering circuit 3; Interface end asynchronous serial transceiver comprises that interface asynchronism transceiver, frame format packeting circuit 1, frame format unpack circuit 1; Bus end asynchronous serial transceiver comprises that bus asynchronism transceiver, frame format packeting circuit 2, frame format unpack circuit 2.Described interface reception data buffer comprises data buffer zone 1, interface buffer control circuit 1, and interface sends the data buffer zone and comprises data buffer zone 2, interface buffer control circuit 2.
Interface controller mainly unpacks logical circuit by frame packetization logic circuit, frame and frame control word analysis execution logic circuit is formed.The frame packetization logic comprises frame packeting circuit and also-string change-over circuit, and frame unpacks logic and comprises that frame unpacks circuit and string-and change-over circuit.
The effect of frame packetization logic is, the state change information of programmable I/O and the data that from EEPROM, read, be packaged into contain initial symbol, data length, control command word, destination address, data block (programmable I/O state information or the data that read from EEPROM), verification and and the sequence frame of end mark deposit interface reception data buffer 1 in the form of parallel data.
The effect that frame unpacks logic is, interface sent frame sequence in the buffering area separate and be bundled into control command and give programmable I/O, or separate and be bundled into data message and write EEPROM.The frame control word that frame control word in the frame sequence is given in the interface controller is analyzed actuating logic simultaneously, analyzes actuating logic by the frame control word and determines corresponding concrete operations.
The task that the frame control word is analyzed actuating logic is that the frame control word that analysis is sent here is determined to carry out control programmable I/O operation and still read and write EEPROM, and sends corresponding concrete operations order.
By bus interface programmable I/O or EEPROM are operated: communications component is informed interface controller after receiving a control command by bus end.Interface controller is defined as the I/O operational order through after resolving, and at this moment interface controller will produce control signal corresponding, goes programmable I/O is carried out function setting or controls; Interface controller also detects the input port of programmable I/O simultaneously, when the input port of programmable I/O state changes, interface controller will be packaged into frame sequence with these change informations through the frame packetization logic and send communications component to, sends to bus by communications component.Interface controller is defined as the EEPROM operational order after resolving, interface controller just produces corresponding EEPROM operation signal according to control command, the data of receiving are write EEPROM, or the data of certain memory cell or certain several memory cell among the EEPROM are read out, become frame sequence to send communications component to these packing data through the frame packetization logic, send to bus by communications component.
Whole read-write programming I/O interface controller/communication controller is made into an integrated circuit (IC) chip.Can realize error count and fault processing function with the fatal error testing circuit shown in the accompanying drawing 3 during concrete the making, and-string change-over circuit and string-and change-over circuit can merger unpack in the circuit in frame format packeting circuit and frame format.
The operation principle of read-write programming I/O interface controller/communication controller: when the input port state of programmable I/O changes, state information through interface controller be converted to initial symbol, data length, control command word, destination address, data block, verification and and the frame sequence parallel data of end mark deposit interface data buffering area 1 in.Simultaneously, send and add up and checking circuit, determine whether the transmission data are correct, send the transmit control register heap the result.The transmit control register heap extracts control command word, destination address and transmission data from the interface reception data buffer, and deposit bus in and send the data buffer zone, add local address, by the cyclic redundancy code generation circuit check code is deposited in check field simultaneously, and organize the bus transfer frame.(the bus transfer frame is the frame sequence with initial symbol, destination address, local address, control command word, length, data block, check field and end mark.) according to different control word decisions data to be sent to bus be to adopt the broadcast mode or the mode of intelligence transmission for transmit control register heap, start to send.The signal that collision detection provides according to carrier sense multiple access when being the bus free time, allows to send, and then starts to send.Bus sends the data buffer zone and data is sent also-gone here and there change-over circuit to form serial sequence.Send bus transfer frame through asynchronous serial bus interface BTX to communication bus by bus end asynchronous serial transceiver at last.Adopting the mode of " listening while saying " to determine whether to send successfully in the process of transmitting, specifically is that BRX by the asynchronous serial bus interface receives more whether the bit sequence of the bit sequence that sends to bus and transmission is input to the carrier sense multiple access collision detection circuit consistent.If consistent, then continue to send; If inconsistent then notify transmit control register heap and error count fault processing circuit immediately, stop transmission.If error count is overflowed, then carry out fault processing, stop to send, producing mismark etc.
On the contrary,, at first be input to bus end asynchronous serial transceiver, be reduced to 8 bit stream, send serial-parallel conversion circuit, CRC circuit, time-out check circuit through asynchronous serial bus interface BRX if communication bus is sent a transmission frame sequence.String-also then deposit the bus reception data buffer in after the conversion; The cyclic redundancy check circuit obtains sending reception control register heap behind the result, determines whether transmission frame is effective; The signal whether the time-out check circuit then provides frame sequence to finish can accurately reset whole receiving circuit, enters new wait accepting state.The address check circuit then extracts DAF destination address field and local address relatively from the bus reception data buffer, determine to mail to local transmission frame.Destination address, control command word and data block deposit interface transmission data buffer zone in the control register heap copy bus reception data buffer by receiving.Simultaneously by add up and generative circuit obtain verification and, also deposit interface in and send the data buffer zone.After data deposit reception data buffer in, receive the control register heap and produce a signalisation interface controller, at this moment interface controller will be provided with the state of accepting state register, and will have simultaneously initial symbol, data length, control command word, destination address, data block, verification and and the frame sequence of end mark be converted to a control signal and remove to notify programmable I/O, programmable I/O is after this signal of response, the operation signal that output is corresponding, equipment is carried out corresponding operation.
Frame tagged word register file 2 is the results that unpack according to frame, stores the tagged word of representative frame into the relevant register heap, as command word, frame length, source address, destination address, local update address, local update control register etc.Interface transmit control register heap is when control interface transmission interface buffering area control circuit 2 starts work; Judge that interface sends condition, start to send; Control adds up and generates (adding up and generation module); Control interface frame format packing (frame format packing 1).It is that the verification received frame is corrected errors that bus receives the control register heap, judges frame head, postamble, judges cyclic redundancy code (CRC module), judge information bit length, judge receive time-out (time-out check module), by source address, destination address, the judgment frame sending direction; The audit interface state judges whether to move frame information to interface; When control bus reception data buffer control module 2 starts work.The result that frame tagged word register file module 2 unpacks according to frame stores the tagged word of representative frame into the relevant register heap, as command word, frame length, source address, destination address, local update address, local update control register etc.It is that the verification received frame is corrected errors that interface receives the control register heap, judges frame head, postamble, judges and add up and (add up and check module) that judgment frame length is judged receive time-out (time-out check module); The supervision bus state judges whether to the bus translation frame information; When control interface buffering area control circuit 1 starts work.Bus transmit control register heap is when control bus buffering area control module 1 starts work; Judge that bus sends condition, start to send; The Control Circulation redundant code generates (cyclic redundancy code generation module); Control bus frame format packing (frame format packetization module).The data buffer zone comprises the interface reception data buffer, interface sends data buffer zone, bus reception data buffer, bus transmission data buffer zone 4 block RAMs, and every block size is 8*32bit.The buffering area control circuit is used to produce read-write control signal, the read/write address of data buffer zone (RAM) and empties the buffering area signal.The frame structure parse module is the characteristics according to dissimilar frame structures, and frame data are unpacked.The frame structure packetization module is the characteristics according to dissimilar frame structures, and frame data are packed.Asynchronism transceiver (UART) module is to receive and the standard of transmission start-stop type charcter topology start bit, 8 bit data positions and a position of rest.If the charcter topology mistake, interface end abandons automatically; The fatal error of then carrying out bus end detects (fatal error detection module) and replys judge module: the acknowledgement frame that receives is handled accordingly; Check results to non-acknowledgement frame is replied processing accordingly; Chip is provided with frame is replied and warm reset (having only interface that this function is arranged); Start transmission transmission acknowledgement frame (having only bus that this function is arranged) according to bus acknowledge situation control interface.Carrier sense, collision detection module are used for the real-time listening bus, and address priority is judged in collision detection.Sample frequency is 16 times of interface baud rate.The fatal error testing circuit is the charcter topology when set form when containing one or more non-tagmeme, then detects a form error, produces bus error (fatal error) when being accumulated to 128 form errors.And control interface transmit control register heap starts interface transmission transmission fatal error frame.
Wherein, the transmission frame sequence of sending for bus end, interface controller is defined as the EEPROM operational order after resolving, interface controller just produces corresponding EEPROM operation signal according to control command, the data of receiving are write EEPROM, or the data of certain memory cell or certain several memory cell among the EEPROM are read out, send to bus after the packing.
Control Network of the present invention is meant a kind of local area network (LAN) that personal computer, household electrical appliance, water power hot air heating table, illuminator and safety system etc. in family's category are linked together.Its major function is various electric equipments and local area network (LAN) inserted external network in the centralized control local area network (LAN).
Claims (5)
1, read-write programming I/O interface controller/communication controller, it is characterized in that: its formation comprises communications component, data buffering processing unit 1, interface controller, programmable I/O and EEPROM; Communications component comprises bus portion and communication logic control section; The data buffering processing unit 2 that the formation of bus portion comprises bus end asynchronous serial Transmit-Receive Unit and joins with it; The communication logic control section comprises communication control unit, error count and fault processing circuit, carrier sense multiple access conflict monitoring circuit.
2, read-write programming I/O interface controller/communication controller according to claim 1, it is characterized in that: the formation of described bus end asynchronous serial Transmit-Receive Unit comprises bus end asynchronous serial transceiver, join with it also-string change-over circuit and string-and change-over circuit; The formation of described data buffering processing unit 2 comprises that bus sends data buffer zone and bus reception data buffer; Described communication control unit comprises, the transmit control register heap, and the cyclic redundancy code generation circuit receives the control register heap, address check circuit, CRC circuit, time-out check circuit; The formation of described data buffering processing unit 1 comprises that interface reception data buffer and interface send the data buffer zone.
3, read-write programming I/O interface controller/communication controller according to claim 2 is characterized in that: described bus sends the data buffer zone and comprises data buffer zone 3, bus buffer district control circuit 1; The bus reception data buffer comprises data buffer zone 4, bus buffer district control circuit 2; Receive the control register heap and comprise that frame tagged word register file 2, interface transmit control register heap, bus receive control register heap, answering circuit 2 and answering circuit 4; The transmit control register heap comprises that frame tagged word register file 1, interface receive control register heap, bus transmit control register heap, answering circuit 1 and answering circuit 3; Interface end asynchronous serial transceiver comprises that interface asynchronism transceiver, frame format packeting circuit 1, frame format unpack circuit 1; Bus end asynchronous serial transceiver comprises that bus asynchronism transceiver, frame format packeting circuit 2, frame format unpack circuit 2.Described interface reception data buffer comprises data buffer zone 1, interface buffer control circuit 1, and interface sends the data buffer zone and comprises data buffer zone 2, interface buffer control circuit 2.
4, according to claim 1,2 or 3 described read-write programming I/O interface controller/communication controllers, it is characterized in that: described interface controller comprises that frame packetization logic circuit, frame unpack logical circuit and the frame control word is analyzed execution logic circuit.
5, read-write programming I/O interface controller/communication controller according to claim 4 is characterized in that: the frame packetization logic comprises frame packeting circuit and also-string change-over circuit, and frame unpacks logic and comprises that frame unpacks circuit and string-and change-over circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA200510003279XA CN1964303A (en) | 2005-11-11 | 2005-11-11 | Read-write programmable I/O interface controller/communication controller |
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| CNA200510003279XA CN1964303A (en) | 2005-11-11 | 2005-11-11 | Read-write programmable I/O interface controller/communication controller |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105981319A (en) * | 2014-02-17 | 2016-09-28 | 罗伯特·博世有限公司 | Participant station for a bus system, and method for increasing the data rate of a bus system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105981319A (en) * | 2014-02-17 | 2016-09-28 | 罗伯特·博世有限公司 | Participant station for a bus system, and method for increasing the data rate of a bus system |
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