CN1957527A - Differential stage voltage offset trimming circuit - Google Patents
Differential stage voltage offset trimming circuit Download PDFInfo
- Publication number
- CN1957527A CN1957527A CN 200480043157 CN200480043157A CN1957527A CN 1957527 A CN1957527 A CN 1957527A CN 200480043157 CN200480043157 CN 200480043157 CN 200480043157 A CN200480043157 A CN 200480043157A CN 1957527 A CN1957527 A CN 1957527A
- Authority
- CN
- China
- Prior art keywords
- current
- voltage
- transistor
- differential pair
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009966 trimming Methods 0.000 title claims abstract description 35
- 230000004044 response Effects 0.000 claims description 29
- 230000008859 change Effects 0.000 claims description 17
- 230000007423 decrease Effects 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 101150093559 TRIM2 gene Proteins 0.000 claims description 9
- 230000000295 complement effect Effects 0.000 claims description 7
- 230000003247 decreasing effect Effects 0.000 claims description 4
- 230000001052 transient effect Effects 0.000 claims 11
- 238000010586 diagram Methods 0.000 description 9
- 230000001105 regulatory effect Effects 0.000 description 4
- 102100037224 Noncompact myelin-associated protein Human genes 0.000 description 3
- 101710184695 Noncompact myelin-associated protein Proteins 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Landscapes
- Amplifiers (AREA)
Abstract
A differential stage voltage offset trimming circuit includes one or more trimming circuits, each dedicated to trimming the voltage offset (Vbias) of a "main" differential pairos) One particular source of error. A trimming circuit may be dedicated to trimming V caused by mismatch between the threshold voltages of the main pairosError, while another trim circuit may be dedicated to trimming V due to mismatch between the beta values of the main pairosAnd (4) error. Another trim circuit trims V caused by gamma mismatch between main pair transistorsosError, and a corresponding trimming circuit may be used to trim V caused by threshold mismatch and/or beta mismatch between transistors of an active load driven by the main pairosAnd (4) error. Several trimming circuits may be used simultaneously to reduce the offset error caused by each of several sources.
Description
The application requires to enjoy the temporary patent application No.60/558 that Kalb submitted on March 31st, 2004,401 right.
Technical field
The present invention relates to the field of difference transistor amplifying stage, relate in particular to the circuit and the method for the bias voltage that is used to finely tune differential transistor stage.
Background technology
All crystal amplifiers all exist influences the voltage bias of its precision (V
OS) error.This biased error causes by several mechanism the influence of MOSFET amplifier.The main cause of the biased error in the MOSFET input stage is owing to constitute two right transistorized threshold voltage (V of difference input
T) between mismatch cause.Known have several schemes to can be used to regulate this error.Usually, fine-adjusting current difference ground is injected the right drain electrode of input, Fig. 1 a shows this scheme.The difference input makes its source terminal link to each other with common node 10 to MN1 and MN2, and its grid is linked to each other to receive difference input voltage V
+～V
-Bias current sources 12 provides bias current to common node 10, makes MN1 and MN2 in response to putting on V
+And V
-Difference input voltage conduction corresponding output current; At this, input stage drives the active load that comprises transistor MP1 and MP2. Trim currents sources 14 and 16 is respectively with fine-adjusting current I
Trim+And I
Trim-Be injected into the drain electrode of MN1 and MN2 respectively, and through regulating the voltage offset error that reduces this utmost point.
Usually, the method for trimming shown in Fig. 1 a only is accurate under the condition of a biasing, and along with the input common mode variations in the precise decreasing (especially in the rail-to-rail amplifier).Can regulate tracking at temperature by design engineer or Test Engineer to temperature variant fine setting, but fine tune temperature and do not rely on any physical process and must determine by rule of thumb on the contrary.
Another kind of V
OSMethod for trimming relates to the degeneracy resistor is inserted in the right source circuit of input; Fig. 1 b and 1c show two kinds of possible technical schemes.In Fig. 1 b, can change the size of current that flows through resistor by the resistance value that changes resistor, thereby on a working point, produce needed offset change.In Fig. 1 c, can between two current sources, divide tail current, and can change bias fine-tuning by adding or deduct fine-adjusting current from tail current.Unfortunately, this method can produce the imbalance of non-expectation between the right both sides of input.In addition, these two methods all can reduce the gain and the common-mode input range of input stage.
Summary of the invention
A kind of differential levels offset voltage trim circuitry is provided, and it can overcome the problems referred to above and accurate bias fine-tuning is provided on the scope at input common mode voltage under the situation of not using the degeneracy resistor.The present invention can also solve by the caused biased error of the transistor of active load.
The present invention relates to the use of one or more trimming circuits, each trimming circuit is exclusively used in a particular source of the biased error of fine setting " master " differential pair.For example, owing to, the invention provides second differential pair in the caused trim offset error of leading between the right threshold voltage of mismatch, and be configured to make the input common mode voltage of second differential pair to approximate the circuit of leading right input common mode voltage.Subsequently, first and second programmable current sources provide corresponding electric current to second pair control input, to produce the expectation differential voltage on second differential pair.This just makes this second couple can conduct the fine-adjusting current that corresponding and main right output current is coupled.Current source is programmed, thereby finely tune main centering because of voltage offset error that threshold mismatch produced.Another trimming circuit is exclusively used in correction because of the caused error of mismatch between the right β value of master.At this, as the master second differential pair of biasing is linked to each other with the electric current that produces and the master is directly proportional to tail current, and the master will follow the tracks of main right common-mode voltage to tail current.Second pair conducts reference current in response, and this reference current puts on the reference current input of digital to analog converter (DAC).DAC produces fine-adjusting current in corresponding electric current output, wherein fine-adjusting current changes along with reference current, and increases and decreases in proportion according to the numerical value on the digital input end that puts on DAC.Fine-adjusting current is coupled with main right output current.Can programme to DAC, to finely tune the biased error that main centering is produced because of the β mismatch.
Be exclusively used in fine setting and comprise the circuit that produces reference current because of the circuit of leading the biased error that the γ mismatch between the transistor is produced, this reference current is linear change (the perhaps linear change (for example ax+b) along with additive constant, in other place along with subtracting each other constant linear change) along with main right input common mode voltage.DAC receives reference current, and produce along with reference current change, and according to put on that numerical value in the input of DAC numeral increases and decreases in proportion electric current I 1 and I2.The 3rd differential pair receives I1 and I2 and conducts corresponding fine-adjusting current in response.Fine-adjusting current is coupled with main right output current, and DAC is programmed, to finely tune the voltage offset error that main centering is produced because of the γ mismatch.
Can provide similar circuit, the biased error that the threshold mismatch between the transistor of the active load that drives and/or β mismatch is produced in order to fine setting reason master.Preferably, some trimming circuits discussed in this article can adopt simultaneously, to reduce the biased error that each was produced because of several sources.
To those skilled in the art, from following go through and accompanying drawing other features and advantages of the present invention become apparent.
Description of drawings
Fig. 1 a-1c shows known differential input stage offset voltage trim circuitry.
Fig. 2 is the schematic diagram that is used to finely tune the circuit of threshold mismatch according to the present invention.
Fig. 3 is the schematic diagram that is used to finely tune another circuit of threshold mismatch according to the present invention.
Fig. 4 is the schematic diagram that is used to finely tune the another circuit of threshold mismatch according to the present invention.
Fig. 5 a and 5b are the schematic diagrames that is used to finely tune the circuit of β mismatch according to the present invention.
Fig. 6 is the schematic diagram that is used to finely tune the circuit of γ mismatch according to the present invention.
Fig. 7 is the schematic diagram of another embodiment that is used to finely tune the circuit of γ mismatch according to the present invention.
Fig. 8 is the schematic diagram that is used to finely tune the circuit of the mismatch between the threshold value of differential levels active load according to the present invention.
Fig. 9 is the schematic diagram that is used to finely tune the circuit of the mismatch between the β value of differential levels active load according to the present invention.
Figure 10 is the schematic diagram that is used to reduce from the circuit of the biased error of some not homologies.
Embodiment
The invention provides several trimming circuits, each trimming circuit is all at a particular source of the bias voltage error of differential levels.When being used in combination, the voltage offset error of this grade can significantly reduce.
Circuit discussed in this article can be applicable to ambipolar and FET type differential levels, no matter is that input stage also is non-input stage.The present invention also can be applicable to the active load of differential levels.Because the present invention can be used for reducing the bias voltage error that is associated with P type and N type differential pair, so also can expect the rail-to-rail amplifier.Yet, for purposes of discussion, use single FET differential input stage that work of the present invention is described.
The most common source of voltage offset error is because the mismatch of forming between the transistorized threshold voltage of " master " differential pair (that is, reduce its bias voltage error to) produces in the FET differential input stage.The present invention can reduce this error by second differential pair is set, and this second differential pair has input common mode voltage and approximates main right input common mode voltage.Fig. 2 shows the circuit that is used to realize this purpose.Main differential pair MN1 links to each other its source electrode with MN2 on common node 10, this common node is also connected to current source 12.The grid of MN1 and MN2 is connected to corresponding input V
-And V
+, they receive a difference input voltage.Current source 12 to the first bias current n*I is provided, makes MN1 and MN2 in response to putting on V to main
-And V
+Difference input voltage conduction corresponding output current I
Out1And I
Out2Output current I
Out1And I
Out2Usually all be connected to gain or output stage (not shown).
The second differential pair MN3 links to each other its source electrode with MN4 on common node 14, this common node is also connected to the current source 16 that the second bias current I is provided to second differential pair.Servomechanism, preferably operational amplifier A 1, makes its input be connected to common node 10 and 14, and makes its output be connected to node 18, and this node 18 is coupled via the grid of resistor R 1 and R2 and MN3 and MN4.
The above connects A1 and second pair common node 14 is compensated becomes to equal main right common node 10.The size of MN3 and MN4 (1*X) becomes the ratio that equals second bias current (I) and first bias current (n*I) with the ratio of the size (n*X) of MN1 and MN2.When being provided with like this, second pair just has with main basically to essentially identical bias condition.
A pair of programmable current source 20 links to each other with 22 provides electric current I 1 and I2 with the grid to MN3 and MN4 respectively.Electric current I 1 and I2 are adjusted to the differential voltage that produces expection on MN3 and MN4, and this causes MN3 and MN4 to conduct fine-adjusting current I respectively
Trim1And I
Trim2Subsequently, fine-adjusting current I
Trim1And I
Trim2Be coupled with the drain electrode of MN3 and MN4, thus with I
Trim1And I
Trim2Inject I respectively
Out1And I
Out2Programmable current source 20 and 22 is adjusted to and reduces main centering because of the voltage offset error that threshold mismatch produced between MN1 and the MN2.
Suppose that it is R that R1 and R2 have resistance separately, and electric current I 1=I2=I
t, differential trim I then
Trim1-I
Trim2Can provide by following formula:
I
trim1-I
trim2＝2*I
t*R*gm
2
In the formula: gm
2It is the mutual conductance of second couple of transistor MN3 and MN4.This second couple produces main right input Associativeoffsets voltage V
Off, as follows:
V
off＝(2*I
t*R*gm
2)/gm
1
In the formula: gm
1It is the mutual conductance of main differential pair.In this way, reduce or eliminate the needed V of the voltage offset error that is produced because of threshold mismatch to provide by regulating programmable current source 20 and 22
OffVoltage, just the bias voltage of acquisition expection reduces.
See V as above
OffWith 2*I
t* R is proportional.Because threshold mismatch and temperature are irrelevant substantially, thus the level of fixed charge and doping depended on, if make I
t* R keeps constant with temperature, thereby then the threshold mismatch component of biased error just can be zero acquisition high accuracy.This fine setting can keep on temperature and input common mode voltage.For example, can equal band gap voltage and form temperature independent I by forming band gap voltage and making reference current flow through the voltage of resistor on resistor
t* R.Subsequently, the mapping reference electric current is to produce electric current I 1 and I2.Note, perhaps, can make I
t* R has the desired temperatures characteristic.
Note, can provide output current I by the drain electrode of electric current being injected MN1/MN2
Out1And I
Out2Common mode component; These electric currents can be provided by all current sources 23 and 24 as shown in Figure 2, perhaps can be by I
Out1And I
Out2The level that is driven provides.This guarantees differential trim only to occur in the drain electrode of MN1 and MN2.The also available PMOS transistor of these current sources is realized.Perhaps, these current sources also can converge in the main right load.
Another of trimming circuit that is used to reduce the caused voltage offset error of threshold mismatch realized as shown in Figure 3.Main to MN1 and MN2 and the second differential pair MN3 and MN4 realization as above.In addition, also increased continuous sky, put on V with reception to transistor MN5 and MN6
-And V
+The difference input voltage, and make its source electrode be connected to common node 30.The size of MN5 and MN6 (m*X) and (by current source 32) put on bias condition that the bias current (m*I) of common node 30 is selected as MN5 and MN6 roughly with main identical to the bias condition of MN1 and MN2, thereby the source voltage of MN5/MN6 is followed the tracks of the source voltage of MN1/MN2.
Diode circuit, the FET MN7 that connects of diode preferably can be connected to common node 30 and be biased to the current density that flows through MN7 with current source 33 and approximates the current density that flows through MN1-MN6; This just causes voltage V
dGeneration, this voltage V
dIt is the diode drop on the common node 30.Then, voltage V
dBe connected to the common node 18 of resistor R 1 and R2, be used to compensate the voltage on second pair the common node 14, make it to approximate main voltage (this is to guarantee by the current density that MN7, MN3 and MN4 suitably are set) common node 10.In this embodiment, programmable current source 34 and 36 is connected between the grid and circuit common of MN3 and MN4.I1 and I2 produce differential voltage on R1 and R2, thereby make MN3 and MN4 with fine-adjusting current I
Trim1And I
Trim2Inject output current I respectively
Out1And I
Out2As previously mentioned, reduce or eliminates to provide by regulating programmable current source 34 and 36 owing to leading the fine-adjusting current I required to the caused biased error of the threshold mismatch between the transistor
Trim1And I
Trim2, just the bias voltage that can obtain to expect reduces.Note, just can provide output current I by the drain electrode of electric current being injected MN1/MN2
Out1And I
Out2Common mode component; These electric currents also can be provided by current source for example shown in Figure 3 37 and 38, perhaps also can be by I
Out1And I
Out2The level that is driven provides.
The another kind that has used slightly different servo loops to reduce the trimming circuit of the caused biased error of threshold mismatch may be realized as shown in Figure 4.Main to MN1 and MN2, the second couple of MN3 and MN4 with virtual MN5 and MN6 can be realized and setover as described above.Transistor MN5, MN6 and MN7 are revealed as the input of the amplifier that MN5-MN7, MP1-MP4, MN8 and MN9 constitute.Amplifier adopts the biasing of single feedback, keeps the necessary voltage of current balance type between MN5/MN6 and the MN7 thereby force the grid of MN7 to reach.Then, this grid voltage (V
d) be used to setover MN3 and MN4, thereby cause the source voltage of MN3/MN4 to approximate the source voltage of MN1/MN2.As shown in Figure 3, reduce or eliminates to provide by regulating programmable current source 34 and 36 owing to lead to the necessary fine-adjusting current I of the caused biased error of the threshold mismatch between the transistor
Trim1And I
Trim2, just the bias voltage that can obtain to expect reduces.This biasing approximates drain electrode-source voltage of MN1-MN7 by making its drain electrode-source voltage, just can make the current density that flows through MN7 mate the current density that flows through MN1-MN6 more accurately.
Another source of bias voltage error is owing to input stage " β " mismatch.When using in this article, the β mismatch may be defined to the difference on the increase and decrease multiple between two transistors.This can be the result of the difference of the difference of difference, mobility of for example length or width and/or oxide thickness.Main proportional with main right tail current to verified its difference drain current of a small amount of β mismatch between the transistor.The present invention reduces because of the caused bias voltage error of β mismatch by injecting main right drain electrode with the proportional fine-adjusting current difference of average drain current ground.
A kind of circuit of this purpose of realizing is shown in Fig. 5 a.The master setovers with the bias current that equals n*I to MN1 and MN2.The second differential pair MN10/MN11 can link to each other to receive the difference input voltage and to use the bias current I from current source 40 to setover.The size of MN10 and MN11 (1*x) becomes the ratio that equals bias current I and bias current n*I with the ratio of the size (n*x) of MN1 and MN2.When biasing like this, second pair just has with main essentially identical bias condition.
The drain electrode of MN10 and MN11 is connected to common node 42 together, makes MN10/MN11 conduct the reference current I with the right proportional variation of average drain current of master
RefReference current I
RefBe provided for the reference current input of digital to analog converter (DAC), this is provided in corresponding current output terminal and produces fine-adjusting current I
Trim1And I
Trim2, and this fine-adjusting current is along with I
RefChange and increase and decrease in proportion according to the numerical value that puts on the DAC digital input end.Fine-adjusting current and corresponding master are coupled to drain current.
When configuration like this, reference current I
Ref, and fine-adjusting current I
Trim1And I
Trim2All change along with main right average drain current.Fine setting DAC 44 increases and decreases into fine-adjusting current I in proportion with this electric current
Trim1And I
Trim2Can reduce main centering because of leading to the caused voltage offset error of mismatch between transistorized " β " value.Fine-adjusting current I
Trim1And I
Trim2All change, can obtain more high-precision fine setting thereby compare with some other prior art scheme along with input common mode voltage.
A kind of current source 12 and 40 may realize shown in Fig. 5 b.At this, bias current sources 12 usefulness transistor MN12 realize that bias current sources 40 then realizes with transistor MN13.In order to obtain above-mentioned ratio, the size of MN13 is 1 with respect to MN12: n.Notice that bias current sources 12 and 40 all realizes with cascade transistor separately usually, rather than adopts the single transistor shown in Fig. 5 b to realize.
Another of bias voltage error may be originated and because of main mismatch between the transistorized body factors (being commonly referred to " γ " mismatch) be caused.This error is general and common-mode voltage is linear.For above-mentioned biased error source, the present invention is different from other biasing generation mechanism ground fine setting " γ " mismatch separately.This is by producing along with realizing with respect to the reference current of the supply voltage of ground connection (perhaps, for PMOS to being the supply voltage with respect to VDD) linear change (perhaps with additive constant (being ax+b), other place then with subtracting each other the constant linear change).Then, will inject main right drain electrode with the proportional current-differencing of reference current ground, thereby realize fine setting.
A kind ofly realize may realizing as shown in Figure 6 of above-mentioned purpose.γ fine setting reference current generating 50 comprises differential pair MN13 and MN14, makes its drain electrode be connected to node 52 together and make its source electrode be connected to node 54 together; Node 54 is connected to circuit common via resistor R 3.MN13 and MN14 receive the difference input voltage, and conduction and second couple input common mode voltage (V in response
Cm) proportional electric current I
Ref, this second couple's input common mode voltage (V
Cm) change along with main right input common mode voltage again.Fine setting DAC 56 receives I
RefAnd at corresponding current output terminal generation electric current I 1 and I2, wherein electric current I 1 and I2 change along with reference current, also increase and decrease in proportion according to the numerical value that puts on the digital input end of DAC.
In Fig. 6, come the electric current I 1 of self trim DAC 56 and I2 can offer MN15/MN16.Notice that I1 and I2 also can offer the differential pair that is used to finely tune threshold mismatch selectively, for example, Fig. 3 and MN3/MN4 shown in Figure 4 have eliminated the independent a pair of needs to for example MN15/MN16 that is exclusively used in the γ mismatch thus.This class configuration as shown in figure 10.Another possibility embodiment of γ fine setting reference current generating 50 as shown in Figure 7.At this, differential pair MN17/MN18 links to each other to receive the difference input voltage its grid, makes its source electrode be connected to node 70 together, and makes its drain electrode be connected to node 72 together; Bias current sources 74 and resistor R 6 are connected between node 70 and the circuit common.Current source 74 can improve precision, uses this current source 74 that the current density of MN17/MN18 and MN1/MN2 are complementary.Differential pair MN19/MN20 links to each other to receive the difference input voltage its grid, makes its source electrode be connected to node 76 together, and makes its drain electrode be connected to node 78 together; Bias current sources 80 is connected between node 76 and the circuit common.MN17/MN18 and MN19/MN20 are with corresponding electric current I
XAnd I
YBe transmitted to current subtraction device 80, this current subtraction device 80 carries out (I
X-I
YThe calculating of)/2 flows to the reference current I of fine setting DAC 56 with generation
RefProduce I
XAnd I
YBe by making the byproduct of MN17/MN18 biasing, carry out subtraction and be used for the eliminate bias electric current.Scheme as shown in Figure 6 and Figure 7 provides effectively finely tunes the simple of γ mismatch.Note, also can and change most of source voltage and adopt other accurate more and complicated more γ mismatch trimming scheme based on fixed common mode voltage.
When main differential pair drives active load, the transistor of forming active load can be the another source of bias voltage error.This error can be because threshold mismatch and/or β mismatch between the active load transistor are caused, thereby this can produce unequal drain current can cause biased error when being reflected to amplifier input terminal.A kind of possible circuit that is used to proofread and correct the threshold mismatch between the active load transistor as shown in Figure 8.At this, the main active load that driving is made up of transistor MP5 and MP6 to MN1/MN2, each transistor bias voltage V
B1Biasing.A pair of PMOS FET MP7 setovers as active load transistor MP5 and MP6 with MP8, and wherein its source electrode links to each other so that voltage VDD to be provided, and its grid is connected to bias voltage V via respective resistors
B2, bias voltage V wherein
B2Preferably but might not with V
B1Identical.The grid of MP7 and MP8 also is connected to corresponding programmable current source 90 and 92, and they provide electric current I 1 and I2 respectively, makes it to produce on MP7 and MP8 the differential voltage of expection.In response to I1 and I2, MP7 and MP8 conduct corresponding fine-adjusting current I
Trim1And I
Trim2, these fine-adjusting currents are injected into main right drain electrode.Can regulate programmable current source 90 and 92 as required and be complementary with the drain current with MP5 and MP6, reducing thus may be by the caused voltage offset error of leading between the right active load transistor of threshold mismatch.
The possible circuit of the β mismatch between a kind of transistor that is used to finely tune active load as shown in Figure 9.PMOSFET MP9 as the active load transistor setover and conduction reference current I
Ref Fine setting DAC 100 receives I at its reference current input
RefAnd at corresponding current output terminal generation fine-adjusting current I
Trim1And I
Trim2, wherein this fine-adjusting current change along with reference current and, and increase and decrease in proportion according to the numerical value that puts on the DAC digital input end.Fine-adjusting current is coupled to output current with corresponding main, and can regulate DAC 100 as required and be complementary with the drain current with MP5 and MP6, reduces thus otherwise may be because of the caused voltage offset error of β mismatch between the main right active load transistor.
Some kinds of trimming circuits discussed in this article can adopt simultaneously, and to reduce the voltage offset error of differential pair, wherein each trimming circuit fine setting is by the V of particular source generation
OSError.This as shown in figure 10.At this, as previously mentioned, main to MN1/MN2 conduction output current I
Out1And I
Out2, this master is to generally being connected to gain stage (as shown in figure 10) or output stage.Can reduce because of the caused voltage offset error of the threshold mismatch between MN1 and the MN2 with being similar to circuit shown in Figure 4 110.Can regulate programmable current source 34 and 36 as required, to reduce because of the caused voltage offset error of the threshold mismatch between MN1 and the MN2.
The γ mismatch can be solved by circuit 112, and this circuit 112 is similar to Fig. 6 and circuit shown in Figure 7.At this, can regulate the numeral input of fine setting DAC 56 as required, to reduce because of the caused voltage offset error of γ mismatch between MN1 and the MN2.
Finely tuned by the β mismatch available circuit 114 between the transistor (as transistor MP10 and the MP11 among Fig. 1) of the active load that MN1 and MN2 drove, this circuit 114 is similar to circuit shown in Figure 9.At this, can regulate the numeral input of fine setting DAC 100 as required, to reduce because of the caused voltage offset error of β mismatch between MP10 and the MP11.
Also can adopt the circuit of the threshold mismatch between the β mismatch that is used to finely tune between MN1 and the MN2 (for example, the transistor shown in Fig. 5 a and the 5b) and MP10 and the MP11 (for example, shown in Figure 8 transistor) if desired.In fact, can any combination use trimming circuit discussed in this article.The quantity and the type of the circuit that uses depend on concrete application, and wherein the acceptable degree of the offset voltage specification of differential levels and circuit complexity is a principal element.
Notice that it only is exemplary that trimming circuit discussed above is realized; Each of the circuit of discussing can various method realize.Important only is that each trimming circuit can be used to reduce because of the caused bias voltage error of a particular source.
Though specific embodiment of the present invention illustrates and is described, to those skilled in the art, can make many different variants and optional embodiment.Therefore, the present invention is intended to only be subjected to the restriction of claims.
Claims (33)
1. differential levels comprises:
Main difference transistor is right, and it is biased in response to the difference input voltage conducts corresponding output current;
Second difference transistor is right;
Circuit, it with described second difference transistor to linking to each other and being arranged such that described second pair input common mode voltage approximates the right input common mode voltage of described master; And
First and second programmable current sources, be configured to described second difference transistor on produce the expectation differential voltage, thereby described second pair transistor conducts corresponding fine-adjusting current, described fine-adjusting current and corresponding described output current are coupled, and described first and second programmable current sources are programmed to described fine-adjusting current and reduce in the main differential pair because the right transistor of described master has the caused voltage offset error of threshold voltage of mismatch.
2. differential levels comprises:
Main differential pair comprises first and second transistors, and each transistor has the control input end and first and second current terminals, and described second current terminal links together at first node;
Be connected to first bias current sources of described first node, described first bias current sources provides first bias current to described main differential pair, make described first and second transient response conduct corresponding output current in the difference input voltage that puts on its control input end at its first current terminal, described first differential pair has the input common mode voltage that is associated;
Second differential pair comprises third and fourth transistor, and each transistor all has the control input end and first and second current terminals, and described second current terminal links together at second node;
Second bias current sources, it connects into to described second differential pair second bias current is provided;
Circuit, it links to each other with described second differential pair, and is configured to make the input common mode voltage of described second differential pair to approximate the right input common mode voltage of described master; And,
First and second trim currents sources, it is configured to provide corresponding electric current I 1 and I2 to the described third and fourth transistorized control input end respectively, thereby on described second differential pair, produce the expectation differential voltage, make described third and fourth transistor conduct corresponding fine-adjusting current I
Trim1And I
Trim2, described fine-adjusting current and corresponding described output current are coupled.
3. input stage as claimed in claim 2 is characterized in that, the ratio between described first and second bias currents approximates the ratio between the described first and second transistorized sizes difference described relatively third and fourth transistorized sizes.
4. input stage as claimed in claim 2 is characterized in that, described circuit comprises:
First and second resistors, they are connected in series between the described third and fourth transistorized control input end, and the tie point of described first and second resistors is the 3rd nodes; And,
Servomechanism makes its input be connected to described first and second nodes, and makes its output be connected to described the 3rd node, thereby the voltage on described second node is compensated into about the voltage that equals on described first node.
5. input stage as claimed in claim 4 is characterized in that, described first and second resistors have resistance R separately, and described electric current I 1=I2=I
t, make differential trim I
Trim1-I
Trim2Be approximately:
I
trim1-I
trim2＝2*I
t*R*gm
2，
In the formula: gm
2Be the mutual conductance of second differential pair, and described second differential pair produce the right input-reference bias voltage V of described master
Off:
V
off＝2*I
t*R*gm
2/gm
1
In the formula: gm
1It is the mutual conductance of main differential pair.
6. input stage as claimed in claim 5 is characterized in that, described resistor and described trim currents sources are configured to I
t* R is with the temperature constant.
7. input stage as claimed in claim 5 is characterized in that, described resistor and described trim currents sources are configured to I
t* R has the preferred temperature characteristic.
8. input stage as claimed in claim 6 is characterized in that, described trim currents sources comprises:
At least one band-gap voltage source, it produces band gap voltage; And
Respective resistors, described band gap voltage are connected each resistor two ends of described resistor, to produce described electric current I 1 and I2.
9. input stage as claimed in claim 2 is characterized in that, the described main differential pair and second differential pair all are MOSFET.
10. input stage as claimed in claim 9, it is characterized in that, described first and second trim currents sources all are programmable current sources, described first and second trim currents sources can be programmed, thereby significantly reduce in the described main differential pair because the caused voltage offset error of threshold voltage that described first and second transistors have mismatch to produce fine-adjusting current I1 and I2.
11. input stage as claimed in claim 2 is characterized in that, the described main differential pair and second differential pair all are bipolar transistors.
12. input stage as claimed in claim 2 is characterized in that, described circuit comprises:
Virtual differential pair comprises the 5th and the 6th transistor, and each transistor has the control input end and first and second current terminals, and described control input end connects into and receives described difference input voltage, and described second current terminal links together on the 3rd node;
Be connected to the 3rd bias current sources of described the 3rd node, described the 3rd bias current sources provides the 3rd bias current to described the 3rd differential pair, makes the described the 5th and the 6th transient response conduct corresponding electric current in described difference input voltage at their first current terminal; And,
Diode circuit, one end are connected to described the 3rd node and the other end is connected to the control input end of described second differential pair by respective resistors, thereby the voltage on described second node is compensated into about the voltage that equals on described first node.
13. input stage as claimed in claim 12 is characterized in that, the ratio between the described first and the 3rd bias current approximates the ratio between the described first and second transistorized sizes the described relatively the 5th and the 6th transistorized size.
14. input stage as claimed in claim 13 is characterized in that, described diode circuit comprises:
Be connected with the transistor of diode; And,
Current source, it connects into can provide bias current to the described transistor that is connected with diode, make flow through the described transistorized current density that is connected with diode approximate flow through described master to, described second pair and described virtual right current density.
15. input stage as claimed in claim 2, it is characterized in that, described first trim currents sources is connected between the described the 3rd transistorized control input end and the circuit common, and described second trim currents sources is connected between the described the 4th transistorized control input end and the circuit common.
16. input stage as claimed in claim 2 is characterized in that, also comprises third and fourth current source, they are connected respectively to described first and second transistorized first ends, and are configured to provide the common mode component of described output current.
17. input stage as claimed in claim 2 is characterized in that, described circuit comprises:
Virtual differential pair, comprise the 5th and the 6th transistor, each transistor has the control input end and first and second current terminals, described control input end connects into and receives described difference input voltage, described second current terminal links together at the 3rd node, and described first current terminal links together at the 4th node;
Be connected to the 3rd bias current sources of described the 3rd node, the 3rd bias current sources provides the 3rd bias current to described the 3rd differential pair, makes the described the 5th and the 6th transient response conduct respective electrical stream in described difference input voltage on its first end;
The the 7th and the 8th transistor, they have the control input end and first and second current terminals separately, and described first and second current terminals are connected between supply voltage and the 5th and the 6th node;
The the 9th and the tenth transistor, they have the control input end and first and second current terminals separately, and described first and second current terminals are connected between the described the 5th and the 6th node and the 7th and the 8th node;
The 11 transistor, it has the control input end and first and second current terminals, and described the 11 transistor is connected between described the 7th node and the circuit common with the diode connected mode;
The tenth two-transistor, it has the control input end and first and second current terminals, and described first and second current terminals are connected between described the 8th node and the described circuit common;
The the described the 7th and the 8th transistorized control input end is connected to first bias voltage;
The the described the 9th and the tenth transistorized control input end is connected to second bias voltage;
The described the 11 and the control input end of the tenth two-transistor link together; And
The 13 transistor, it has the control input end and first and second current terminals, and described first and second current terminals are connected between described the 6th node and described the 3rd node, and described control input end is connected to described the 8th node;
Described the 8th node is connected to the control input end of described second differential pair by respective resistors, makes that the voltage on described second node is compensated into about the voltage that equals on described first node.
18. a differential input stage comprises:
Main differential pair comprises first and second transistors, and each transistor has the control input end and first and second current terminals, and described second current terminal links together at first node, and described control input end connects into and receives the difference input voltage;
Be connected to first current source of described first node, described first current source provides first bias current to described main differential pair, makes described first and second transient response conduct corresponding output current in the difference input voltage that puts on its control input end on its first current terminal;
Second differential pair, comprise third and fourth transistor, each transistor all has the control input end and first and second current terminals, described second current terminal links together at second node, and described first current terminal links together at the 3rd node, and described second pair control input end connects into and receives described difference input voltage;
Be connected to second bias current sources of described second node, it is connected to described second node, described second bias current sources provides second bias current to described second differential pair, make described third and fourth transient response conduct corresponding output current at its first current terminal in described difference input voltage, ratio between wherein said second and first bias current is roughly 1: N, and being approximately 1 at the ratio of the described relatively first and second transistorized sizes of the described third and fourth transistorized size: N makes that the right average drain current of described second pair output current and described master is proportional; And,
Digital to analog converter (DAC), it is connected to described the 3rd node at the reference current input, and is biased at corresponding current output terminal generation fine-adjusting current I
Trim1And I
Trim2Described fine-adjusting current is along with the electric current and the right average drain current of described master of described the 3rd node change and increase and decrease in proportion according to the numerical value that puts on described DAC digital input end, the corresponding output current that described fine-adjusting current and described master are right is coupled, and described DAC is programmed to reduce in described main differential pair because the caused voltage offset error of mismatch between the described first and second transistorized β values.
19. input stage as claimed in claim 18, it is characterized in that, described first current source comprises the 5th transistor, it has the control input end and first and second current terminals, described control input end is connected to bias voltage, and described first current terminal is connected to described first node, makes described the 5th transistor conduct described first bias current; And,
The 6th transistor, it has the control input end and first and second current terminals, and described control input end is connected to described bias voltage, and described first current terminal is connected to described second node, makes described the 6th transistor flow through described second bias current;
The ratio of the described the 6th transistorized size and described the 5th transistorized size is about 1: N.
20. a differential input stage comprises:
Main differential pair comprises first and second transistors, and each transistor has the control input end and first and second current terminals, and described second current terminal links together at first node, and described control input end connects into and receives the difference input voltage;
Be connected to first current source of described first node, described first current source provides first bias current to described main differential pair, makes described first and second transient response conduct corresponding output current in the difference input voltage that puts on its control input end on its first current terminal;
Circuit, it receives described difference input voltage and is configured to produce reference current, and described reference current changes linearly along with described grade source voltage with respect to ground connection or additional constant changes linearly;
Digital to analog converter (DAC), connect at the reference current input and receive described reference current and be biased to and can produce electric current I 1 and I2 at corresponding current output terminal, described electric current changes and increases and decreases in proportion according to the numerical value by the digital input end that puts on described DAC along with described reference current;
Second differential pair, comprise third and fourth transistor, each transistor all has the control input end and first and second current terminals, the second described second pair current terminal links together and its control input end is connected respectively to electric current I 1 and I2 at second node, and is connected to the voltage that changes along with the right common-mode voltage of described master by respective resistors; And
Be connected to second bias current sources of described second node, described bias current sources provides second bias current to described second differential pair, make described third and fourth transistor conduct corresponding fine-adjusting current at its first current terminal, the corresponding output current that described fine-adjusting current and described master are right is coupled, and described DAC is programmed to and reduces because the caused voltage offset error of γ mismatch between described first and second transistors.
21. input stage as claimed in claim 20 is characterized in that, described circuit comprises:
The 3rd differential pair, comprise the 5th and the 6th transistor, each transistor all has the control input end and first and second current terminals, second described the 3rd pair current terminal links together at the 3rd node, its first current terminal links together at the 4th node, and its control input end connects into the described difference input voltage of reception; And
Be connected to the circuit element of described the 3rd node, described circuit element provides the 3rd bias current to described the 3rd differential pair, make the described the 5th and the 6th transient response conduct corresponding output current at its first current terminal in described difference input voltage, thereby on described the 4th node, produce described reference current, described the 3rd pair and described circuit element are configured to described reference current along with the source voltage with respect to the described level of ground connection changes linearly, and a perhaps additional constant changes linearly.
22. input stage as claimed in claim 21 is characterized in that, described circuit element is the resistor that is connected between described the 3rd node and the circuit common.
23. input stage as claimed in claim 20 is characterized in that, described circuit comprises:
The 3rd differential pair, comprise the 5th and the 6th transistor, each transistor all has the control input end and first and second current terminals, second described the 3rd pair current terminal links together at the 3rd node, its first current terminal links together at the 4th node, and its control input end connects into the described difference input voltage of reception; And
The 3rd bias current sources, it is connected to described the 3rd node and provides the 3rd bias current to described the 3rd differential pair, make the described the 5th and the 6th transient response conduct corresponding output current at its first current terminal, thereby on described the 4th node, produce electric current I in described difference input voltage
y
The 4th differential pair, comprise the 7th and the 8th transistor, each transistor all has the control input end and first and second current terminals, second described the 4th pair current terminal links together at the 5th node, its first current terminal links together at the 6th node, and its control input end connects into the described difference input voltage of reception;
The 4th bias current sources and be connected in resistor between described the 5th node and the circuit common in parallel, provide the 4th bias current to described the 4th differential pair, make the described the 7th and the 8th transient response conduct corresponding output current at its first current terminal, thereby on described the 6th node, produce electric current I in described difference input voltage
xAnd
Current subtraction device circuit, it produces along with I
x-I
yThe output that changes, described subtracter output is described reference current, described third and fourth pair is configured to described reference current along with the source voltage with respect to the described level of ground connection changes linearly with described third and fourth bias current sources and described resistor, and a perhaps additional constant changes linearly.
24. a differential input stage comprises:
Main differential pair comprises first and second transistors, and each transistor has the control input end and first and second current terminals, and described second current terminal links together at first node, and described control input end connects into and receives the difference input voltage;
Be connected to first current source of described first node, provide first bias current, make described first and second transient response conduct corresponding output current at its first current terminal in the difference input voltage that puts on its control input end to described main differential pair;
Active load comprises with series system being connected third and fourth transistor between supply voltage and described first and second transistors that the transistor of described active load makes them can conduct described output current with the bias voltage biasing;
Second differential pair comprises the 5th and the 6th transistor, and each transistor all has the control input end and first and second current terminals, and described second current terminal links together at second node;
First and second resistors are connected between the described the 5th and the 6th transistorized control input end with series system, and the tie point of described first and second resistors is the 3rd nodes, and described the 3rd node and described bias voltage are coupled; And
First and second programmable current sources, they are configured to provide corresponding electric current I 1 and I2 to the described the 5th and the 6th transistorized control input end respectively, on described second differential pair, produce the expectation differential voltage, make the described the 5th and the 6th transistor conduct corresponding fine-adjusting current I
Trim1And I
Trim2Described fine-adjusting current and corresponding described output current are coupled, described first and second trim currents sources are programmed fine-adjusting current I1 and the I2 that is complementary with the electric current that produces and described third and fourth transistor is conducted, thereby reduce in the described main differential pair because the active load transistor has the caused voltage offset error of mismatch threshold voltage.
25. a differential input stage comprises:
Main differential pair comprises first and second transistors, and each transistor has the control input end and first and second current terminals, and described second current terminal links together at first node, and described control input end connects into and receives the difference input voltage;
Be connected to first current source of described first node, described first current source provides first bias current to described main differential pair, makes described first and second transient response conduct corresponding output current in the difference input voltage that puts on its control input end at its first current terminal;
Active load comprises with series system being connected third and fourth transistor between supply voltage and described first and second transistors that the transistor of described active load makes them can conduct described output current with the bias voltage biasing;
The 5th transistor, it has the control input end and first and second current terminals, described first end is connected to described supply voltage, and described control input end is connected to described bias voltage, makes described the 3rd transistor setover as described active load transistor and conducts the reference current that changes along with described bias voltage;
Digital to analog converter (DAC), it connects into to receive described reference current and be configured at the reference current input and produces first and second fine-adjusting currents at corresponding current output terminal, and described electric current changes along with described reference current and increases and decreases in proportion according to the numerical value of the digital input end that puts on described DAC;
The corresponding output current that described fine-adjusting current and described master are right is coupled, described DAC is programmed to and can mates the electric current that described third and fourth transistor is conducted, thereby reduces in the described main differential pair because the caused voltage offset error of β mismatch between described third and fourth transistor.
26. a differential input stage comprises:
Main differential pair comprises first and second transistors and setovering with first bias current, makes described master to conducting corresponding output current in response to the difference input voltage;
At least one voltage offset trim circuitry, described at least one voltage offset trim circuitry comprises:
Trimming circuit is adjusted to and reduces in the described main differential pair because the caused voltage offset error of mismatch between the described first and second transistorized threshold voltages, and described trimming circuit also comprises except that described main differential pair:
Second difference transistor is right;
Circuit, it is right that it is connected to described main difference transistor, and be configured to make described second pair input common mode voltage to approximate the right input common mode voltage of described master; And
First and second programmable current sources, they connect into described second difference transistor on produce the expectation differential voltage, make described second pair transistor conduct corresponding fine-adjusting current, described fine-adjusting current and corresponding described output current are coupled, described first and second programmable current sources are programmed, and make described fine-adjusting current significantly reduce in the described main differential pair because the master has the caused voltage offset error of mismatch threshold voltage to transistor; And/or
Trimming circuit is adjusted to and reduces in the described main differential pair because described first and second the caused voltage offset error of β mismatch between transistorized, and described trimming circuit also comprises except that described main differential pair:
Second difference transistor is right, it is setovered with second bias current, make described second pair in response to described difference input voltage conduction corresponding output current, wherein, ratio between described second and first bias current is about 1: N, and described master is about 1 to the ratio between the described relatively respectively second pair of transistorized size of transistorized size: N, thus make that the right average drain current of described second pair output current and described master is proportional; And
Digital to analog converter (DAC), it connects at the reference current input and receives described second pair output current and constitute and can produce fine-adjusting current at each current output terminal, described fine-adjusting current is along with described second pair output current and the right average drain current of described master and change, and the numerical value according to the digital input end that puts on described DAC increases and decreases in proportion, the corresponding output current that described fine-adjusting current and described master are right is coupled, and described DAC is programmed to reduce in the described main differential pair owing to the caused voltage offset error of β mismatch between described master is to transistor; And/or trimming circuit, can be adjusted to and reduce in the described main differential pair because described first and second the caused voltage offset error of γ mismatch between transistorized, described trimming circuit also comprises except that described main differential pair:
Circuit is used to receive described difference input voltage and is configured to produce reference current, and described reference current is along with the source voltage with respect to the described level of ground connection changes linearly, and a perhaps additional constant changes linearly;
Digital to analog converter (DAC), it connects at the reference current input and receives described reference current, and be configured to produce electric current I 1 and I2 at corresponding current output terminal, described electric current changes along with described reference current, and increases and decreases in proportion according to the numerical value of the digital input end that puts on described DAC; And,
Second difference transistor is right, be used for received current I1 and I2 and be biased to conducting corresponding fine-adjusting current in response, the corresponding output current that described fine-adjusting current and described master are right is coupled, described DAC be programmed to reduce in the described main differential pair since described master to the caused voltage offset error of γ mismatch between the transistor; And/or
Trimming circuit can be adjusted to and reduces in the described main differential pair because the caused voltage offset error of threshold mismatch between the active load transistor that described main differential pair drove, and described trimming circuit also comprises except that described main differential pair:
Active load comprises with series system being connected to third and fourth transistor between supply voltage and described first and second transistors that described active transistor is biased to bias voltage and makes it conduct described output current;
Second differential pair, it comprises the 5th and the 6th transistor and setovers with described bias voltage; And
First and second programmable current sources, they are configured to provide corresponding electric current I1 and I2 to the described the 5th and the 6th transistor respectively, thereby on described second differential pair, produce needed differential voltage, make the described the 5th and the 6th transistor conduct corresponding fine-adjusting current, described fine-adjusting current and corresponding described output current are coupled, described first and second programmable current sources are programmed fine-adjusting current I1 and the I2 that is complementary with the electric current that produces and described third and fourth transistor is conducted, and therefore reduce in the described main differential pair because the active load transistor has the caused voltage offset error of mismatch threshold voltage; And/or
Trimming circuit can be adjusted to and reduces in the described main differential pair because the caused voltage offset error of β mismatch between the active load transistor that described main differential pair drove, and described trimming circuit also comprises except that described main differential pair:
Active load comprises with series system being connected to third and fourth transistor between supply voltage and described first and second transistors that described active transistor is biased to bias voltage and makes it conduct described output current;
The 5th transistor, it is connected to described supply voltage and described bias voltage, makes described the 5th transistor setover as described active load transistor, and conducts the reference current that changes with described bias voltage;
Digital to analog converter (DAC), it connects at the reference current input and receives described reference current, and be configured to produce first and second fine-adjusting currents at each current output terminal, described electric current changes along with described reference current, and increases and decreases in proportion according to the numerical value of the digital input end that puts on described DAC;
The corresponding output current that described fine-adjusting current and described master are right is coupled, described DAC is programmed to mate the electric current that described third and fourth transistor is conducted, and therefore reduces in the described main differential pair because the caused voltage offset error of β mismatch between described third and fourth transistor.
27. differential input stage as claimed in claim 26, it is characterized in that, regulate that described fine-adjusting current reduces in the described main differential pair because second differential pair of the caused voltage offset error of γ mismatch and regulate described fine-adjusting current and reduce in the described main differential pair because second differential pair of the caused voltage offset error of mismatch between the described first and second transistorized threshold voltages is with a pair of.
28. one kind reduces to comprise owing to be biased to the method for conducting the caused voltage offset error of mismatch between the threshold voltage of main FET differential pair of corresponding output current in response to the difference input voltage:
The 2nd FET differential pair is provided;
Make described second pair input common mode voltage approximate the right input common mode voltage of described master;
Provide first and second programmable currents to described second pair,, make described second couple FET conduct corresponding fine-adjusting current so that on described second pair, produce the expectation differential voltage;
Described fine-adjusting current and corresponding described output current are coupled; And,
Regulate described first and second programmable currents, make described fine-adjusting current reduce in the described main differential pair because described master has the caused voltage offset error of mismatch threshold voltage to transistor.
29. one kind reduces to comprise owing to be biased to the method for conducting the caused voltage offset error of mismatch between the β value of main FET differential pair of corresponding output current in response to the difference input voltage:
The 2nd FET differential pair is provided, and it is configured to make described second pair to conduct corresponding output current in response to described difference input voltage, and the right average drain current of described second pair output current and described master is proportional;
Produce fine-adjusting current I
Trim1And I
Trim2, described fine-adjusting current changes along with described second pair output current, and therefore changes along with the right average drain current of described master;
The size of described fine-adjusting current is increased and decreased in proportion with user-programmable value;
Right corresponding output current is coupled to make described fine-adjusting current and described master; And regulate described user-programmable value, make described fine-adjusting current reduce in the described main differential pair because described master has the caused voltage offset error of mismatch β value to transistor.
30. one kind reduces to comprise owing to be biased to the method for conducting the caused voltage offset error of mismatch between the γ numerical value of main FET differential pair of corresponding output current in response to the difference input voltage:
Produce reference current, described reference current is along with respect to the source voltage of the described level of ground connection and a linear variation or an additional constant changes linearly;
Electric current I 1 and I2 that generation changes with described reference current;
The size of described electric current I 1 and I2 is increased and decreased in proportion with user-programmable value;
Received current I1 and I2 are provided and are biased to the 2nd FET differential pair that conducts corresponding fine-adjusting current in response;
Right corresponding output current is coupled to make described fine-adjusting current and described master; And
Regulate described user-programmable value, make described fine-adjusting current reduce in the described main differential pair because described master has the caused voltage offset error of mismatch γ numerical value to transistor.
31. one kind reduces owing to bias voltage biasing and by being biased to the method for conducting the caused voltage offset error of mismatch between the threshold voltage of FET active load of main FET differential pair drives of corresponding output current in response to the difference input voltage, comprising:
The 2nd FET differential pair with described bias voltage biasing is provided;
Provide first and second programmable currents to described second pair,, make described second couple FET conduct corresponding fine-adjusting current so that on described second pair, produce the expectation differential voltage;
Described fine-adjusting current and corresponding described output current are coupled;
Regulate described first and second programmable currents, make the drain current of described fine-adjusting current and described active load FET be complementary, thereby reduce in described main differential pair because the active load transistor has the caused voltage offset error of mismatch threshold voltage.
32. one kind reduces owing to bias voltage biasing and be biased to the method for conducting the caused voltage offset error of mismatch between the threshold voltage of FET active load of main FET differential pair drives of corresponding output current in response to the difference input voltage, comprising:
Come bias transistor with described bias voltage, make its conduct the reference current that changes along with described bias voltage;
The fine-adjusting current I that generation changes along with described reference current
Trim1And I
Trim2
The size of described fine-adjusting current is increased and decreased in proportion with user-programmable value;
Make right corresponding being coupled of output current of described fine-adjusting current and described master; And,
Regulate described user-programmable value, make the drain current of described fine-adjusting current and described active load FET be complementary, thereby reduce in the described main differential pair because the active load transistor has the caused voltage offset error of mismatch β value.
33. one kind reduces to be biased to the method for voltage offset error of conducting the main FET differential pair of corresponding output current in response to the difference input voltage, comprising:
Regulate the fine-adjusting current able to programme that a pair of and corresponding described output current is coupled, to reduce in the described main differential pair because described master has the caused voltage offset error of mismatch threshold voltage to transistor; And/or
Regulate the fine-adjusting current able to programme that a pair of and corresponding described output current is coupled, to reduce in the described main differential pair because described master has the caused voltage offset error of mismatch β value to transistor; And/or
Regulate the fine-adjusting current able to programme that a pair of and corresponding described output current is coupled, to reduce in the described main differential pair because described master has the caused voltage offset error of mismatch γ value to transistor; And/or
Regulate the fine-adjusting current able to programme that a pair of and corresponding described output current is coupled, to reduce in the described main differential pair because described master has the caused voltage offset error of mismatch threshold voltage to the active load transistor that drives; And/or
Regulate the fine-adjusting current able to programme that a pair of and corresponding described output current is coupled, to reduce in the described main differential pair because described master has the caused voltage offset error of mismatch β value to the active load transistor that drives.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US55840104P | 2004-03-31 | 2004-03-31 | |
| US60/558,401 | 2004-03-31 | ||
| US10/911,371 | 2004-08-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1957527A true CN1957527A (en) | 2007-05-02 |
| CN100571025C CN100571025C (en) | 2009-12-16 |
Family
ID=38063775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004800431577A Expired - Fee Related CN100571025C (en) | 2004-03-31 | 2004-12-16 | Differential stage voltage offset trimming circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100571025C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104156022A (en) * | 2014-07-25 | 2014-11-19 | 苏州旭创科技有限公司 | Circuit and method for generating bias voltages for avalanche photodiodes and optical module |
| CN105827235A (en) * | 2015-01-22 | 2016-08-03 | 株式会社巨晶片 | Differential output buffer |
| CN105929887A (en) * | 2016-05-18 | 2016-09-07 | 华南理工大学 | Low-power-consumption broad-band current differential circuit |
| CN106059507A (en) * | 2016-05-30 | 2016-10-26 | 矽力杰半导体技术(杭州)有限公司 | D type amplifier and method for suppressing noise of D type amplifier |
| CN106559054A (en) * | 2012-05-24 | 2017-04-05 | 意法半导体研发(深圳)有限公司 | Operation transconductance amplifier with enhanced current sink capability |
| CN106663989A (en) * | 2014-07-10 | 2017-05-10 | 德州仪器公司 | Dual-comparator circuit with dynamic vio shift protection |
| CN108023581A (en) * | 2016-10-28 | 2018-05-11 | 亚德诺半导体集团 | Small area low-power electrification reset circuit |
| CN108702137A (en) * | 2016-03-30 | 2018-10-23 | 德克萨斯仪器股份有限公司 | Common-mode gain for amplifier is finely tuned |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5573114A (en) * | 1978-11-28 | 1980-06-02 | Nippon Gakki Seizo Kk | Output offset control circuit for full step direct-coupled amplifier |
| DE19706985B4 (en) * | 1997-02-21 | 2004-03-18 | Telefonaktiebolaget L M Ericsson (Publ) | Input buffer circuit |
| US6194962B1 (en) * | 1999-04-13 | 2001-02-27 | Analog Devices, Inc. | Adaptive operational amplifier offset voltage trimming system |
| US6310519B1 (en) * | 2000-06-08 | 2001-10-30 | Mitsubishi Electric & Electronics U.S.A., Inc. | Method and apparatus for amplifier output biasing for improved overall temperature stability |
-
2004
- 2004-12-16 CN CNB2004800431577A patent/CN100571025C/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106559054A (en) * | 2012-05-24 | 2017-04-05 | 意法半导体研发(深圳)有限公司 | Operation transconductance amplifier with enhanced current sink capability |
| CN106559054B (en) * | 2012-05-24 | 2019-07-12 | 意法半导体研发(深圳)有限公司 | The operation transconductance amplifier of current sink capability with enhancing |
| CN106663989A (en) * | 2014-07-10 | 2017-05-10 | 德州仪器公司 | Dual-comparator circuit with dynamic vio shift protection |
| CN106663989B (en) * | 2014-07-10 | 2019-05-21 | 德州仪器公司 | Dual comparator circuit with dynamic VIO displacement protection |
| CN104156022A (en) * | 2014-07-25 | 2014-11-19 | 苏州旭创科技有限公司 | Circuit and method for generating bias voltages for avalanche photodiodes and optical module |
| CN105827235A (en) * | 2015-01-22 | 2016-08-03 | 株式会社巨晶片 | Differential output buffer |
| CN108702137A (en) * | 2016-03-30 | 2018-10-23 | 德克萨斯仪器股份有限公司 | Common-mode gain for amplifier is finely tuned |
| CN108702137B (en) * | 2016-03-30 | 2023-06-27 | 德克萨斯仪器股份有限公司 | Common mode gain trimming for an amplifier |
| CN105929887A (en) * | 2016-05-18 | 2016-09-07 | 华南理工大学 | Low-power-consumption broad-band current differential circuit |
| CN106059507A (en) * | 2016-05-30 | 2016-10-26 | 矽力杰半导体技术(杭州)有限公司 | D type amplifier and method for suppressing noise of D type amplifier |
| CN106059507B (en) * | 2016-05-30 | 2019-03-01 | 上海芃矽半导体技术有限公司 | Class-D amplifier and the method for inhibiting class-D amplifier noise |
| CN108023581A (en) * | 2016-10-28 | 2018-05-11 | 亚德诺半导体集团 | Small area low-power electrification reset circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100571025C (en) | 2009-12-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4638481B2 (en) | Differential stage voltage offset trim circuit | |
| US5512848A (en) | Offset comparator with common mode voltage stability | |
| US7973569B1 (en) | Offset calibration and precision hysteresis for a rail-rail comparator with large dynamic range | |
| CN1242548C (en) | Bandgap reference circuit and method | |
| US7525381B2 (en) | Amplifier structures that enhance transient currents and signal swing | |
| US7557659B2 (en) | Slew-enhanced input stages and amplifiers | |
| EP0620515B1 (en) | Band gap reference voltage source | |
| WO2010132108A1 (en) | Operational trans-conductance amplifier with output clamp circuit | |
| JP2002149252A (en) | Band-gap reference circuit | |
| WO2019150744A1 (en) | Correction current output circuit and reference voltage circuit with correction function | |
| US5434538A (en) | Gain enhancement for amplifier using a replica amplifier | |
| CN1957527A (en) | Differential stage voltage offset trimming circuit | |
| CN111601429A (en) | Constant current driving circuit | |
| US5045773A (en) | Current source circuit with constant output | |
| CN206671935U (en) | A kind of bipolar transistor amplifier with input current compensation circuit | |
| US20130169260A1 (en) | Current mirror with low headroom and linear response | |
| US5455539A (en) | Device for regulating the common mode voltage at the output of a balanced amplifier | |
| US5680037A (en) | High accuracy current mirror | |
| US10574200B2 (en) | Transconductance amplifier | |
| JPH0365806A (en) | Operational amplifier having null offset which is adjustable by digital processing | |
| US20210286394A1 (en) | Current reference circuit with current mirror devices having dynamic body biasing | |
| CN1675830A (en) | Operational amplifier | |
| US5334949A (en) | Differential amplifiers | |
| CN2609030Y (en) | Energy gap reference voltage reference circuit | |
| US20210359647A1 (en) | Operational amplifier with indirect current feedback current limiter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: AMERICA ANALOG DEVICE INC. Free format text: FORMER NAME: ANALOG DEVICES, INC. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: Massachusetts, USA Patentee after: ANALOG DEVICES, Inc. Address before: Massachusetts, USA Patentee before: Analog Devices, Inc. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091216 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |