CN1956193A - Buried chip package structure - Google Patents
Buried chip package structure Download PDFInfo
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- CN1956193A CN1956193A CNA2005101184910A CN200510118491A CN1956193A CN 1956193 A CN1956193 A CN 1956193A CN A2005101184910 A CNA2005101184910 A CN A2005101184910A CN 200510118491 A CN200510118491 A CN 200510118491A CN 1956193 A CN1956193 A CN 1956193A
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- package structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
A packaging structure of buried chip consists of the first metal plate, the second metal plate being set with a through opening and being used to a heat radiation base plate together with the first one, at least one semiconductor chip and at least one capacity element of chip type both being connected to the first metal plate and being contained in through hole on the second metal plate, a passive element layer set on top surface of the second metal plate and at least one circuit lamination structure being set on surface of heat radiation base plate and being used to cover semiconductor chip and capacity element of chip type as well as passive element layer.
Description
Technical field
The present invention relates to a kind of buried chip package structure, active and passive component are connected in circuit increase buried chip package structure between layer (build-up layer) structure and the heat-radiating substrate in particular to a kind of.
Background technology
In recent years, flourish along with Internet appliance product and communication product, the capacity of message transmission greatly increases, the signal transmitting speed requires also significantly to improve, under the driving of multi-functional hand-held formula electronic product, semiconductor technology develops unavoidable densification towards high power capacity, narrow linewidth, high frequency, low power consuming, the evolution of multi-functional integration direction simultaneously.
Therefore aspect the IC encapsulation technology, for the high standard that cooperates high I/O number, high heat radiation and package dimension downsizing requires down, make wafer-level package (Chip Scale Package, CSP), (FlipChip FC) waits high-order encapsulation type attitude demand to continue to raise to flip-chip.In addition, the lamination of circuit board (lamination) technology also just must be towards the characteristics development of thin thickness, multilayer number and high wiring density, and in order further to dwindle the space requirement of circuit board, that the surface is provided with the flip-chip chip and as the multilayer circuit board of the passive component of resistor, capacitor and inductor etc. and develop.
Yet the flip-chip chip electrically connects with the line layer that the passive component that is arranged at the multilayer circuit board surface still need see through in the multilayer circuit board, so often because access path is oversize, and influence electrical performance.Therefore, the utilization of multilayer circuit board inner space is to reach the distance of access path between reduced volume, the radiating efficiency that improves chip and shortening and the semiconductor chip, to reach compact, dynamical encapsulating structure, all be to be badly in need of overcoming and the direction that develops.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of buried chip package structure of imbedding active and passive component, to improve aforesaid shortcoming.
For reaching above-mentioned purpose, according to a preferred embodiment of the invention, structure of the present invention includes: one first metallic plate; One second metallic plate is located at the upper surface of this first metallic plate, and this second metallic plate forms at least one opening that runs through, and this second metallic plate and this first metallic plate constitute a heat-radiating substrate; At least one semiconductor chip and at least one chip type capacity cell are connected in this first metal sheet surface respectively, run through in the opening and be contained in formed this of this second metallic plate; One passive component layer is arranged at the part upper surface of this second metallic plate; And at least one circuit layer reinforced structure, be located at this heat-radiating substrate surface and cover this semiconductor chip, this chip type capacity cell and this passive component layer.This circuit layer reinforced structure in the structure wherein of the present invention includes: a dielectric layer; At least one is formed at the line layer on the dielectric layer; And at least one passes dielectric layer to connect the conductive blind hole to line layer, is electrically connected to this chip type capacity cell, semiconductor chip and passive component layer so that this circuit layer reinforced structure sees through this conductive blind hole; And the outer fringe surface of this circuit layer reinforced structure is formed with a welding resisting layer, and this welding resisting layer is formed with a plurality of perforates to manifest this line layer of part as a plurality of electric connection pads.
Because the present invention is arranged at a heat-radiating substrate surface with active element and passive component, therefore have the following advantages: (1) can promote the radiating effect of electronic component.(2), can promote the performance of product because of the shortening of wiring distance.(3) use goodly because of wiring space, can dwindle the volume of product.(4) passive component layer of the present invention forms the electric capacity of a metal-insulator-metal spacer structure.
In order to enable a nearlyer step understanding feature of the present invention and a technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 is the buried chip package structure cutaway view of imbedding active and passive component in the preferred embodiments of the present invention.
Fig. 2 is for being provided with the structure cutaway view of flip-chip element on Fig. 1 of the present invention.
Fig. 3 is for being provided with the structure cutaway view of passive component on Fig. 2 of the present invention.
Description of reference numerals
3 circuit layer reinforced structures, 4 circuit layer reinforced structures
5 welding resisting layers, 6 tin balls
7 flip-chip elements, 8 passive components
10 first metallic plates, 12 second metallic plates
14 heat-radiating substrates 16 run through opening
17 run through opening 18 semiconductor chips
19 chip type capacity cells, 20 passive component layers
22 line layers, 31 dielectric layers
32 line layers, 33 conductive blind holes
34 openings, 36 electric connection pads
41 dielectric layers, 42 line layers
43 conductive blind holes, 71 solder projections
81 solder projections, 181 electronic padses
191 electronic padses
Embodiment
Please refer to Fig. 1, Fig. 1 is the buried chip package structure cutaway view of imbedding active and passive component in the preferred embodiments of the present invention.As shown in Figure 1, the bottom of this structure is one first metallic plate 10, and then, one second metallic plate 12 is located at the upper surface of first metallic plate 10 and is constituted a heat-radiating substrate 14 with first metallic plate 10.Wherein second metallic plate 12 is formed with at least one and runs through opening, for example: run through out 16 and 17.First metallic plate 10 of the present invention and second metallic plate 12 can be made of identical or different metal material.Etching one metallic plate for example forming the recess with a desired depth at this metallic plate, and then constitutes and has second metallic plate 12 and first metallic plate 10 that runs through opening.Perhaps directly form one and have another metal level that runs through opening, have second metallic plate 12 that runs through opening and be formed at heat-radiating substrate 14 structures on first metallic plate, 10 surfaces with formation at a metal sheet surface.In addition, first metallic plate 10 shown in Figure 1 of the present invention also can be the metal-metal of single metal level, multilayer or the laminated construction of metal-insulator material-metal, and all metal materials with good heat conduction function are all the category that the present invention's application is contained.
Subsequently at least one semiconductor chip 18 and a chip type capacity cell 19 usefulness binding materials (figure does not show) are connect respectively and place first metallic plate 10 and be contained in second metallic plate, 12 formed opening 16 and 17 run through.Wherein, the active face of semiconductor chip 18 includes a plurality of electronic padses 181, and semiconductor chip 18 can be active element, for example: and internal memory, light-emitting component or integrated circuit (IC) chip etc., and chip type capacity cell 19 also has the active face that includes a plurality of electronic padses 191 as similar semiconductor chip.Semiconductor chip 18 of the present invention is used the upper surface that a kind of binding material (figure does not show) is fixed in first metallic plate 10; In like manner, chip type capacity cell 19 is also used the upper surface that a kind of binding material is fixed in first metallic plate 10, the semiconductor chip 18 and the distance of the outside electric connection of chip type capacity cell 19 are shortened, and then promote electrical property efficiency; And be connected in the radiating efficiency that metal sheet surface more can effectively promote each electronic component, and electrical performance is preferably arranged.
Part upper surface at second metallic plate 12 is provided with a passive component layer 20 then.Passive component layer 20 can be a dielectric materials layer with high-k, and this dielectric material laminar surface is provided with the line layer 22 that at least one is made of a metal level, wherein line layer 22, dielectric materials layer and second metallic plate 12 form a metal-insulator-metal (Metal-Insulator-Metal, MIM) electric capacity of spacer structure.Next, form a circuit layer reinforced structure 3 and a circuit layer reinforced structure 4 in heat-radiating substrate 14 surface and cover chip type capacity cell 19, semiconductor chip 18 and passive component layer 20 top.Wherein, circuit layer reinforced structure 3,4 includes respectively: dielectric layer 31,41; Be formed at the line layer 32,42 on the dielectric layer 31,41; And pass dielectric layer 31,41 to connect to line layer 32,42 conductive blind hole 33,43, so that circuit layer reinforced structure 3,4 is seen through a plurality of electronic padses 181,191 on each active face that conductive blind hole 33,43 is electrically connected to semiconductor chip 18 and chip-shaped capacity cell 19; Line layer 22 on the passive component layer 20 and second metallic plate, 12 surfaces, in order to the line layer 22 on conducting semiconductor chip 18, chip-shaped capacity cell 19 and the passive component layer 20, and the demand of visual actual product design and optionally electrically connect heat-radiating substrate 14 to be made into function with ground connection.And the outer fringe surface of circuit layer reinforced structure 4 is formed with a welding resisting layer 5, and welding resisting layer 5 is formed with a plurality of perforates 34 to manifest part line layer 42 as a plurality of electric connection pads 36.So promptly finish the buried chip package structure of imbedding active and passive component of the present invention.
It should be noted that, finish after the preferred embodiments of the present invention, as shown in Figure 2, the present invention more can be in conjunction with the flip-chip package technology, and be formed with a welding resisting layer 5 at circuit layer reinforced structure 4 outer fringe surfaces, and welding resisting layer 5 is formed with a plurality of perforates 34 manifesting part line layer 42 as electric connection pad 36, and connects and be equipped with a plurality of tin balls 6 and at least one flip-chip element 7, and flip-chip element 7 for example internal memory, light-emitting component or integrated circuit (IC) chip etc.; And flip-chip element 7 electrically connects electric connection pad 36 partly with a plurality of solder projections 71, and flip-chip element 7 and the semiconductor chip 18 of encapsulating structure inside, chip-shaped capacity cell 19 are electrically conducted with passive component layer 20.Wherein flip-chip element 7 more can electrically connect to reach grounding function with heat-radiating substrate 14 by circuit layer reinforced structure 3,4.
It should be noted that in addition that as shown in Figure 3 the present invention also can connect on electric connection pad 36 and put at least one passive component 8, wherein passive component 8 can for example be electric capacity, inductance, resistance etc.; And passive component 8 utilizes a plurality of solder projections 81 to electrically connect the electric connection pad 36 of part, and passive component 8 and the semiconductor chip 18 of encapsulating structure inside, chip-shaped capacity cell 19 are electrically conducted with passive component layer 20.
In addition, the surface that heat-radiating substrate 14 of the present invention does not engage with the circuit layer reinforced structure can be provided with at least one radiator structure (figure does not show) in addition, the three-dimensional radiator structure of rough surface, groove, indentation or fin-shaped for example is in order to increase the area of dissipation of heat-radiating substrate 14.
Comprehensively above-mentioned, the buried chip package structure of imbedding active and passive component of the present invention is compared prior art and is comprised following advantage at least:
Heat-radiating substrate can promote the radiating effect of imbedding electronic component;
Active and passive component is connected to heat-radiating substrate and carries out ground connection, so can significantly promote electrical performance and reduce noise;
Integrate active element and passive component and imbed in the substrate, and the passive component layer forms the electric capacity of a metal-insulator-metal spacer structure;
Shorten the distance of wiring, can effectively promote the performance of product, and reach high function and high performance purpose and wiring space is used better, can dwindle the volume of product;
The flip-chip element on active element of imbedding and passive component and circuit layer reinforced structure surface and passive component can reach the purpose of modularization and multifunction.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (12)
1, a kind of buried chip package structure includes:
One first metallic plate;
One second metallic plate is located at the upper surface of described first metallic plate, and described second metallic plate forms at least one opening that runs through, and described second metal and described first metallic plate constitute a heat-radiating substrate;
At least one semiconductor chip and at least one chip type capacity cell are connected in described first metal sheet surface respectively, and are contained in formed described running through in the opening of described second metallic plate;
One passive component layer is arranged at the part upper surface of described second metallic plate; And
At least one circuit layer reinforced structure is located at described heat-radiating substrate surface and is covered described semiconductor chip, described chip type capacity cell and described passive component layer.
2, buried chip package structure as claimed in claim 1, wherein, including a plurality of electronic padses respectively is formed at an active face in addition for described semiconductor chip and described chip type capacity cell.
3, buried chip package structure as claimed in claim 1, wherein, described semiconductor chip is an active element, and described active element comprises wherein one of internal memory, light-emitting component and integrated circuit (IC) chip.
4, buried chip package structure as claimed in claim 1, wherein, described circuit layer reinforced structure includes:
One first dielectric layer;
At least one is formed at first line layer on described first dielectric layer; And
At least one passes described first dielectric layer to connect to the conductive blind hole of described first line layer, is electrically connected to described chip type capacity cell, semiconductor chip and passive component layer so that described circuit layer reinforced structure sees through described conductive blind hole.
5, buried chip package structure as claimed in claim 4, other includes a welding resisting layer, and described welding resisting layer is formed at the outer fringe surface of described circuit layer reinforced structure, and is formed with a plurality of perforates to manifest described first line layer of part as a plurality of electric connection pads.
6, buried chip package structure as claimed in claim 4, wherein, described circuit layer reinforced structure can electrically connect described heat-radiating substrate to reach grounding function.
7, buried chip package structure as claimed in claim 5, other includes at least one flip-chip chip, is arranged at the outer fringe surface of described circuit layer reinforced structure, and electrically connects the electric connection pad such as described of part.
8, buried chip package structure as claimed in claim 5, other includes at least one passive component, is arranged at the outer fringe surface of described circuit layer reinforced structure, and electrically connects the electric connection pad such as described of part.
9, buried chip package structure as claimed in claim 1, wherein, dielectric materials layer that described passive component layer is a high-k and described dielectric material laminar surface are provided with the line layer that at least one is made of a metal level.
10, as the buried chip package structure of claim 9, wherein, described metal level, described dielectric materials layer and described second metallic plate form the electric capacity of the spacer structure of a metal-insulator-metal.
11, buried chip package structure as claimed in claim 1, wherein, described heat-radiating substrate is not provided with at least one radiator structure in addition with the surface that described circuit layer reinforced structure engages.
12, buried chip package structure as claimed in claim 1, wherein, described semiconductor chip and described chip type capacity cell can electrically connect described heat-radiating substrate to reach grounding function by the circuit layer reinforced structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101184910A CN100505252C (en) | 2005-10-27 | 2005-10-27 | Buried chip package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101184910A CN100505252C (en) | 2005-10-27 | 2005-10-27 | Buried chip package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1956193A true CN1956193A (en) | 2007-05-02 |
| CN100505252C CN100505252C (en) | 2009-06-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2005101184910A Active CN100505252C (en) | 2005-10-27 | 2005-10-27 | Buried chip package structure |
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| CN (1) | CN100505252C (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980360A (en) * | 2010-09-15 | 2011-02-23 | 日月光半导体制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN102148173A (en) * | 2010-01-12 | 2011-08-10 | 马维尔国际贸易有限公司 | Attaching passive component to semiconductor package |
| CN102194711A (en) * | 2010-02-25 | 2011-09-21 | 新科金朋有限公司 | Semiconductor device and method of forming IPD in FO-WLCSP |
| CN101789380B (en) * | 2009-01-23 | 2012-02-15 | 日月光半导体制造股份有限公司 | Structure and process of internally buried package |
| CN106373952A (en) * | 2015-07-22 | 2017-02-01 | 台达电子工业股份有限公司 | Power module packaging structure |
| CN107393903A (en) * | 2016-04-28 | 2017-11-24 | 英飞凌科技股份有限公司 | Multiple layer metal pad |
| CN113745187A (en) * | 2020-05-28 | 2021-12-03 | 欣兴电子股份有限公司 | Carrier plate structure capable of increasing wiring area of core layer and manufacturing method thereof |
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2005
- 2005-10-27 CN CNB2005101184910A patent/CN100505252C/en active Active
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101789380B (en) * | 2009-01-23 | 2012-02-15 | 日月光半导体制造股份有限公司 | Structure and process of internally buried package |
| CN102148173A (en) * | 2010-01-12 | 2011-08-10 | 马维尔国际贸易有限公司 | Attaching passive component to semiconductor package |
| US8987830B2 (en) | 2010-01-12 | 2015-03-24 | Marvell World Trade Ltd. | Attaching passive components to a semiconductor package |
| US9171744B2 (en) | 2010-01-12 | 2015-10-27 | Marvell World Trade Ltd. | Attaching passive components to a semiconductor package |
| CN102194711B (en) * | 2010-02-25 | 2016-02-24 | 新科金朋有限公司 | Semiconductor device and form the method for IPD in FO-WLCSP |
| CN102194711A (en) * | 2010-02-25 | 2011-09-21 | 新科金朋有限公司 | Semiconductor device and method of forming IPD in FO-WLCSP |
| US9343396B2 (en) | 2010-02-25 | 2016-05-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming IPD in fan-out wafer level chip scale package |
| CN101980360B (en) * | 2010-09-15 | 2012-08-29 | 日月光半导体制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN101980360A (en) * | 2010-09-15 | 2011-02-23 | 日月光半导体制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN106373952A (en) * | 2015-07-22 | 2017-02-01 | 台达电子工业股份有限公司 | Power module packaging structure |
| US10096562B2 (en) | 2015-07-22 | 2018-10-09 | Delta Electronics, Inc. | Power module package |
| CN106373952B (en) * | 2015-07-22 | 2019-04-05 | 台达电子工业股份有限公司 | Power module package structure |
| CN107393903A (en) * | 2016-04-28 | 2017-11-24 | 英飞凌科技股份有限公司 | Multiple layer metal pad |
| CN107393903B (en) * | 2016-04-28 | 2020-10-16 | 英飞凌科技股份有限公司 | Multi-layer metal bonding pad |
| CN113745187A (en) * | 2020-05-28 | 2021-12-03 | 欣兴电子股份有限公司 | Carrier plate structure capable of increasing wiring area of core layer and manufacturing method thereof |
| CN113745187B (en) * | 2020-05-28 | 2024-03-22 | 欣兴电子股份有限公司 | Carrier plate structure with increased core layer wiring area and manufacturing method thereof |
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