CN1949702B - Method and apparatus for digital signal processing - Google Patents
Method and apparatus for digital signal processing Download PDFInfo
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- CN1949702B CN1949702B CN2006100635700A CN200610063570A CN1949702B CN 1949702 B CN1949702 B CN 1949702B CN 2006100635700 A CN2006100635700 A CN 2006100635700A CN 200610063570 A CN200610063570 A CN 200610063570A CN 1949702 B CN1949702 B CN 1949702B
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Abstract
The invention provides a digital signal processing method and device, reducing in-band interference and adjacent band interference of output signal on the condition that digital signal processing main clock frequency is not integral times as large as data clock frequency. And the invention mainly utilizes main clock sequence to synthesize data clock sequence and its time offset, utilizes the time offset and digital signal value to calculate transition value, inserts the transition value in the digital signal sequence to make step jumping on trapezoid holding signal waveform of the digital signal modified into slow transition of band middle values, and reduces spectrum mixing interference caused by main clock sampling.
Description
Technical field
The present invention relates to digital signal technique, particularly a kind of method of Digital Signal Processing and device.
Background technology
Be illustrated in figure 1 as theoretic digital signal, the sampling interval is T (also being that data rate is 1/T), has signal amplitude to impact on each sampled point, can think 0 or do not have a definition between the sampled point.
The frequency spectrum of above-mentioned digital signal as shown in Figure 2, the frequency spectrum lobe repeated with the interval 1/T cycle.This spectral shape is called the pectination frequency spectrum.
The actual digital signal of using can not be impulse response, usually as shown in Figure 3.Data sampling is spaced apart T, and data change on sampled point, at the numerical value that keeps between the sampled point on the sampled point.This kind signal can be thought the result of the filter output of the ideal digital signal shown in Figure 1 rectangular pulse that to have passed through an impulse response width be T, can be described as trapezoidal inhibit signal waveform.The general shape as shown in Figure 4 of the frequency spectrum of trapezoidal inhibit signal waveform, dash area is a power spectrum, can regard pectination frequency spectrum and Singh's function as
Product.
In communications applications, trapezoidal interpolation waveform is transmitted into transmission medium and gets on if the afterbody of Digital Signal Processing will output to D/A converter and become analog signal.The 0 frequency spectrum main lobe of locating frequently through being in after the frequency conversion on the available signal bandwidth of regulation, is useful signal in the future.The signal energy of other dash area is on the bandwidth of other signal through after the frequency conversion, can influence the communication quality of other signal, and being that band is outer disturbs.Therefore will be before emission with filter interference signal filtering outside these bands.
When realizing Digital Signal Processing with FPGA or ASIC, generally use external crystal-controlled oscillation, perhaps external crystal-controlled oscillation adds that the mode of inner phase-locked loop provides the master clock of a upper frequency, and other clock is all synthetic with master clock.The period T of above-mentioned digital signal is got the integral multiple of master clock cycle, only in this way could be in Synchronous Processing under the master clock frequency.But also have cycle of digital signal and master clock cycle an odd lot doubly, many occasions require the data clock speed adjustable continuously, for example require data rate adjustable continuously from 3.6Mhz～6.952Mhz in Chinese cable TV standard, the 1Khz stepping.In wide like this scope, require master clock to become integral multiple relation to be actually unlikely realization with data clock speed.If master clock speed and data rate an odd lot concern that doubly data clock is synthetic by master clock, then the pulse spacing of He Cheng data clock sequence changes.Suppose that master clock speed is Fm, the data clock speed that requires is Fs, Fm/Fs=M.N, N is a fractional part, then in the interval of the He Cheng adjacent clock pulse of data clock, be M master clock cycle (1-N) * 100%, N * 100% is a M+1 master clock cycle, and both are mixed into the data clock sequence equably.
Above-mentioned data clock sequence triggers the various processing to data, but is not that integral multiple concerns with the frequency of master clock and generated data clock sequence, can cause each data hold time of trapezoidal inhibit signal waveform unequal.This retention time unequally generally can not throw into question in numeric field, if can be used for waveform shaping, is converted to analog signal through D/A, is equivalent to master clock trapezoidal inhibit signal waveform among Fig. 3 be sampled, and the problem of bringing is exactly that in-band noise disturbs.According to nyquist sampling theorem, it is to repeat stack the cycle to the original signal frequency spectrum with sampling clock speed that time-domain sampling is equivalent at frequency domain, and the result can cause on the frequency spectrum of Fig. 4, in frequency K * Fm (K=± 1, ± 2, ± 3 ...) near energy be added to 0 frequently on the useful signal.If the sampling clock frequency is not the integral multiple of data rate, overlapping portion is exactly a noise jamming, makes signal just comprise a part of noise jamming energy before emission.Because this part noise jamming energy and useful signal are on the same frequency band, so can't can influence received signal quality by follow-up processing filtering.
Disturb in order to reduce this in-band noise, can adopt the method that improves master clock frequency, it is high more that master clock speed height is equivalent to sampling clock speed, corresponding to K * Fm (K=± 1, ± 2, ± 3 ...) near interfering energy just more little, the interfering energy at place is just more little frequently to be added to 0 behind over-sampling.But master clock frequency is subjected to the performance limitations of device, can not infinitely improve.And interfering energy is very slow with the speed of the rising reduction of master clock frequency, so reduce interfering energy by improving master clock frequency, signal to noise ratio also is difficult to reach the signal to noise ratio requirement of high-order modulating, the adjustable also very difficult realization of data speed frequency wide region simultaneously.
Summary of the invention
The invention provides a kind of digital signal processing method and device, the in-band noise that being used to suppresses to sample causes disturbs.
For achieving the above object, the invention provides a kind of digital signal processing method, this method is utilized master clock sequence generated data clock sequence, and obtain time deviator between described data clock sequence and the ideal data clock sequence, handle by described data clock sequence flip-flop transition value interpolation; Described transition value interpolation is handled and is specially: the signal value according to described time deviator and digital signal calculates transition value, and described transition value is inserted in the digital signal sequences.
The present invention also provides a kind of digital signal processing device, this device comprises clock synthesis module and transition value interpose module, the clock synthesis module is used for the generated data clock sequence, obtains the time deviator between described data clock sequence and the ideal data clock sequence; The transition value interpose module is used for calculating transition value according to described time deviator, and transition value being inserted in the digital signal sequences when being subjected to described generated data clock sequence and triggering.
Adopt above-mentioned method or device can obtain following beneficial effect:
Represent the data clock edge by data clock sequence and clock deviator, improved the expression precision of clock along the position, when master clock generated data clock cycle and master clock cycle an odd lot doubly concern, by the transition value interpolation ladder on the trapezoidal inhibit signal waveform is jumped over and to be revised as band intermediate value slow transition, thereby suppressed the spectral aliasing interference that sampling causes, on the changes in data rate scope of broad, disturbed in the band of inhibition output signal and the adjacent band interference.
Description of drawings
Fig. 1 is an ideal digital time domain plethysmographic signal schematic diagram;
Fig. 2 is an ideal digital signal spectrum schematic diagram;
Fig. 3 is an actual digital signal time domain waveform schematic diagram;
Fig. 4 is the actual digital signal spectrum diagram;
Fig. 5 is the inventive method embodiment overview flow chart;
Fig. 6 is the Digital Signal Processing oscillogram of the embodiment of the invention;
Fig. 7 is apparatus of the present invention example structure figure.
Embodiment
The embodiment of the invention mainly is to utilize master clock sequence generated data clock sequence, and obtain the time deviator of described data clock sequence, handle by described data clock sequence flip-flop transition value interpolation, promptly calculate transition value, described transition value is inserted be implemented under the situation that master clock frequency and data clock an odd lot doubly concern noise jamming in the inhibition zone in the digital signal sequences according to the time deviator between described data clock sequence and the ideal data clock sequence.
Provide frequency higher master clock in the digital signal processing, cycle is Tm=1/Fm, Fm is a master clock frequency, when concerning by synthetic data clock of master clock and master clock cycle an odd lot, actual synthetic data clock is exactly a unequal interval, desirable data clock has just had the time deviator that differs in size, P1 as shown in Figure 6, P2, P3 along position and actual synthetic data along the position.For keeping the temporal information of ideal data clock, increase a bus in addition and preserve each desirable clock edge and actual time deviator of synthesizing between the clock edge, this bus just is called the time deviator bus of generated data clock sequence.The embodiment of the invention is accurately represented data clock by the generated data clock sequence and with the time deviator of ideal data clock sequence.
As shown in Figure 5, be method embodiment of the present invention, mainly may further comprise the steps:
Step 501:, obtain the time deviator of data clock sequence by master clock sequence generated data clock sequence.
Step 502: described generated data clock pulse triggers according to the time deviator and calculates transition value, and this transition value is inserted in the digital signal sequences.The time deviator can adopt the relative time deviator herein, calculates transition value according to corresponding formulas.The time deviator has multiple expression way, be the numerical value of time deviator that unit carries out two and advances value representation with ns or ps directly for example, but the most useful mode is to adopt numerical value relative time deviator to represent.Described relative time deviator adopts formula PH (k)=TP (k)/Tm to calculate, wherein, k is the clock pulse sequence number of the generated data clock sequence of correspondence, TP (k) is the time deviator size of k generated data clock pulse and ideal data clock pulse, Tm is a master clock cycle, and PH (k) is the corresponding relative time deviator of TP (k).Reach the precision of 1/M if wish the relative time deviator, can adopt following formula to calculate:
PH(k)＝[TP(k)/Tm*M]/M
Wherein, [] expression rounds.The numerical value of M desirable 2
N, N is a time deviator highway width, promptly is used for the figure place of the binary number of express time deviator.Can make full use of the number range that bus is represented like this.Also can get other greater than 2 integer value, as long as can satisfy required precision.
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing preferred embodiment that develops simultaneously, the present invention is described in more detail.It is Fm that Digital Signal Processing provides master clock frequency, period T m=1/Fm.Requiring the generated data clock frequency is Fs (should be lower than Fm half), and the tunable steps of generated data clock is Fstep
Digital signal processing method first embodiment provided by the invention may further comprise the steps:
Step 1: logarithm value Vrem carried out the one-accumulate computing, accumulation result Vrem=Vrem+ frequency word FW, wherein the frequency change step-length Fstep of the frequency Fs/ clock to be synthesized of FW=clock to be synthesized when each main clock pulse arrived; Wherein the initial value of Vrem can set in advance and be arbitrary value.
Step 2: if Vrem＜CW goes to step 1;
If Vrem 〉=CW makes delivery to Vrem and handles, promptly Vrem=Vrem mod CW goes to step 3;
Realize the delivery processing for convenience, the Vrem initial value also can be set less than 2*CW-FW, adopt subtraction to reach the effect that delivery is handled simultaneously, promptly Vrem=Vrem-CW goes to step 3.
The frequency change step-length Fstep of CW=master clock Fm/ clock to be synthesized wherein.
Step 3: as time deviator TP (k) output, output frequency is the generated data clock pulse of Fs simultaneously with the Vrem after the delivery processing, and k is the clock pulse sequence number of the generated data clock sequence of correspondence.
The Vrem initial value just carries out certain skew with the phase place of data clock to the influence of TP (k), and digital Signal Processing is not impacted.
Step 4: calculate relative time deviator PH (k) according to TP (k);
Calculate relative time deviator PH (k) and can adopt formula 1:PH (k)=(M-1-[TP (k)/FW*M])/M or formula 2:PH (k)=(1+[TP (k)/FW*M])/M, wherein 1/M is a relative time deviator precision, the numerical value of M desirable 2
N, N is a time deviator highway width, promptly is used for the figure place of the binary number of express time deviator.
Above step 1 to step 4 realizes the generated data clock sequence, and obtains the time deviator of data clock sequence.
Step 5: calculate transition value XV (k) according to PH (k);
If above-mentioned steps adopts formula 1 to calculate PH (k) for 4 kinds, then the corresponding calculated transition value can adopt formula XV (k)=D (k+1)+(D (k)-D (k+1)) * PH (k), or adopt the mathematics of this formula to be out of shape XV (k)=D (k+1) * (1-PH (k))+D (k) * PH (k) or XV (k)=D (k+1)-D (k+1) * PH (k)+D (k) * PH (k), wherein, D (k) is a signal value of digital signal sequences, and D (k+1) is the back signal value of D (k).
If above-mentioned steps adopts formula 2 to calculate PH (k) for 4 kinds, then corresponding transition value is calculated mathematics distortion XV (k)=D (k) * (1-PH (k))+D (k+1) the * PH (k) or XV (k)=D (k)-D (k) * PH (k)+D (k+1) the * PH (k) that can adopt formula XV (k)=D (k)+(D (k+1)-D (k)) * PH (k) or adopt this formula.Wherein, D (k) is a signal value of digital signal sequences, and D (k+1) is the back signal value of D (k).
Step 6: sampled value XV (k) is inserted in the digital signal sequences, i.e. sampling instant insertion XV (k) between first sampled point of last sampled point of D (k) and D (k+1).
Among the said method embodiment, the condition that delivery is handled can be Vrem 〉=0, and concrete processing procedure such as method second embodiment may further comprise the steps:
Step 1: when each main clock pulse arrives Vrem is carried out the one-accumulate computing, accumulation result Vrem=Vrem+ frequency word FW, wherein the Vrem initial value can be set to less than CW, the frequency change step-length Fstep of FW=Fs/ clock to be synthesized, the frequency change step-length Fstep of CW=master clock Fm/ clock to be synthesized.
Step 2: if Vrem＜0 goes to step 1;
If Vrem 〉=0, as time deviator TP (k) output, k is the clock pulse sequence number of the generated data clock sequence of correspondence, goes to step 3 with the Vrem after adding up.
Step 3: Vrem is made delivery handle, be i.e. Vrem=Vrem mod CW; Output frequency is the generated data clock pulse of Fs simultaneously.Realize the delivery processing for convenience, can adopt subtraction to reach the effect that delivery is handled, i.e. Vrem=Vrem-CW.
The step 4 of subsequent step such as method first embodiment does not repeat them here to step 6.
Above-mentioned method embodiment carries out the one-accumulate computing to Vrem when each main clock pulse arrives, also can tire out to subtract computing in actual process, and the 3rd embodiment may further comprise the steps as method:
Step 1: when each main clock pulse arrives Vrem is carried out once the tired computing that subtracts, the tired Vrem=Vrem-FW as a result that subtracts; The Vrem initial value can be arbitrary value, the Vrem initial value can be set greater than-2*CW+FW for making things convenient for processing.
Step 2: if Vrem≤-CW, the absolute value of Vrem is made delivery handle Vrem=-(| Vrem|mod CW), if the Vrem initial value is set, can adopt add operation to reach the effect that delivery is handled greater than-2*CW+FW, promptly Vrem=Vrem+CW goes to step 3; If Vrem＞-CW, go to step 1.
Step 3: the Vrem after delivery handled gets that negative output frequency is the generated data clock pulse of Fs simultaneously as time deviator TP (k) output, and k be the clock pulse sequence number of the generated data clock sequence of correspondence.
The step 4 of subsequent treatment such as method first embodiment is to step 6.The condition of carrying out the delivery processing in method the 3rd embodiment can also be Vrem≤0, and concrete the processing may further comprise the steps as method the 4th embodiment:
Step 1: subtract Vrem=Vrem-FW as a result to carrying out once the tired computing that subtracts, tiring out when each main clock pulse arrives; The initial value of Vrem can be any number, the Vrem initial value can be set greater than-CW and less than 0 for making things convenient for processing.
Step 2: if Vrem＞0 goes to step 1; If Vrem≤0, Vrem is got negative as time deviator TP (k), k be the clock pulse sequence number of the generated data clock sequence of correspondence, goes to step 3.
Step 3: Vrem is made delivery handle Vrem=-(| Vrem|mod CW),, then can reach the delivery effect with add operation if the Vrem initial value is set greater than-CW and less than 0, i.e. Vrem=Vrem+CW, output frequency is the generated data clock pulse of Fs simultaneously.
The step 4 of subsequent step similar approach first embodiment is to step 6.
By the embodiment of above method as can be seen, the present invention can make that by simple computation master clock frequency improves greatly, disturbs thereby reduce in the band, and the transition value interpolation suppresses the spectral aliasing that sampling causes and disturbs.
For realizing that the above-mentioned method embodiment of the present invention provides device embodiment of the present invention, the present invention includes clock synthesis module and transition value interpose module, the clock synthesis module is used for the clock of anamorphic zone time deviator, the transition value interpose module is used for the clock calculation transition value according to band time deviator, and transition value is inserted in the digital signal sequences.
Concrete, as shown in Figure 7, described clock synthesis module 100 comprises mould CW arithmetic unit 1001, time deviator arithmetic unit 1002.Transition value interpose module 200 comprises transition value arithmetic unit 2000, dateout synthesis module 2009.Mould CW arithmetic unit 1001 output generated data clock sequence and time deviator TP, time deviator arithmetic unit 1002 calculates relative time deviator PH (k) according to the TP (k) of mould CW arithmetic unit output, and generated data clock sequence flip-flop transition value arithmetic device 2000 calculates transition value and dateout synthesis module 2009 according to PH (k) transition value is inserted in the digital signal sequences.
Described device provides the master clock of a upper frequency, frequency Fm, period T m=1/Fm.Requiring the rate adjusted step-length of generated data clock is Fstep, if the clock rate that will export is Fs, frequency word FW=Fs/Fstep should be integer.And CW=Fm/Fstep also should be integer.The numerical value of mould CW arithmetic unit 1001 is designated as Vrem, and initial value can be set to any number, and each main clock pulse carries out one-accumulate, and accumulating values is FW:Vrem=Vrem+FW.Overflow whenever Vrem just is called to add up more than or equal to CW, Vrem is made delivery handle Vrem=Vrem mod CW, the Vrem after delivery is handled is as TP (k) output, and k is the clock pulse sequence number of the generated data clock sequence of correspondence.For making things convenient for delivery to handle, the Vrem initial value can be set less than 2*CW-FW, adopt subtraction to reach the effect that delivery is handled simultaneously, promptly Vrem=Vrem-CW exports an overflow pulse simultaneously.This overflow pulse be exactly frequency be the generated data clock pulse of Fs, the size of TP (k) express time deviator.Overflow pulse triggered time deviator arithmetic unit 1002 is done following computing with TP (k) and is just obtained the relative time deviator:
PH(k)＝(M-1-[TP(k)/FW*M])/M，
In the formula, 1/M is the precision of relative time deviator, the numerical value of M desirable 2
N, N is a time deviator highway width, promptly is used for the figure place of the binary number of express time deviator.The computing of following formula can be simplified, and takes advantage of M or removes the change that M only is equivalent to scaling position on the binary system bus, and the M-1-X computing is the equal of that X is got the complement of one's (every negate).Following formula in fact only need a division arithmetic as a result for it.Delay time register 1003 overflow pulse fixed delay a period of time as data clock Fs, make the relative time deviator PH (k) and the data clock sequence of output synchronous.
Relative time deviator PH (k) is sent to transition value interpose module 200, calculate transition value according to the relative time deviator by transition value arithmetic unit 2000.Transition value arithmetic unit 2000 comprises register 2001, register 2002, register 2003, register 2004, register 2005, adder 2006, subtracter 2007, multiplier 2008 in the present embodiment.Input data D (k) lock register 2001 by data clock, lock register 2002 again, finish following computing via subtracter 2007, multiplier 2008, adder 2006:
XV(k)＝D(k+1)+(D(k)-D(k+1))*PH(k)
If adopt the annexation of formula XV (k)=D (k+1) * (1-PH (k))+D (k) * PH (k) or XV (k)=D (k+1)-D (k+1) * PH (k)+then corresponding adder of D (k) * PH (k), subtracter, multiplier to change accordingly.
Time deviator arithmetic unit 1002 also available following formula calculate the relative time deviator:
PH(k)＝(1+[TP(k)/FW*M])/M，
1/M is the precision of relative time deviator, the numerical value of M desirable 2
N, N is a time deviator highway width, promptly is used for the figure place of the binary number of express time deviator.The corresponding calculated transition value adopts formula XV (k)=D (k)+(D (k+1)-D (k)) * PH (k) or XV (k)=D (k) * (1-PH (k))+D (k+1) * PH (k) or XV (k)=D (k)-D (k) * PH (k)+D (k+1) * PH (k).Adopt different transition value computing formula, the annexation of register, adder, subtracter, multiplier will be done respective change.
Dout (t)=D (k), from data clock FS pulse to the transition value clock pulse,
XV (k), the transition value clock pulse moment,
D (k+1), from the transition value clock pulse to the next data clock FS pulse.
Whole process can adopt two's complement arithmetic, but does not get rid of numeric representation exclusive disjunction of equal value on other mathematics.
Obviously, those skilled in the art can carry out some changes and distortion to the present invention and not break away from the spirit and scope of the present invention.Like this, if these modifications of the present invention and distortion are belonged within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and is out of shape interior.
Claims (12)
1. digital signal processing method, it is characterized in that, utilize master clock sequence generated data clock sequence, and obtain the time deviator between described data clock sequence and the ideal data clock sequence, handle by described data clock sequence flip-flop transition value interpolation;
Described transition value interpolation is handled and is specially: the signal value according to described time deviator and digital signal calculates transition value, and described transition value is inserted in the digital signal sequences;
The described master clock sequence generated data clock sequence that utilizes, and the time deviator of obtaining between described data clock sequence and the ideal data clock sequence comprises: when main clock pulse arrives, logarithm value Vrem carries out mould CW computing, output generated data clock pulse and time deviator, wherein, the initial value of numerical value Vrem sets in advance and is arbitrary value, the frequency change step-length Fstep of CW=master clock frequency Fm/ data clock sequence to be synthesized.
2. digital signal processing method as claimed in claim 1, it is characterized in that, the described master clock sequence generated data clock sequence that utilizes, and the time deviator of obtaining between described data clock sequence and the ideal data clock sequence comprises: logarithm value Vrem carried out the one-accumulate computing when each main clock pulse arrived, accumulation result Vrem=Vrem+ frequency word FW, when Vrem more than or equal to CW, Vrem is made mould CW to be handled, Vrem after the delivery processing is exported as time deviator TP (k), output generated data clock pulse, the frequency change step-length Fstep of the frequency Fs/ clock to be synthesized of FW=clock to be synthesized wherein, k are the clock pulse sequence number of corresponding generated data clock sequence.
3. digital signal processing method as claimed in claim 1, it is characterized in that, the described master clock sequence generated data clock sequence that utilizes, and the time deviator of obtaining between described data clock sequence and the ideal data clock sequence comprises: logarithm value Vrem carried out the one-accumulate computing when each main clock pulse arrived, accumulation result Vrem=Vrem+ frequency word FW, when Vrem more than or equal to 0, with Vrem as after time deviator TP (k) output, Vrem is made mould CW to be handled, output generated data clock pulse, the frequency change step-length Fstep of the frequency Fs/ clock to be synthesized of FW=clock to be synthesized wherein, k are the clock pulse sequence number of corresponding generated data clock sequence.
4. digital signal processing method as claimed in claim 1, it is characterized in that, the described master clock sequence generated data clock sequence that utilizes, and the time deviator of obtaining between described data clock sequence and the ideal data clock sequence comprises: logarithm value Vrem carried out once the tired computing that subtracts when each main clock pulse arrived, the tired Vrem=Vrem-frequency word FW as a result that subtracts, when Vrem is less than or equal to negative CW, the absolute value of Vrem is made mould CW to be handled, delivery is handled the back result to be got and negatively exports as time deviator TP (k), export the generated data clock pulse simultaneously, the frequency change step-length Fstep of the frequency Fs/ clock to be synthesized of FW=clock to be synthesized wherein, k are the clock pulse sequence number of corresponding generated data clock sequence.
5. digital signal processing method as claimed in claim 1, it is characterized in that, the described master clock sequence generated data clock sequence that utilizes, and the time deviator of obtaining between described data clock sequence and the ideal data clock sequence comprises: logarithm value Vrem carried out once the tired computing that subtracts when each main clock pulse arrived, the tired Vrem=Vrem-frequency word FW as a result that subtracts, when Vrem is less than or equal to 0, Vrem is got negative as after time deviator TP (k) output, the Vrem absolute value is made mould CW to be handled, export the generated data clock pulse simultaneously, the frequency change step-length Fstep of the frequency Fs/ clock to be synthesized of FW=clock to be synthesized wherein, k are the clock pulse sequence number of corresponding generated data clock sequence.
6. as the arbitrary described digital signal processing method of claim 2 to 5, it is characterized in that the described time deviator of obtaining the data clock sequence further comprises according to time deviator TP (k) calculates relative time deviator PH (k).
7. digital signal processing method as claimed in claim 6 is characterized in that, described relative time deviator PH (k)=(M-1-[TP (k)/FW*M])/M, 1/M is the precision of relative time deviator, and M is not less than 2 integer, and [] expression rounds.
8. digital signal processing method as claimed in claim 7, it is characterized in that: described transition value XV (k)=D (k+1)+(D (k)-D (k+1)) * PH (k), D (k) is the previous digital signal value of transition value, and D (k+1) is the back digital signal value of D (k).
9. digital signal processing method as claimed in claim 6 is characterized in that, described relative time deviator PH (k)=(1+[TP (k)/FW*M])/M, 1/M is the precision of relative time deviator, and M is not less than 2 integer, and [] expression rounds.
10. digital signal processing method as claimed in claim 9 is characterized in that, described transition value is XV (k)=D (k)+(D (k+1)-D (k)) * PH (k), and D (k) is the previous signal value of transition value, and D (k+1) is the back signal value of D (k).
11. a digital signal processing device is characterized in that, comprises clock synthesis module and transition value interpose module, the clock synthesis module is used for the generated data clock sequence, obtains the time deviator between described data clock sequence and the ideal data clock sequence; The transition value interpose module is used for calculating transition value according to described time deviator, and transition value being inserted in the digital signal sequences when being subjected to described generated data clock sequence and triggering; Described clock synthesis module comprises mould CW arithmetic unit, time deviator arithmetic unit, mould CW arithmetic unit is used to add up, and delivery is handled or the tired delivery that subtracts is handled and obtained time deviator TP (k) and data clock sequence to be synthesized, time deviator arithmetic unit is used for obtaining relative time deviator PH (k) according to time deviator TP (k), k is the clock pulse sequence number of the data clock sequence of correspondence, wherein the frequency change step-length Fstep of CW=master clock frequency Fm/ data clock sequence to be synthesized.
12. digital signal processing device as claimed in claim 11, it is characterized in that, described transition value interpose module comprises transition value arithmetic unit, dateout synthesis module, the transition value arithmetic unit is used for calculating transition value according to the relative time deviator of time deviator arithmetic unit output, and the dateout synthesis module is used for transition value is inserted digital signal sequences.
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| 鲍小云.现代基站速率变换技术研究.中国优秀硕士学位论文全文数据库 信息科技辑.2002,(02), * |
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