CN1949525A - Reliable interconnection of solar cells including integral bypass diode - Google Patents
Reliable interconnection of solar cells including integral bypass diode Download PDFInfo
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- CN1949525A CN1949525A CNA2006101286961A CN200610128696A CN1949525A CN 1949525 A CN1949525 A CN 1949525A CN A2006101286961 A CNA2006101286961 A CN A2006101286961A CN 200610128696 A CN200610128696 A CN 200610128696A CN 1949525 A CN1949525 A CN 1949525A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0687—Multiple junction or tandem solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/142—Energy conversion devices
- H01L27/1421—Energy conversion devices comprising bypass diodes integrated or directly associated with the device, e.g. bypass diode integrated or formed in or on the same substrate as the solar cell
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
- H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
- H01L31/0508—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module the interconnection means having a particular shape
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/544—Solar cells from Group III-V materials
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
A solar cell array including a first solar cell with an integral bypass diode and an adjacent second solar cell and two discrete metal interconnection members coupling the anode of the bypass diode of the first cell with the anode of the second solar cell.
Description
Technical field
The present invention relates to solar cell semiconductor device field, and in particular, relate to the integrated semiconductor structure that comprises multijunction solar cell and bypass diode.
Background technology
Photocell (being also referred to as solar cell) is to be used to one of most important new equipment that produces electric energy, and electric energy is compared with other energy and had commercial competition in the past few years.Paid the solar conversion efficiency that considerable effort increases solar cell.Therefore, at present solar cell be used for many commercialities and the application that satisfies the needs of consumers in.Though this field is significantly developed, the more complicated application need of requirement satisfy to(for) solar cell is not synchronous with demand as yet.The application that for example is used for the satellite of data communication has increased the demand to the solar cell with improved electric power and Conversion of energy characteristic greatly.
In satellite and other space correlation application, the size of satellite electric power system, quality and cost depend on the power and the energy conversion efficiency of employed solar cell.In other words, the availability of (on-board) service is directly proportional with the electric power amount that is provided on the size and satellite of payload.Therefore, along with the payload more sophisticated that becomes, serve as on the satellite solar cell of the energy conversion device of electric power system and become and become more and more important.
Solar cell usually by semiconductor wafer with vertical, multijunction structure manufacturing, and wafer or cell arrangements become planar array, wherein individual solar cells links together in series current with row.Form the shape of row of array and structure with and the contained number of battery cells part that has by desired output voltage and electric current decision.
Solar cell in array all receives sunlight, that is, during the top layer of irradiation battery, each battery will and will carry electric current by forward bias in the array.Yet, when because the shade that causes of satellite motion or because when causing solar cell not receive sunlight, there is resistance in the destruction that battery is subjected to along the battery path.When solar cell was present in the array, some batteries may produce electric current, and other battery may be inactive.In the case, from the electric current of the irradiated battery battery by crested still probably.Electric current will pass battery layers by force, thereby make these reverse battery bias voltages and for good and all demote (if not destroying the electrical characteristics of these batteries).
If series circuit contains diode and some solar cell crested, the electric current that can be the battery by crested so provides the path in parallel that substitutes of passing inactive battery, and will keep the integrality of crested battery.The purpose of bypass diode is to draw out electric current from the battery of crested or destruction.When the battery of crested became reverse biased, bypass diode became forward bias.Because solar cell is in parallel with bypass diode, thus not to force electric current to pass the battery of crested, but diode draws out electric current from the battery of crested and make electric current complete so that keep the connection that arrives next battery.
If battery crested or do not receive sunlight because of other reasons, in order to make electric current select the diode path, the connection voltage in diode path must be less than the puncture voltage along the battery path so.Puncture voltage along the battery path will be at least five volts (if being not more than five volts) usually.Under the situation of Schottky (Schottky) bypass diode, Schottky contacts needs relatively small amount voltage to come " connection ", about 600 millivolts.Yet in order to tie by Ge, the bias voltage of Ge knot must be reverse, thereby need than big voltage.Make the bias voltage of Ge knot oppositely need about 9.4 volts, therefore almost need ten volts to make electric current follow the diode path.Be used for making reverse ten volts of the bias voltage of Ge knot may otherwise not be used for other application.
United States Patent (USP) the 6th, 680, No. 432 descriptions have the multijunction solar cell of integral bypass diode structure, wherein use the metal shunt to make Ge knot " short circuit " base stage to bypass diode.Because short circuit, institute only needs minimum voltage so that electric current passes between bypass diode and the Ge substrate.No longer need high voltage to force electric current to pass the Ge knot.Electric current easily flows through " short circuit " path.
More particularly, the multijunction solar cell of describing in the above-mentioned patent comprises substrate, bottom battery, intermediate cell, top battery, bypass diode, transverse conductance layer and shunt.Transverse conductance is deposited upon the top battery top.Bypass diode is deposited upon transverse conductance layer top.In a part of substrate, remove the bypass diode layer, thereby stay the solar cell layer of exposure.In another part, allow to keep the layer that will be used for forming bypass diode.Etch groove, thereby the solar cell district is separated with bypass district electricity.Plated metal shunt layer, wherein a side of shunt is connected to substrate, and the opposite side of shunt is connected to the transverse conductance layer, and the transverse conductance layer is connected to the active layer of bypass diode.The metal shunt is used for short circuit and forms the intermediate layer of the strutting piece of bypass diode, makes these layers not carry out any electric work energy, and only serves as the strutting piece of bypass diode.
As mentioned above, connect single solar cell successively to form the array of vertical row.This is connected in series needs to have power path between the anode of the negative electrode of a battery or top layer and adjacent cells or the bottom.Specifically, in having the solar cell of integral bypass diode, must set up being connected from the lower surface of multijunction solar cell and wafer from the bypass diode on the top surface of first wafer to adjacency.
The prior art interconnection configuration has been utilized single the electrically contacting that arrives the top layer (or anode) of bypass diode.Although this configuration is satisfactory substantially for most of application and reliability requirement, there is some application that needs stricter reliability.Before the present invention, existing interconnection configuration still can not satisfy such reliability requirement.
Summary of the invention
1. purpose of the present invention
The object of the present invention is to provide a kind of improved solar battery array.
Another object of the present invention is to provide the method for the interconnection generation electrical short that prevents between bypass diode and the solar cell semiconductor device.
Another object of the present invention is to provide the interconnection configuration in a kind of solar cell semiconductor device, described solar cell semiconductor device has bypass diode to be used to improve array reliability and to improve manufacturing output.
Another object of the present invention is to provide a kind of by utilizing bypass diode to contact the improved method that solar battery array is made in interconnection with the one-to-many that is close between the solar cell.
The those skilled in the art will understand other purposes of the present invention, advantage and novel feature from this disclosure (comprising following detailed description) and by putting into practice the present invention.Though followingly describe the present invention with reference to preferred embodiment, should be appreciated that, the invention is not restricted to described preferred embodiment.Obtain that those skilled in the art will realize that of this paper teaching belongs to disclosed herein and the scope of the invention advocated in and the present invention can have additional application, modification and embodiment in other field of practicality for it.
2. feature of the present invention
In brief, and put it briefly, the invention provides a kind of solar battery array, it comprises: one first solar cell, and it has an integral bypass diode; One second solar cell, it has an integral bypass diode; One first metal interconnected parts, the negative electrode of its described first solar cell that is coupled and the anode of described second solar cell.Further provide: one second metal interconnected parts, one first district on one first district on the anode of its described bypass diode that is coupled and the described anode of described second solar cell; One the 3rd metal interconnected parts, one second district on one second district on the described anode of its described bypass diode that is coupled and the described anode of described second solar cell.
Set forth in detail is considered to the novel characteristics of feature of the present invention in the appended claims.Yet, when reading in conjunction with the accompanying drawings, from following to understanding the present invention itself (about its structure and method of operation thereof) the description of specific embodiment together with its attached purpose and advantage.
Description of drawings
Consider in conjunction with the accompanying drawings, will better and more fully understand these and other feature and advantage of the present invention with reference to following detailed description.
Figure 1A is the plan view from above with semiconductor wafer of the solar cell of being with bypass diode as be known in the art;
Figure 1B is the amplification plan view of the solar cell of Figure 1A, and it shows bypass diode;
Fig. 2 passes the A-A plane of Figure 1B and the amplification cross-sectional view of the solar cell with bypass diode that intercepts;
Fig. 3 passes the B-B plane of Figure 1B and the amplification cross-sectional view of the solar cell with bypass diode that intercepts;
Fig. 4 A is the plan view from above of the solar cell with bypass diode that cuts in the wafer of describing from Figure 1A;
Fig. 4 B is the face upwarding view of the solar cell with bypass diode shown in Fig. 4 A;
Fig. 5 is the circuit diagram of the solar cell with bypass diode of Fig. 4 A;
Fig. 6 as be known in the artly utilizes negative electrode between the battery to the plan view from above of the sequence of two solar cells that connect into array of anode interconnect;
Fig. 7 passes the A-A plane of Fig. 6 and the cross-sectional view of two solar cells intercepting;
Fig. 8 has as the interconnection described among Fig. 6 A or according to the exploded view of the part of two solar cell sequences of the wire jumper of prior art;
Fig. 9 has another plan view from above to the solar cell of the band bypass diode of interconnection that is attached to battery according to prior art; With
Figure 10 is the plan view from above that has according to the present invention the solar cell with bypass diode of a pair of interconnection of bypass diode.
Embodiment
The detailed content of the present invention that now description is comprised exemplary aspect of the present invention and embodiment.Referring to the accompanying drawings and the description below, identical reference number is used for discerning components identical on identical or the function, and wishes to illustrate in the summary mode of highly simplifying the principal character of one exemplary embodiment.In addition, do not expect that accompanying drawing is depicted each feature of practical embodiments or the relative size of the element described, and and not to scale (NTS) draw.
The present invention relates to the interconnection that the anode of III-V multijunction solar cell in the array contacts with negative electrode, this is to realize by the metal clip or the wire jumper that use bonding or be welded to contiguous cells.For example United States Patent (USP) the 6th, 680, the solar cell semiconductor device of describing in No. 432 is generally comprised within epitaxial growth on the substrate but the bypass diode that separates with solar battery structure by groove, and described groove provides the electricity of solar cell and bypass diode to isolate.The surface of groove is covered by dielectric material, and described dielectric material is non-conductive and reduces to produce along battery edge any suitable material of the possibility of electrical short or shunt paths.
Figure 1A is the plan view from above with semiconductor wafer of the solar cell of being with bypass diode as be known in the art.Two batteries 501 that exemplary wafer 500 can be contained in that manufacture process marks or cut out from wafer 500 when finishing and 502.Abandon the peripheral edge material 550 of semiconductor wafer.That describes to arrive the top surface of battery 501 or negative electrode electrically contacts 510,511 and 512, and battery 502 electrically contact 506,507 and 508.Also describe the bypass diode 503 of battery 501 and the bypass diode 504 of battery 502, and in the amplifier section of the wafer that in Figure 1B, shows it is showed in greater detail.
Figure 1B is the amplification plan view from above with wafer area of the bypass diode of implementing in the solar cell of Figure 1A 503.Described figure also shows some vertical conductors 806, and described vertical conductor 806 extends on the top surface of battery 501 abreast, and is used for setting up with the top layer of battery 501 and electrically contacts, and when the surperficial electric charge of collecting when illuminated.Also describe conductive bus 807, described conductive bus 807 extends around the periphery of battery 501, and is used for each of electric connecting conductor 806 and is connected among Figure 1A the cathodic electricity contact 510,511 and 512 on the top surface of the battery 501 described.
The plan view from above of bypass diode 503 shows that it is preferably rectangular shape, and as seeing in the cross-sectional view of Fig. 2 and Fig. 3, it is preferably implemented as the mesa structure on the top layer that is manufactured on battery 501.Three isolated metal levels 630,631 and 632 extend on three sides of table top, and are used at the top layer of bypass diode 503 and set up between the substrate at place, groove 650 bottoms electrically contacting.Also deposit another metal level 804 on the top of bypass diode 503, it serves as electrically contacting of top terminal (being the anode of diode in the preferred embodiment) that arrive diode.
The detailed cross sectional view of the integral type semiconductor structure with three-joint solar cell structure 640 and bypass diode 503 that the A-A plane of Figure 1B intercepts is passed in Fig. 2 explanation.Described structure comprises substrate 602, three-joint solar cell 640, bypass diode 620, groove or trap 650 and electric shunting layer 630.Three-joint solar cell structure 640 further comprises bottom, the sub-battery 604,606 and 608 in centre and top respectively.One of conductive gate ruling 806, and be depicted as and be deposited on the transverse conductance layer 610.Also describe contact mat 804, it is deposited on the bypass diode 620.
The cross-sectional view of the battery 501 that the B-B plane of Figure 1B intercepts is passed in Fig. 3 explanation, and it describes to be used for preventing to produce along battery edge the possibility of electrical short or shunt paths around the non-conductive or dielectric materials layer 635 at the edge of battery 501.In preferred structure according to the present invention, be the ideal selection of this dielectric material 635 usually with the material identical materials that is used as battery 501 lip-deep antireflecting coating (ARC).Usually the ARC layer is coated to the top surface of the solar cell 501 in the present commercial device so that reduce front surface reflection.The manufacturing sequence step that preferred embodiment uses allows the ARC layer not only to extend on the surface of solar cell, and enters in the table top groove 650 so that the protection to the vertical edge of solar cell table top to be provided.
Say that more specifically in one embodiment, substrate is p type germanium (" Ge ") substrate 602, it is covered to form lower metal contact mat (as shown in Figure 4) by the metal level on semiconductor wafer 500 rears 514 fully.Bottom battery 604 contains p type Ge base layer 810, n type Ge emitter layer 812 and n type GaAs layer 814.Base layer 810 is formed in the substrate 602 by technology known in the affiliated field.In one embodiment, layer 810 can form by atom is diffused into the Ge substrate from the emitter layer 812 that deposits.After making bottom battery 604, deposition p type and n type tunnel junctions layer 816 sequence are known as the structure of tunnel-through diode when being formed with, and described structure provides the circuit element that connects bottom battery 604 and next son battery 606.
The Window layer 826 that is used for intermediate cell 606 also operates to reduce the reorganization loss.Window layer 826 is also improved the passivation of the battery surface of the knot that is positioned at the below.It will be understood by one of ordinary skill in the art that can be without departing from the present invention, the additional layer (one or more) of interpolation or deletion in battery structure.Before 608 layers of deposition top battery, p type and n type tunnel junctions layer 830 are deposited on the intermediate cell 606 to form the tunnel diode that intermediate cell 606 is connected to top battery 608.
According to present embodiment, top battery 608 comprises p type two InGaP aluminium (" InGaAlP
2") BSF layer 840, p type GaInAP
2 Base layer 842 and n type GaInAP
2 Emitter layer 844 and n type two aluminum phosphate indium (" AIInP
2) sequence of layer of Window layer 846.In case BSF layer 840 is deposited on the tunnel junctions layer 830, just the base layer 842 with top battery 608 is deposited on the BSF layer 840.After being deposited on layer 844 on the base layer 842, subsequently Window layer 846 is deposited on the emitter layer 844.
According to present embodiment, use n type GaAs cap layer 850 to strengthen and contact with the better of metal material.Cap layer 610 is deposited on the top battery 608.Top cover or transverse conductance layer 610 are formed by n type GaAs, are deposited on the Window layer 846.N type GaInP
2 Stopping etch layer 612 is deposited on the transverse conductance layer 610.After deposition stops etch layer 612, the layer of intending formation bypass diode on a part of battery 501 is deposited on the entire wafer with extensional mode.
In one embodiment, bypass diode layer 620 comprises the sequence of n type GaAs layer 860, i type GaAs layer 862 and p type GaAs layer 864.N type layer 860 is deposited on and stops on the etch layer 612.I type layer 862 is deposited on the n type layer 860.P type layer 864 is deposited on the i type layer 862.After sedimentary deposit 864, contact mat 804 is deposited on the bypass diode 620.In case form anode contact mat 804, the result is forming the integral type p-i-n bypass diode with p polarity on the n (p-on-n polarity) on the solar cell.In another embodiment, can use above-mentioned similar process forming n-i-p bypass diode on the solar battery structure with n polarity on the p (n-on-p polarity).It will be understood by one of ordinary skill in the art that can be without departing from the present invention, adds in bypass diode 620 or delete extra layer (one or more).
In one embodiment, metallic shunt 630 is deposited in the part of trap 650.One end 631 of shunt 630 is set up with substrate 602 and is electrically contacted, and the other end 632 of shunt 630 sets up with transverse conductance layer 610 and electrically contact, and and then arrives the active layer 846 (more particularly, arriving top battery 608) of three junction batteries.Can on some part of solar cell, deposit antireflecting coating 635 to strengthen solar cell properties.
Should be appreciated that can form the multijunction solar cell structure to any suitable combination of family's V element by the III of family cited in the periodic table, wherein the III of family comprises boron (B), aluminium (Al), gallium (Ga), indium (In) and thallium (T).The IV of family comprises carbon (C), silicon (Si), germanium (Ge) and tin (Sn).The V of family comprises nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi).
Fig. 4 A is the plan view from above that marks or cut solar cell 501 afterwards from wafer 500.In particular, peripheral bus 807, contact 510,511 and 512 are described, contact 804 with bypass diode.
Fig. 4 B is the face upwarding view of solar cell 501, and in particular, is explanation rear contact metal layer 514.
Fig. 5 is the circuit diagram 700 of explanation by the circuit of solar cell 501 representatives, and described circuit comprises three-joint solar cell structure and bypass diode 620.Circuit 700 is described top battery 608, intermediate cell 606, bottom battery 604, bypass diode 620, resistance bolck 702 and four paths 710,712,714 and 716.In one embodiment, resistance bolck 702 representative is from the resistance of the short circuit part of the multijunction solar cell structure that is placed in bypass diode 620 belows with from the resistance of the shunt shown in Fig. 2 630.
During the normal running space (for example, when solar cell 604 to 608 is exposed to sunlight, daylight, light, radiation and/or photon), solar cell 604-608 is a forward bias.They are the electric current that produces between the adjacent solar battery of electric energy and the vicinity that is connected in series with conversion of solar energy.Should be appreciated that term sunlight, daylight, light, radiation and/or photon are used interchangeably.In the present embodiment, solar cell is connected in series.When solar cell 604 to 608 was forward bias, bypass diode 620 was a reverse biased, because bypass diode 620 has the polarity opposite with solar cell.Therefore, when bypass diode 620 is in the reverse biased pattern, there is not electric current to pass through bypass diode 620 and solar cell 604 to 608.
When the electric current that produces from adjacent solar battery by the path or contact 710 when arriving at solar cell 604 to 608, solar cell 604 to 608 is delivered to path 716 with the total current of assembling (comprise the electric current that transformed by photoimpact solar cell 604 to 608 and pass path 710 and the input current that arrives at from adjacent solar battery) by path 712.Path or contact 716 and can be connected to another solar cell (solar cell of for example, describing among Fig. 6 521) and/or other electric device.
Yet during solar cell 604 to 608 was in the state of reverse biased pattern when 604 to 608 cresteds of (for example) solar cell the time, bypass diode 620 became forward bias.In this case, bypass diode 620 becomes active device and will pass path 714 from the electric current that adjacent solar battery arrives by path 710 and is delivered to path 716.That is to say that when solar cell 604 to 608 was in the reverse biased pattern, bypass diode 620 became forward bias, and path 714 is used for electric current 710 is delivered to path 716 from the path.Therefore, in this circuit arrangement, bypass diode protection battery 604 to 608.
Feature of the present invention is more clearly described now.Fig. 6 is the plan view from above of a part of utilizing the array of the solar cell with integral bypass diode, and it is described as the interconnecting member to contiguous solar cell 521 at present known in the prior art.In particular, describe left interconnecting member 600, it has respectively the first and second elongated contact components 605 and 606 that the pad 510 on the top surface with solar cell 501 contacts with 511.Use the contact component of two separation and the advantage of two pads to be respectively, one electrically contacts and disconnects or because realize improved reliability in the incident of other reasons and short circuit therein.At the right-hand side of battery 501, describe right interconnecting member 601, it has the first and second elongated contact components 610,611 respectively.First contact component 610 contacts 804 contacts with the anode of bypass diode, and the pad 512 on the top surface of second contact component 611 and solar cell 501 contacts, and fills up 512 and then is electrically connected to the gridline 806 and 807 that is positioned on the top surface.Especially it should be noted that and have only the single contact 804 that arrives bypass diode that electrically contacts.
Fig. 7 is the cross-sectional view that passes the array portion of the solar cell with two connections that the A-A plane of Fig. 6 intercepts.In particular, describe to be used to support the bottom glass substrate 516 of the battery 501,521 that forms array etc.The bottom of battery 501 or rear have the metal contact layer 514 as the whole surface of being described among Fig. 4 B of covering, and similarly, the rear of battery 520 has metal contact layer 517.Pad 510 on interconnecting member 600 and the battery 501 and the contact layer of battery 520 517 are set up and are electrically contacted.Adhesive layer 515 is fixed to glass substrate 516 with battery 501, and adhesive layer 520 is fixed to substrate 516 with battery 521.
The top surface of battery 501 is covered by protectiveness glass cover 513, and protectiveness glass cover 513 is transparent when being exposed to AMO space radiation environment (spectrum that occurs) in the track beyond the earth atmosphere.Covering 513 is generally the pyrex of doping cerium dioxide, and its thickness is nominally 100 microns.Covering 513 is that 50 microns suitable transparent silicon resin adhesive layer 512 is attached to battery 501 by nominal thickness.Similarly, the top surface of battery 521 is covered by glass cover 519, fixes by adhesive layer 518.
Fig. 8 is the exploded view that has as the part of two solar cell sequences of the interconnecting member 600 described among Fig. 6 A.Describe to have on the upper face of glass substrate 516, adhesive layer 515 and solar cell 501 part of pad 510 and 511.Interconnecting member 600 is usually by silver-plated invar alloy composition, and it forms the about 50 microns band of thickness, and wherein first end 610 is set up with pad 510 and electrically contacted.Preferably set up contact by welding, but for example mechanical adhesion, press pleat or soldering other interconnection technique within the scope of the invention.
Interconnecting member 600 is preferably serpentine shape, mid portion 612 and 613 and the rear 517 of battery 521 set up and electrically contact (as describing among Fig. 7).Second end 611 of parts 600 is set up with the pad 511 of battery 501 and is electrically contacted.Parts 600 also have many gaps 617,618, and flat surfaces changes direction to be used to reduce stress in these gaps.
Also describe covering 513 on the battery 501 and covering 519 and the adhesive layer 518 on adhesive layer 512 and the battery 521.
Fig. 9 is the plan view from above of solar cell that has in the prior art band bypass diode of same known another type interconnecting member that is attached to battery.The interconnecting member 600 in battery 501 left sides is with above identical to the described interconnecting member of Fig. 8 in conjunction with Fig. 6.The interconnecting member 603 of battery 501 right-hand sides is the example of " three-toed " parts, and wherein three parts contact with the pad 512 and 513 on bypass diode 804 and battery 501 right sides respectively.
Figure 10 is the plan view from above that has according to the present invention the solar cell of the band bypass diode of a pair of interconnection of bypass diode.
The interconnecting member 605 on battery 501 right sides is with above the interconnecting member 603 in conjunction with Fig. 9 is identical, and wherein a plurality of parts contact with the pad 512 and 513 on bypass diode 804 and battery 501 right sides.The interconnecting member 604 of battery 501 left-hand sides also is " three-toed " parts, and wherein a plurality of parts contact with the pad 510 and 511 in bypass diode 804 and battery 501 left sides.
As describing among Figure 10, the invention provides the first metal interconnected parts 604, it has: first, described first the be coupled negative electrode 510,511 of first solar cell 501 and the anode of second solar cell; And second portion, first district on first district on the negative electrode 804 of described second portion coupling bypass diode and the anode of second solar cell.
The second metal interconnected parts 605, it has: first, described first the be coupled negative electrode 512,513 of first solar cell 501 and the anode of second solar cell; And second portion, second district on second district on the negative electrode 804 of described second portion coupling bypass diode and the anode of second solar cell.
The those skilled in the art also will understand other modifications of the present invention and improvement.Therefore, only wish that this paper describes and the particular combinations of the parts that illustrate representative some embodiment of the present invention, and do not wish as qualification to the replacement device in the spiritual scope of the present invention.
To understand, each in the said elements, or two or more elements also can be effectively applied in other type structure different with the above-mentioned type together.
Though the present invention is illustrated and is described as implemented in the solar battery array, without wishing to be held to shown details, because can under the situation that breaks away from spirit of the present invention never in any form, make various modifications and structural change.
Under situation about further not analyzing, aforementioned content will disclose purport of the present invention fully, make other personnel easily to debug the present invention to be used for various application by using current knowledge, and can not ignore the feature that (on the position of prior art) constitutes the intrinsic propesties of general or particular aspects of the present invention clearly, and therefore, these debugging should and be wished to be included in the method and scope of equivalent of appended claims.
Claims (12)
1. solar battery array, it comprises: one first solar cell, it has an integral bypass diode;
One second solar cell, it has an integral bypass diode; One first metal interconnected parts, the negative electrode of its described first solar cell that is coupled and the anode of described second solar cell;
One second metal interconnected parts, one first district on one first district on the anode of its described bypass diode that is coupled and the described anode of described second solar cell; With
One the 3rd metal interconnected parts, one second district on one second district on the described anode of its described bypass diode that is coupled and the described anode of described second solar cell.
2. array according to claim 1, wherein said first solar cell comprises that one has the semiconductor body of semiconductor material layer sequence, described semiconductor body comprises: one first district, and wherein said semi-conducting material sequence of layer forms at least one battery of a multijunction solar cell; With one second district, wherein said sequence of layer forms described bypass diode, makes that described bypass diode is a reverse biased, and when described solar cell was reverse biased, described bypass diode was a forward bias when described solar cell is forward bias.
3. array according to claim 1, wherein said first solar cell comprise that one has the semiconductor body of semiconductor material layer sequence, and described semiconductor body comprises:
One first district, wherein said semi-conducting material sequence of layer forms a battery sequence of a multijunction solar cell; With
One second district; described second district by the groove in the described sequence of layer with described first distinguish from; and wherein said sequence of layer formation one is used for the strutting piece of described bypass diode; with when the described solar cell crested, flow through the influence of protecting described multijunction solar cell to avoid reverse biased by allowing electric current.
4. array according to claim 3, wherein said first solar cell further comprises a passivation layer, it extends in the described groove on the edge of the described sequence of layer in described first district.
5. array according to claim 2, the described sequence of layer of a wherein said battery and the described sequence of layer of described bypass diode be epitaxial growth in a different processing step.
6. array according to claim 2, wherein said semiconductor body comprise a Ge substrate, and in the described battery at least one made by GaAs to small part.
7. array according to claim 1, the wherein said second and the 3rd metal interconnected parts are metal clips that extend between the lower surface of the top surface of the described anode of the described bypass diode on described first solar cell and described second solar cell.
8. array according to claim 7, wherein said metal clip have smooth first end, a mid portion and second a smooth end.
9. array according to claim 8, the first described smooth end of wherein said second interconnecting member is set up one with a first of the described anode of described bypass diode and is electrically connected.
10. solar battery array, it comprises:
One first solar cell, it has an integral bypass diode; With
One second solar cell, it comprises
One first metal interconnected parts, one first district on one first district on the negative electrode of its described bypass diode that is coupled and the anode of described second solar cell; With
One second metal interconnected parts, one second district on one second district on the described negative electrode of its described bypass diode that is coupled and the described anode of described second solar cell.
11. array according to claim 10, the wherein said first metal interconnected parts are serpentine shape, and has the mid portion that second end section and that a first end section, that is connected to described first solar cell is connected to described first district on the described negative electrode of described bypass diode is connected to described second solar cell.
12. array according to claim 11, the wherein said first metal interconnected parts are serpentine shape, and has the mid portion that second end section and that a first end section, that is connected to described first solar cell is connected to described second district on the described negative electrode of described bypass diode is connected to described second solar cell.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/247,828 | 2005-10-11 | ||
| US11/247,828 US7732705B2 (en) | 2005-10-11 | 2005-10-11 | Reliable interconnection of solar cells including integral bypass diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1949525A true CN1949525A (en) | 2007-04-18 |
| CN100592525C CN100592525C (en) | 2010-02-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200610128696A Active CN100592525C (en) | 2005-10-11 | 2006-09-08 | Reliable interconnection of solar cells including integral bypass diode |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7732705B2 (en) |
| EP (1) | EP1775778B2 (en) |
| JP (1) | JP5302500B2 (en) |
| CN (1) | CN100592525C (en) |
| AT (1) | ATE551729T1 (en) |
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| CN106463516A (en) * | 2014-05-29 | 2017-02-22 | 太阳能公司 | In-cell bypass diode |
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| CN105590871A (en) * | 2014-11-07 | 2016-05-18 | 英飞凌科技股份有限公司 | Semiconductor device and electronic device |
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Also Published As
| Publication number | Publication date |
|---|---|
| EP1775778B1 (en) | 2012-03-28 |
| EP1775778A3 (en) | 2008-11-12 |
| EP1775778B2 (en) | 2016-09-28 |
| CN100592525C (en) | 2010-02-24 |
| EP1775778A2 (en) | 2007-04-18 |
| JP2007110123A (en) | 2007-04-26 |
| US20070079863A1 (en) | 2007-04-12 |
| US7732705B2 (en) | 2010-06-08 |
| JP5302500B2 (en) | 2013-10-02 |
| ATE551729T1 (en) | 2012-04-15 |
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