CN1949515A

CN1949515A - Method and apparatus for operating series nonvolatile memory unit

Info

Publication number: CN1949515A
Application number: CN200510108649.6A
Authority: CN
Inventors: 叶致锴
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2005-10-10
Filing date: 2005-10-10
Publication date: 2007-04-18
Anticipated expiration: 2025-10-10
Also published as: CN100463183C

Abstract

The invention relates to read of a memory cell with a charge storage structure, performed by measuring current between substrate region and one carrier current node of the memory cell. When the other parts of the memory cell store irrelated information, the read operation reduces coupling between charge capturing structures of different parts. Thus, the sensing range of the memory cell can be remarkably improved. And the invention also provides a series memory cell and a series memory cell array.

Description

The method and the device (two) of the non-volatile memory cells that operating series is arranged

Technical field

The present invention relates to the electric erazable programmable nonvolatile memory, especially relate to the memory of the charge-trapping (charge trapping) with bias voltage setting, it is quite sensitive for the charge storing unit capturing structure that reads diverse location.

Prior art

In electronics programming at present and the erasable nonvolatile memory technology, to be applied in the charge storing structure of every field, EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) and flash memory are main as is well known, and some memory cell structures can be used for electricity programming and erasable read only memory and flash memory.Along with the size of integrated circuit is dwindled, can produce in batches because of it and to manufacture program simple based on the memory cell structure of charge-trapping dielectric materials layer, attracted attention gradually.Based on the various memory cell structures of charge-trapping dielectric materials layer as comprising the structure that industry name in the known technology is called PHINES, NROM and SONOS, these memory cell structures by with charge-trapping to charge-trapping dielectric layers (as silicon nitride layer) and store information, and when capturing considerable net negative charge, the critical potential of memory cell will increase.Can be by removing net negative charge from electric charge capture layer or adding the critical potential that clean positive charge to electric charge capture layer reduces memory cell.

General memory cell dependence reverse read operation decides the content of memory construction, yet even only pay close attention to the information of a part of charge-trapping structure, in fact the reverse read technology can be coupled with a plurality of positions of charge-trapping structure.Such dependence limits the charge-trapping structure, as the use of nonvolatile memory, make the measured current sense scope of reverse read technology (sensing window) dwindle, the information storage of having only minority most probably is in the charge-trapping structure.

Energy consumption is another part that can improve.Portable electron device, as music player, mobile phone and wireless device, wherein spendable energy source is limited.The reverse read operation is the reason that a kind of energy runs off, and cause energy consumption, and this type of energy consumption can occur in similarly in the reading operation, and reading operation relies on the flow through degree of raceway groove in the memory cell of transverse current.

Therefore, need a kind of non-volatile memory cells, when only some charge-trapping structure stores relevant information, can read, but can be not in fact and a plurality of positions coupling of charge-trapping structure.In addition, also need a kind of reading operation that can reduce energy consumption with respect to the reverse read operation.

Summary of the invention

The present invention illustrates and a kind ofly operates nonvolatile memory array, comprises the structure of integrated circuit of this memory array and the integrated circuit that comprises capable non-volatile memory cells.

A kind of nonvolatile memory integrated circuit comprises store information for nonvolatile memory array, the bit line of charge storage state and the word line of grid current potential is provided.This nonvolatile memory array may comprise memory cell rows, and each memory cell includes area, a charge storing structure and one or more dielectric structure of first and second live stream node.Dielectric structure is adjacent to charge storing structure, makes a part of dielectric structure between charge storing structure and area, and a part of dielectric structure is between charge storing structure and door current potential source electrode.

Bit line has the corresponding row of memory cell, with the information on the corresponding row that a specific bit line is used in access memory cell.During some task memories, a bit line is electrically connected with first end of the corresponding row of memory cell, and during some task memories, same bit line is electrically connected with second end of the corresponding row of memory cell.For instance, between a programming operational period, identical bit line is electrically connected with first end and second end of corresponding row.In other example, during a reading operation, same bit lines is electrically connected with first end and second end of corresponding row.Carry out this reading operation, by measuring energy gap belt current component, to determine at least one charge storage state.

In certain embodiments, carry out extra task memory at nonvolatile memory array.In these extra task memories, a bit line is electrically connected with first end of the corresponding row of non-volatile memory cells, and second end of the corresponding row of non-volatile memory cells floats.

In certain embodiments, area is the trap in Semiconductor substrate.In another embodiment, area only is a Semiconductor substrate.

Other embodiment of aforementioned techniques comprises a kind of method of operating nonvolatile memory array, and according to delegation's nonvolatile memory of aforesaid technology.

In certain embodiments, comprise the first transistor and transistor seconds.During some task memories, bit line is by the first transistor, and is electrically connected with this first end of the corresponding row of memory cell.During some task memories, identical bit line is by transistor seconds, and is electrically connected with this second end of the corresponding row of memory cell.

In one embodiment, non-volatile memory cells has the design of a splitting bar and comprises a second grid.In task memory, each different grid applies a bias voltage to area.By the design of this splitting bar, logic is implemented to wipe and the program bias setting, electronics is penetrated to the part of charge storing structure correspondence and from the part of this charge storing structure correspondence by injecting electronics, to change charge storage state.

In other embodiments, non-volatile memory cells has floating grid design and nanocrystal design.By design of this floating grid or nanocrystal design, logic is implemented to wipe and the program bias setting, electronics is penetrated to the part of charge storing structure correspondence and from the part of this charge storing structure correspondence by injecting electronics, to change charge storage state.

In other embodiments, non-volatile memory cells has the design of charge-trapping material.By this charge-trapping material, logic is implemented to wipe and the program bias setting, electronics is penetrated to the part of charge storing structure correspondence and from the part of this charge storing structure correspondence by injecting electronics, to change charge storage state.

In a reading operation, measurement electric current between first live of flowing through stream node and/or second live stream node and the area comprises in flow through area and first live stream node and second live stream node tunnelling current between at least one energy gap, to determine charge storage state.In order to reduce the measurement electric current of flowing through between first live stream node and/or second live stream node and the area, read bias voltage and be arranged on generation first potential difference between grid and first live stream node and/or second live stream node, and between first live stream node and/or second live stream node and area, produce second potential difference.

The electric current of first and second live stream node of the non-volatile memory cells measured because reading operation does not need to flow through, therefore, reading bias voltage is provided with and allows one of them zone of first and second live stream node to float, then there is bias voltage in another zone of first and second live stream node, with and area between produce potential difference.

Measurement electric current between first and/or second live of flowing through stream node and the area comprises tunnelling current between at least one energy gap, and the area of flowing through and first and/or second live stream node are with the decision charge storage state.In order to reduce the measurement electric current of flowing through between first and/or second live stream node and the area, read bias voltage and be arranged on generation first potential difference between grid and first and/or second live stream node, and between first and/or second live stream node and area, produce second potential difference.

The potential difference of at least one produces electric field in grid and first and second live stream node, and produces band bending (band bending) at the same area.The degree of band bending is subjected to the influence of the charge storage state of charge-trapping structure, makes that in first and second live stream node tunnelling current changes because of charge storage state between at least one energy gap.In certain embodiments, bias voltage is arranged between one of area and first and second live stream node and applies the bias plasma potential difference, and make first and second live stream node another float.

Other embodiment of aforementioned techniques comprises according to delegation's non-volatile memory cells of aforementioned techniques and operates the method for this row.

By understanding others of the present invention and advantage with reference to following accompanying drawing, implementation method and claim.

Different embodiment comprises memory cell with n raceway groove, have the memory cell of p raceway groove or have the memory cell of n raceway groove and have the memory cell of p raceway groove.

Embodiment

Figure 1A is the sketch of charge capturing storage unit, is illustrated in the reading operation that a charge-trapping structure corresponding to source terminal (charge trapping structure) part is carried out.P type doped substrate regions 170 comprises n+ doped source and drain region 150 and 160.Remaining memory cell comprises the end dielectric structure 140 that is positioned on the substrate, be positioned at charge-trapping structure 130 on the end dielectric structure 140 (bottom oxide), be positioned at the top dielectric structure 120 (top oxide layer) on the charge-trapping structure 130 and be positioned at grid 110 on the oxidation structure (should be the top dielectric structure) 120.Typical top dielectric structure comprises the silicon dioxide and the silicon oxynitride of about 5 to 10 nanometer thickness, or other similar high dielectric constant material, as alundum (Al (Al ₂O ₃).Dielectric structure of the typical end comprises the silicon dioxide and the silicon oxynitride of about 3 to 10 nanometer thickness, or other similar high dielectric constant material.Typical charge-trapping structure comprises the silicon nitride of about 3 to 9 nanometer thickness, or other similar high dielectric constant material, as alundum (Al (Al ₂O ₃), hafnium oxide (HfO ₂) and other.

Comprise as thickness at the bottom oxide of 2 nanometer to 10 nanometers, thickness in the electric charge capture layer of 2 nanometer to 10 nanometers and thickness top oxide layer as the memory cell of SONOS memory in 2 nanometer to 15 nanometers.Other charge capturing storage unit is PHINES and NROM.

In certain embodiments, work function that grid material has is greater than the intrinsic work function (intrinsic work function) of n type silicon or greater than about 4.1 electron-volts (eV), be preferably more than 4.25 electron-volts (eV), for instance greater than 5 electron-volts (eV).Typical grid material comprises the metal and the material of p type polysilicon, titanium nitride (TiN), platinum (Pt) and other high work function.Other other material that is suitable for present technique embodiment includes but not limited to ruthenium (Ru), iridium (Ir), nickel (Ni) and cobalt (Co) metal, including but not limited to the metal alloy of ruthenium-titanium (Ru-Ti), Ni-Ti (Ni-T (should be Ti)), metal nitride and including but not limited to ruthenic oxide (RuO ₂) metal oxide.With respect to the typical n type polysilicon bar utmost point, the grid material of high work function can cause the injection barrier of higher electron tunneling.Have silicon dioxide and be about 3.15 electron-volts (eV) as the injection barrier of the grid of the n type polysilicon of top dielectric structure.Therefore, in the embodiments of the invention, grid and the employed material of top dielectric layer have the injection barrier that is higher than 3.15 electron-volts (eV), as are higher than about 3.4 electronvolt (eV), preferably are higher than 4 electron-volts (eV).For the p type polysilicon bar utmost point with silicon dioxide top dielectric layer, its injection barrier is about 4.25 electron-volts (eV), and extremely relevant with n type polysilicon bar with silicon dioxide top dielectric layer, converge the critical value of (converged) unit generation and can reduce to about 2 volts (V).

In Figure 1A, the source terminal of memory cell as from grid 110 or substrate 170, is reseted the electron storage that adds operation via raceway groove and is injected electronics, Flower-Nordheim tunnel, or other electric charge mobile process, inject or the initial secondary electron injection of raceway groove as channel hot electron.The drain electrode end of memory cell then stores the hole that adds, as passing through energy interband (band-to-band), with the drain electrode end of hole iunjected charge capturing structure 130.

The bias voltage setting of Figure 1A is the source terminal that is used for reading electric charges capturing structure 130, the voltage of its grid 110 is-10 volts (V), the voltage of source electrode 150 is 2 volts (V), and the current potential of drain electrode 160 is (floating) that float, and the current potential of substrate 170 is 0 volt (V).Except reading operation among Figure 1B is to carry out but not the source terminal execution at the drain electrode end of charge-trapping structure, the memory cell of Figure 1B is similar to the memory cell of Figure 1A.Bias voltage setting at Figure 1B is the drain electrode end that is used for reading electric charges capturing structure 130, and the voltage of grid 110 is-10 volts (V), and the current potential of source electrode 150 floats, and the voltage of drain electrode 160 is 2 volts (V), and the current potential of substrate 170 is 0 volt (V).Setting at each terminal room decision bias voltage, make be with can be crooked effectively and in n+ doped source 150 (Figure 1A) or in n+ doped-drain 160 (Figure 1B) generation energy interband electric current, but still keep substrate 170 and source electrode 150 (Figure 1A) or drain and have enough low potential difference between 160 (Figure 1B), make programming or do not wipe and can take place, with reference to the description of Fig. 3 A, Fig. 3 B, Fig. 4 A, Fig. 4 B, Fig. 7 A and Fig. 7 B.

Bias voltage setting in Figure 1A and Figure 1B, the substrate 170 that p mixes and n+ doped source 150 or the characteristic that engages at the engaging zones demonstration reverse biased p-n of 160 of n+ doped-drain.Yet grid potential produces enough crooked being with, and makes n+ doped source 150 (Figure 1A) or n+ doped-drain 160 (Figure 1B) produce energy interband tunnelling.At source electrode 150 or in the high-dopant concentration of drain electrode 160, the high charge density of space charge region generation and the short length (current potential on the space charge region changes) that space charge region is followed, provide narrow band curvature.Electronics on the valence band (valence band) passes forbidden band energy gap (forbidden gap) to conduction band (conduction b and), and drift to potential barrier (potential hill) downwards, darker than n+ doped source 150 (Figure 1A) or n+ doped-drain 160 (Figure 1B).Similar situation, the hole upwards drifts to potential barrier, away from n+ doped source 150 (Figure 1A) or n+ doped-drain 160 (Figure 1B), and towards p type substrate 170.

The current potential of grid 110 passes through end dielectric structure 140 (bottom oxide) and the current potential of control section substrate 170, afterwards, the degree of crook of the current potential of part substrate 170 by being with between end dielectric structure 140 (bottom oxide) control end dielectric structure 140 (bottom oxides) and n+ doped source 150 (Figure 1A) or n+ doped-drain 160 (Figure 1B).When the current potential of grid 110 became more negative (negative), the current potential of the part substrate 170 by end dielectric structure 140 (bottom oxide) control became more negative, makes n+ doped source 150 (Figure 1A) or n+ doped-drain 160 (Figure 1B) band curvature get darker.Because the combination of underlying cause, cause more can flowing by the interband electric current: 1) the overlapping increase between the electron energy level that is not occupied on the opposite side of electron energy level that is occupied on the side of bending energy band and bending energy band, and 2) by (Sze that narrows down of the barrier width between the electron energy level that occupied and the electron energy level that do not occupied, physics of semiconductor device in 1981, Physics of Semiconductor Device).

As described above, the drain electrode end of charge-trapping structure 130 is occupied by many relatively holes, and with respect to the drain electrode end of charge-trapping structure 130, the source terminal of charge-trapping structure 130 is occupied by many relatively electron institutes on the contrary.Therefore, according to Gauss law (Gauss ' s Law), when applying-10 volts (V) in grid 110, with respect to drain electrode end, the bias voltage on source terminal upper base dielectric structure 140 (bottom oxide) is more negative.Therefore, with respect to flowing, be used for reading electric charges capturing structure 130 source terminals and between the source electrode 150 of the bias voltage setting shown in Figure 1A and substrate 170, have more electric current to flow for reading electric charges capturing structure 130 drain electrode ends and at drain electrode 160 and the electric current between the substrate 170 that the bias voltage shown in Figure 1B is provided with.

In the bias voltage setting that is used to read shown in Figure 1A and Figure 1B and be illustrated in Fig. 3 A, Fig. 3 B, Fig. 4 A and the difference of Fig. 4 B between being provided with for programming and the bias voltage wiped, demonstrate meticulous (careful) balance.For reading, potential difference between source region and the drain region would not produce a large amount of states that can transport the charge carrier of tunneling oxide and influence Charge Storage, relatively, for programming and wiping, the potential difference between source region and the drain region is enough to produce a large amount of states that can transport the charge carrier of tunneling oxide and can influence Charge Storage.

Fig. 2 A illustrates the sensing range figure of a typical non-volatile memory cell.In Fig. 2 A, because second effect (second bit effect) makes the memory cell 250 of reverse read operation have narrow relatively sensing range.During the time interval 230, programme when first, first 210 the current curve that reads will be from rising to high-order 264 than lowest-order 260, thereby during the time interval 230, second 220 of first 210 programming materially affect read current curve, make it reduce to low order 262 from lowest-order 260.During the time interval 240, programme when second, second 220 read current curve and will rise to high-order 266 from low order 262, thereby during the time interval 240, first 210 of second 220 programming materially affect read current curve, make it rise to high-order 266 from high-order 264.Therefore, when one of memory cell carrying out the reverse read operation, generation read that electric current essence is subjected to other programming or the state wiped influences.This is because between the reverse read operational period, and the grid potential that provides can make other vague and general and counter-rotating of opposing become more difficult, and clashes into the part substrate that passes other below.

Fig. 2 B is illustrated in other zone of charge storing unit capturing structure and carries out when programming operation the sensing range of memory cell.In the accompanying drawing of Fig. 2 B, first and second charge-trapping is partly carried out programming.Curve 210 is represented the electric current that reads of first charge-trapping part, and curve 220 is represented the electric current that reads of second charge-trapping part.The shown sensing range of Fig. 2 B is wide relatively, and this is because for first terminal or second terminal, can the interband reading operation be local (local).First charge-trapping partly carry out can interband reading operation cause that to read electric current insensitive relatively for the logic state of second charge-trapping part, and it is insensitive relatively for the logic state of first charge-trapping part can the interband reading operation causing of partly carrying out to read electric current at second charge-trapping.This energy interband reading operation does not have the feature of the second charge-trapping part effect of reverse read operation relatively, and wherein, the reading operation of carrying out at an end of charge-trapping structure causes and reads electric current and depend on the stored information of the charge-trapping structure other end relatively.

Each charge-trapping partly stores a position or a plurality of position.For instance, if charge-trapping partly stores two positions, four discontinuous charge values are arranged then.

Fig. 3 A and Fig. 3 B are the sketch of charge capturing storage unit, and the channel hot electron that its different piece that is illustrated in the charge-trapping structure is carried out injects.Bias voltage setting at Fig. 3 A is to be used to add the source terminal of electronics 134 to charge-trapping structure 130, the voltage of grid 110 is 10 volts (V), the voltage of source electrode 150 is 5 volts (V), and the current potential of drain electrode 160 is 0 volt (V), and the current potential of substrate 170 is 0 volt (V).The memory cell of Fig. 3 B is similar to the memory cell of Fig. 3 A, except adding electronics 134 among Fig. 3 B to the drain electrode end of charge-trapping structure 130 but not source terminal.In the bias voltage of Fig. 3 B was provided with, the voltage of grid 110 was 10 volts (V), and the current potential of source electrode 150 is 0 volt (V), and drain electrode 160 voltage is 5 volts (V) and the current potential of substrate 170 is 0 volt (V).

Fig. 4 A and Fig. 4 B are the sketch of charge capturing storage unit, and what its different piece that is illustrated in the charge-trapping structure was carried out can inject by the interband hot hole.Bias voltage setting at Fig. 4 A is to be used to add the source terminal of hole 434 to charge-trapping structure 130, the voltage of grid 110 is-6 volts (V), the current potential of source electrode 150 is 0 volt (V), and the voltage of drain electrode 160 is 5 volts (V), and the current potential of substrate 170 is 0 volt (V).The memory cell of Fig. 4 B is similar to the memory cell of Fig. 4 A, except adding hole 433 (should be 434) among Fig. 4 B to the drain electrode end of charge-trapping structure but not source terminal.In the bias voltage array of Fig. 4 B, the voltage of grid 110 is-6 volts (V), and the voltage of source electrode 150 is 5 volts (V), and the current potential of drain electrode 160 is 0 volt (V), and the current potential of substrate 170 is 0 volt (V).In Fig. 4 A and the shown sketch of Fig. 4 B, the electric charge 433 that stores in the charge-trapping structure symbolically shows electronics less than the hole, and the hole of previous programming has been wiped in the hole that is injected into demonstration.

In certain embodiments, the programming expression removes electronics by adding the hole to the charge-trapping structure or from the charge-trapping structure, the net charge that is stored in the charge-trapping structure is just become, remove the hole or add electronics to the charge-trapping structure from the charge-trapping structure and wipe expression, it is negative that the net charge that is stored in the charge-trapping structure is become.Yet in other embodiments, it is negative that the programming expression becomes the net charge that is stored in the charge-trapping structure, wipes expression the net charge that is stored in the charge-trapping structure is just become.Can use multiple electric charge mobile mechanism, if can the interband tunnelling cause that heat carrier injects, electric field causes tunnelling, the raceway groove heat carrier injects, the initial substrate carrier of raceway groove injects and from the direct Tunneling of substrate.

Fig. 5,6 is the erase operations figure that carries out at delegation's non-volatile memory cells, and non-volatile memory cells is provided with and interconnects with NOR gate (NOR).In the bias voltage setting of Fig. 5 is to be used to wipe the NOR memory lines, and word line 510,520,530 and 540 voltage are-8 volts (V), and

bit line

504 and 506 current potential float, and the voltage of substrate 502 is 10 volts (V).In the bias voltage setting of Fig. 6 is to be used to wipe the NOR memory lines, and word line 510,520,530 and 540 voltage are 8 volts (V), and

bit line

504 and 506 current potential float, and the voltage of substrate 502 is-10 volts (V).Bias voltage among Fig. 5 and Fig. 6 is provided with difference and is: electronics from the gate tunneling to the substrate, then is tunneling to grid from substrate from all directions among Fig. 5 in Fig. 6.

Fig. 7 A and Fig. 7 B are the sketch of charge capturing storage unit, and it illustrates corresponding to Fig. 5,6 and carry out erase operations in the charge-trapping structure.Bias voltage setting at Fig. 7 A is to be used for eraseable memory unit, and the voltage of grid 110 is-8 volts (V), and the current potential of source electrode 150 and drain electrode 160 floats, and the voltage of substrate 170 is 10 volts (V).The erase operations of Fig. 7 A is the erase operations of corresponding diagram 5NOR memory lines.Except the direction that electronics moves, the memory cell of Fig. 7 B is similar to the memory cell of Fig. 7 A.In the bias voltage of Fig. 7 B was provided with, the voltage of grid 110 was 8 volts (V), and the current potential of source electrode 150 and drain electrode 160 floats, and the voltage of substrate 170 is-10 volts (V).The erase operations of Fig. 7 B is the erase operations of corresponding diagram 6NOR memory lines.It is the electronics mobile mechanism of trans-substitution mutually that the erase operations of Fig. 7 A, Fig. 7 B injects operation with the electronics of Fig. 3 A, Fig. 3 B.

Fig. 8 and Fig. 9 are the programming flow diagram of carrying out at delegation's non-volatile memory cells, and non-volatile memory cells is provided with and interconnects with NOR.In the bias voltage of Fig. 8 was provided with, word line 510,530 and 540 current potential were 0 volt (V), and the voltage of word line 520 is-5 volts (V), the current potential of bit line 504 be float or zero, the voltage of bit line 506 is 5 volts (V), and the current potential of substrate 502 is 0 volt (V).Show symbolically among the figure that the hole is programmed for the memory cell of word line 520 controls from bit line 506.In the bias voltage of Fig. 9 was provided with,

bit line

504 and 506 switched, and made that the current potential of bit line 504 (should be 506) is that float or zero, and the voltage of bit line 504 (should be 506) is 5 volts (V).Show symbolically among the figure that the hole is programmed for the memory cell of word line 520 controls from bit line 504.Therefore, the bias voltage of bit line is provided with the Partial charge capturing structure of control for the particular memory location programming.The operation that adds the single unit of hole to Fig. 4 A and Fig. 4 B is similar to the programming operation that NOR connects among Fig. 8,9 memory lines is carried out.

Figure 10 and Figure 11 are the reading operation figure that carries out at delegation's non-volatile memory cells, and non-volatile memory cells is provided with and interconnects with NOR.In the bias voltage of Figure 10 is provided with, word line 510,530 and 540 current potential are 0 volt (V), and the voltage of word line 520 is-10 volts (V), and the voltage of bit line 504 is 2 volts (V), the current potential of bit line 506 is that float or zero, and the current potential of substrate 502 is 0 volt (V).Symbolically show among the figure electric current from bit line 504 by node by the memory cell of word line 520 controls, flow to substrate 502.In the bias voltage of Figure 11 figure was provided with, the current potential of bit line switched, and made that the current potential of bit line 504 is that float or zero, and the current potential of bit line 506 is 2 volts (V).Show symbolically among the figure that electric current from the node of bit line 506 processes by the memory cell of word line 520 controls, flow to substrate 502.Therefore, the bias voltage of bit line is provided with the Partial charge capturing structure that control is used for the particular memory location programming.At the reading operation that the single unit of Figure 1A and Figure 1B is carried out, be the reading operation that is similar to the memory lines execution of Figure 10 and Figure 11 figure NOR connection.

Figure 12 and Figure 13 are the erase operations figure that carries out at non-volatile memory cells, and non-volatile memory cells is provided with and interconnects with virtual ground array (virtual ground array).In the bias voltage of Figure 12 was provided with,

word line

1210,1220,1230 and 1240 voltage were-8 volts (V), and

bit line

1203,1204,1205 and 1206 current potential float, and the voltage of substrate 1202 is 10 volts (V).The virtual ground array of Figure 13 is similar to the virtual ground array of Figure 12, except the direction that electronics moves.In the bias voltage array of Figure 13,

word line

1210,1220,1230 and 1240 voltage are 8 volts (V), and

bit line

1203,1204,1205 and 1206 current potential float, and the voltage of substrate 1202 is-10 volts (V).The erase operations of the corresponding Figure 12 virtual ground array of the erase operations of Fig. 7 A, the erase operations of the corresponding Figure 13 virtual ground array of the erase operations of Fig. 7 B.

Figure 14 figure is the programming flow diagram of carrying out at the non-volatile memory cells that virtual ground array is provided with.In the bias voltage of Figure 14 figure is provided with,

word line

1210,1230 and 1240 current potential are 0 volt (V), the voltage of word line 1220 is-5 volts (V),

bit line

1203,1204 and 1206 current potential float, the voltage of bit line 1206 (should be 1205) is to be 5 volts (V), and the current potential of substrate 1202 is 0 volt (V).Show symbolically among the figure that the hole is programmed for the some of the memory cell of word line 1220 and bit line 1205 controls from bit line 1205.The class of jobs that adds the hole among Fig. 4 A and Fig. 4 B is similar to the programming operation of Figure 14 figure.

Figure 15 figure is the reading operation figure that carries out at the non-volatile memory cells of virtual ground array.In the bias voltage of Figure 15 figure is provided with,

word line

1210,1230 and 1240 current potential are 0 volt (V), and the voltage of word line 1220 is-10 volts (V), and the voltage of bit line 1204 is to be 2 volts (V),

bit line

1203,1205 and 1206 current potential float, and the current potential of substrate 1202 is 0 volt (V).Show symbolically among the figure that electric current from the memory cell of bit line 1204 through being controlled by word line 1220 and bit line 1204, flow to substrate 1202.Reading operation among Figure 1A and Figure 1B is similar to the reading operation of Figure 15 figure.In certain embodiments, for reading the subclass of all bit lines.

Figure 16 and Figure 17 are the erase operations figure that carries out in array of non-volatile memory cells, the cell row that array of non-volatile memory cells interconnects and is set to connect.In the bias voltage of Figure 16 is provided with,

word line

1620,1630,1640,1650,1660,1670 and 1680 voltage are-20 volts (V),

word line

1610 and 1690 current potential float,

bit line

1603,1604,1605,1606 and 1607 current potential float, and the voltage of substrate 1602 is 10 volts (V).The memory cell of Figure 17 is similar to the memory cell of Figure 16, the direction that moves except electronics.In the bias voltage array of Figure 17,

word line

1620,1630,1640,1650,1660,1670 and 1680 current potential are 0 volt (V),

word line

1610 and 1690 current potential float,

bit line

1603,1604,1605,1606 and 1607 current potential float, and the voltage of substrate 1602 is-20 volts (V).The erase operations of the corresponding Figure 16 virtual ground array of the erase operations of Fig. 7 A, the erase operations of the corresponding Figure 17 virtual ground array of the erase operations of Fig. 7 B.

Figure 18 and Figure 19 are the erase operations figure that carries out in array of non-volatile memory cells, the cell row that array of non-volatile memory cells interconnects and is set to connect, and have floating end.In the bias voltage of Figure 18 is provided with,

word line

1820,1830,1840,1850,1860,1870 and 1880 voltage are-20 volts (V), the current potential of word line 1810 floats,

bit line

1803,1804,1805,1806 and 1807 current potential float, and the current potential of substrate 1802 is 0 volt (V).The memory cell of Figure 18 is similar to the memory cell of Figure 19, except the direction that electronics moves.In the bias voltage array of Figure 19,

word line

1820,1830,1840,1850,1860,1870 and 1880 current potential are 0 volt (V), the current potential of word line 1810 floats,

bit line

1803,1804,1805,1806 and 1807 current potential float, and the voltage of substrate 1802 is-20 volts (V).The erase operations of the corresponding Figure 18 virtual ground array of the erase operations of Fig. 7 A, the erase operations of the corresponding Figure 18 virtual ground array of the erase operations of Fig. 7 B.

Figure 20 is the programming flow diagram of carrying out in array of non-volatile memory cells, the cell row that array of non-volatile memory cells interconnects and is set to connect.In the bias voltage of Figure 20 is provided with,

word line

1620,1630,1640 (not being inconsistent with accompanying drawing), 1650,1660,1670 and 1680 voltage are 10 volts (V),

word line

1610 and 1690 voltage are 3 volts (V),

bit line

1603,1605 and 1606 current potential are 0 volt (V),

bit line

1604 and 1607 voltage are 3 volts (V), and the current potential of substrate 1602 is 0 volt (V).Electronics is programmed into by word line 1640 and

bit line

1603,1605 and 1606 memory cell of being controlled from

bit line

1603,1605 and 1606.

Figure 21 is the programming flow diagram of carrying out in array of non-volatile memory cells, the cell row that array of non-volatile memory cells interconnects and is set to connect, and have floating end.In the bias voltage of Figure 20 (should be Figure 21) is provided with, word line 1820,1830,1840 (not being inconsistent with accompanying drawing), 1850,1860,1870 and 1880 voltage are 10 volts (V), the voltage of word line 1810 is 3 volts (V), bit line 1803,1805 and 1806 current potential are 0 volt (V),

bit line

1804 and 1807 voltage are 3 volts (V), and the current potential of substrate 1802 is 0 volt (V).Electronics is programmed into by word line 1840 and bit line 1803,1805 and 1806 memory cell of being controlled from bit line 1803,1805 and 1806.

Figure 22,23 and 24 is the reading operation figure that carries out in array of non-volatile memory cells, the cell row that array of non-volatile memory cells interconnects and is set to connect.In the bias voltage of Figure 22 is provided with, the voltage of word line 1610 is 3 volts (V),

word line

1620 and 1630 voltage are 10 volts (V), the voltage of word line 1640 is-10 volts (V),

word line

1650,1660,1670,1680 and 1690 current potential are 0 volt (V),

bit line

1603,1604,1605,1606 and 1607 voltage are 3 volts (V), and the current potential of substrate 1602 is 0 volt (V).Symbolically show electric current among the figure from

bit line

1603,1604,1605,1606 and 1607, by the channel transistor row (pass transistor row) of word line 1610 controls, the memory cell through word line 1640 controls flow to substrate 1602.In the bias voltage of Figure 23 is provided with,

word line

1610,1620 and 1630 current potential are 0 volt (V), the voltage of word line 1640 is-10 volts (V),

word line

1650,1660,1670 and 1680 voltage are 10 volts (V), the voltage of word line 1690 is 3 volts (V),

bit line

1603,1604,1605,1606 and 1607, by the channel transistor row of word line 1690 controls, the memory cell through word line 1640 controls flow to substrate 1602.In the bias voltage of Figure 24 is provided with,

word line

1610 and 1690 voltage are 3 volts (V),

word line

1620,1630,1650,1660,1670 and 1680 voltage are 10 volts (V), the voltage of word line 1640 is-10 volts (V),

bit line

1603,1604,1605,1606 and 1607, by the channel transistor row of

word line

1610 and 1690 controls, the memory cell through word line 1640 controls flow to substrate 1602.Reading operation among Figure 1A and Figure 1B is similar to Figure 22,23 and 24 reading operation.Two current terminals of the memory cell that reads 1640 controls of electric current process word line among Figure 24 flow to substrate 1602, and a certain current terminal of the memory cell that reads 1640 controls of electric current process word line among Figure 22,23 flow to substrate 1602.Therefore, read electric current greater than the electric current that reads among Figure 22,23 among Figure 24.In certain embodiments, the subclass of all bit lines is read.

Figure 25 is the reading operation figure that carries out in array of non-volatile memory cells, the cell row that array of non-volatile memory cells interconnects and is set to connect, and have floating end.In the bias voltage of Figure 25 is provided with, the voltage of word line 1810 is 3 volts (V), word line 1820 and 1830 voltage are 10 volts (V), the voltage of word line 1840 is-10 volts (V),

word line

1850,1860,1870 and 1880 current potential are 0 volt (V),

bit line

1803,1804,1805,1806 and 1807 voltage are 3 volts (V), and the current potential of substrate 1802 is 0 volt (V).Symbolically show electric current among the figure from

bit line

1803,1804,1805,1806 and 1807, by the channel transistor row of word line 1810 controls, the memory cell through word line 1840 controls flow to substrate 1802.In certain embodiments, the subclass of all bit lines is read.

Figure 26 is the erase operations figure that carries out at non-volatile memory cells, the cell row that non-volatile memory cells interconnects and is set to connect.In the bias voltage of Figure 26 is provided with, the

grid

2620,2630,2640,2650,2660,2670 of memory cell and 2680 voltage are that-20 volts (V), the grid 2610 of memory cell and 2690 current potential float, the current potential of bit line 2603 floats, and the current potential of substrate 2602 is 0 volt (V).The memory cell of Figure 27 is similar to the memory cell of Figure 26, except the direction that electronics moves.In the bias voltage of Figure 27 is provided with,

word line

2620,2630,2640,2650,2660,2670 and 2680 current potential are 0 volt (V), the grid 2610 of memory cell and 2690 current potential float, and the current potential of bit line 2603 floats, and the voltage of substrate 2602 is-20 volts (V).The erase operations of the corresponding Figure 26 memory lines of the erase operations of Fig. 7 A, the capable erase operations of corresponding Figure 17 (27) the figure memory of the erase operations of Fig. 7 B.

Figure 28 and Figure 29 are the erase operations figure that carries out at non-volatile memory cells, the cell row that non-volatile memory cells interconnects and is set to connect, and have floating end.In the bias voltage of Figure 28 is provided with, the current potential of the grid 2810 of memory cell floats, the

grid

2820,2830,2840,2850,2860,2870 of memory cell and 2880 voltage are-20 volts (V), and the current potential of bit line 2803 floats, and the current potential of substrate 2802 is 0 volt (V).The memory lines of Figure 29 is similar to the memory lines of Figure 28, except the direction that electronics moves.In the bias voltage of Figure 29 is provided with, the current potential of the grid 2810 of memory cell floats, the

grid

2820,2830,2840,2850,2860,2870 of memory cell and 2880 current potential are 0 volt (V), and the current potential of word line 2803 floats, and the voltage of substrate 2802 is-20 volts (V).The erase operations of the corresponding Figure 28 memory lines of the erase operations of Fig. 7 A, the erase operations of the corresponding Figure 29 memory lines of the erase operations of Fig. 7 B.

Figure 30 is the programming flow diagram of carrying out at non-volatile memory cells, the cell row that non-volatile memory cells interconnects and is set to connect.In the bias voltage of Figure 30 is provided with, the grid 2610 of memory cell and 2690 voltage are 3 volts (V), the

grid

2620,2630,2650,2660,2670 of memory cell and 2680 voltage are 10 volts (V), the voltage of the grid 2640 of memory cell is 20 volts (V), the voltage of bit line 2603 is 0 (not being inconsistent with accompanying drawing) volt (V), and the current potential of substrate 2602 is 0 volt (V).Electronics is programmed into the memory cell of being controlled by word line 2640 from bit line 2603.

Figure 31 is the programming flow diagram of carrying out at non-volatile memory cells, the cell row that non-volatile memory cells interconnects and is set to connect, and have floating end.In the bias voltage of Figure 31 is provided with, the voltage of the grid 2810 of memory cell is 3 volts (V), the

grid

2820,2830,2850,2860,2870 of memory cell and 2880 voltage are 10 volts (V), the voltage of the grid 2840 of memory cell is 20 volts (V), the voltage of bit line 2803 is 0 (not being inconsistent with accompanying drawing) volt (V), and the current potential of substrate 2802 is 0 volt (V).Electronics is programmed into the memory cell of being controlled by word line 2840 from bit line 2803.

Figure 32,33 and 34 is the reading operation figure that carries out at non-volatile memory cells, the cell row that array of non-volatile memory cells interconnects and is set to connect.In the bias voltage of Figure 32 is provided with, the voltage of the grid 2610 of memory cell is 3 volts (V), the grid 2620 of memory cell and 2630 voltage are 10 volts (V), the voltage of the grid 2640 of memory cell is-10 volts (V), the

grid

2650,2660,2670,2680 of memory cell and 2690 current potential are 0 volt (V), the voltage of bit line 2603 is 3 volts (V), and the current potential of substrate 2602 is 0 (not being inconsistent with an accompanying drawing) volt (V).Symbolically show electric current among the figure from bit line 2603,,, flow to substrate 2602 through memory cell 2640 by channel transistor 2610.In the bias voltage of Figure 33 is provided with, the

grid

2610,2620 of memory cell and 2630 current potential are 0 volt (V), the voltage of the grid 2640 of memory cell is-10 volts (V), the

grid

2650,2660,2670 of memory cell and 2680 voltage are 10 volts (V), the voltage of word line (should be the grid of memory cell) 2690 is 3 volts (V), the voltage of bit line 2603 is 3 volts (V), and the current potential of substrate 2602 is 0 (not being inconsistent with an accompanying drawing) volt (V).Symbolically show electric current among the figure from bit line 2603,,, flow to substrate 2602 through memory cell 2640 by channel transistor 2690.In the bias voltage of Figure 34 is provided with, the grid 2610 of memory cell and 2690 current potential are 3 volts (V), the

grid

2620,2630,2650,2660,2670 of memory cell and 2680 current potential are 10 volts (V), the voltage of the grid 2640 of memory cell is-10 volts (V), the voltage of bit line 2603 is 3 volts (V), and the current potential of substrate 2602 is 0 volt (V).Symbolically show electric current among the figure from bit line 2603,,, flow to substrate 2602 through memory cell 2640 by channel transistor 2610 and 2690.Reading operation among Figure 1A and Figure 1B is similar to Figure 32,33 and 34 reading operation.Two current terminals that read electric current process memory cell 2640 among Figure 34 flow to substrate 2602, and a certain current terminal that reads electric current process memory cell 2640 among Figure 32,33 flow to substrate 2602.Therefore, read electric current greater than the electric current that reads among Figure 32,33 among Figure 34.

Figure 35 is the reading operation figure that carries out at non-volatile memory cells, the cell row that non-volatile memory cells interconnects and is set to connect, and have floating end.In the bias voltage of Figure 35 is provided with, the voltage of the grid 2810 of memory cell is 3 volts (V), the grid 2820 of memory cell and 2830 voltage are 10 volts (V), the voltage of the grid 2840 of memory cell is-10 volts (V), the

grid

2850,2860,2870 of memory cell and 2880 voltage are 0 volt (V), the voltage of bit line 2803 is 3 volts (V), and the current potential of substrate 2802 is 0 volt (V).Symbolically show electric current among the figure from bit line 2803,,, flow to substrate 2802 through memory cell 2840 by channel transistor 2810.

Figure 36 A to Figure 36 C illustrates the sketch of other non-volatile memory cells with different charge storing structures.Figure 36 A illustrates the structure of a splitting bar (split-gate), has first grid 1020, second grid 1010, charge storing structure 1030 and oxide layer 1040.Figure 36 B illustrates the non-volatile memory cells that is similar to nonvolatile memory among Fig. 1, and the shown non-volatile memory cells of Figure 36 B has the floating grid 1030 that forms with polysilicon usually.Figure 36 C illustrates a non-volatile memory cells that is similar to nonvolatile memory among Fig. 1, and the shown person of Figure 36 C has nanoparticle (nanoparticle) charge storing structure 1030.

Figure 37 is the sketch with integrated circuit of charge capturing storage unit array and control circuit.Integrated circuit 3750 is included in the memory array 3700 of using nonvolatile memory to carry out on the Semiconductor substrate.Memory array 3700 may interconnect in the mode of parallel connection, series connection or virtual ground array.Column decoder (decoder) 3701 and a plurality of word line 3702 couplings, and a plurality of word line 3702 is provided with along row in memory array 3700.Row decoder 3703 and plurality of bit lines 3704 couplings, and a plurality of word line 3704 follows setting in memory array 3700.Provide row decoder 3703 and column decoder 3701 addresses in bus 3705.Sensing amplifier in square 3706 and information input structure are coupled with row decoder 3703 by bus 3707.Input/output end port provides information from the integrated circuit 3750 by information incoming line 3711, or inner or outside out of Memory provides information to the information input structure the square 3706 from integrated circuit 3750.Information by information output line 3715 with sensing amplifier in the square 3706 is provided to input/output end port on the integrated circuit 3750, or is provided to integrated circuit 3750 inner or outside out of Memory targets.Bias voltage be provided with stater 3709 with similar can interband the Current Control bias voltage supply voltage 3708 is set, confirm voltage as erase-verifying and programming, and for programming, wipe and the setting of reading cells.

In other embodiments, can ignore the transistor of choosing.

By reference front description technique and example the present invention is shown, scrutable is that this row example is only nonrestrictive for illustrative.In the scope of the present invention's spirit and following claims, other variant and combination and be those skilled in the art's understandings easily.

Description of drawings

Figure 1A is the sketch of charge capturing storage unit, and the reading operation of carrying out at the Partial charge capturing storage unit corresponding to source terminal is shown;

Figure 1B is the sketch of charge capturing storage unit, and the reading operation of carrying out at the Partial charge capturing storage unit corresponding to drain electrode end is shown;

Fig. 2 A illustrates the sensing range figure of typical non-volatile memory cell;

Fig. 2 B illustrates when when the charge capturing storage unit of other parts is carried out the programming operation, the sensing range figure of memory cell;

Fig. 3 A is the sketch of charge capturing storage unit, is illustrated in the channel hot electron injection that a part of charge capturing storage unit is carried out;

Fig. 3 B is the sketch of charge capturing storage unit, and the channel hot electron that is illustrated in the charge capturing storage unit execution of other parts injects;

Fig. 4 A is the sketch of charge capturing storage unit, is illustrated in that the band hot hole injects between the energy that a part of charge capturing storage unit carries out;

Fig. 4 B is the sketch of charge capturing storage unit, is illustrated in that the band hot hole injects between the energy that the charge capturing storage unit of other parts carries out;

The erase operations figure of Fig. 5 for carrying out at delegation's non-volatile memory cells by the bias voltage setting, non-volatile memory cells is provided with and interconnects with NOR;

Fig. 6 is for being provided with the erase operations figure that carries out at delegation's non-volatile memory cells by another bias voltage, and non-volatile memory cells is provided with and interconnects with NOR;

Fig. 7 A is the sketch of charge capturing storage unit, and the erase operations of carrying out in the charge-trapping structure corresponding to Fig. 5 is shown;

Fig. 7 B is the sketch of charge capturing storage unit, and it illustrates the erase operations of carrying out in the charge-trapping structure corresponding to Fig. 6;

Fig. 8 is the programming flow diagram of carrying out at delegation's non-volatile memory cells, and non-volatile memory cells is provided with and interconnects with NOR, and the hole adds the memory cell of part;

Fig. 9 is the programming flow diagram of carrying out at delegation's non-volatile memory cells, and non-volatile memory cells is provided with and interconnects with NOR, and the hole adds another memory cell partly;

Figure 10 is the reading operation figure that carries out at delegation's non-volatile memory cells, and non-volatile memory cells is provided with and interconnects with NOR, reads a part of memory cell;

Figure 11 figure is the reading operation figure that carries out at delegation's non-volatile memory cells, and non-volatile memory cells is provided with and interconnects with NOR, reads another memory cell partly;

Figure 12 is for being provided with the erase operations figure that carries out at non-volatile memory cells by other bias voltage, and non-volatile memory cells interconnects with the virtual ground array setting;

The erase operations figure of Figure 13 for carrying out at non-volatile memory cells by the bias voltage setting, non-volatile memory cells interconnects with the virtual ground array setting;

Figure 14 figure is the programming flow diagram of carrying out at non-volatile memory cells, and non-volatile memory cells interconnects with the virtual ground array setting, and the hole adds the memory cell of part;

Figure 15 figure is the programming flow diagram of carrying out at the non-volatile memory cells that virtual ground array is provided with;

The erase operations figure of Figure 16 for carrying out in array of non-volatile memory cells by the bias voltage setting, the cell row that array of non-volatile memory cells interconnects and is set to connect;

Figure 17 is for being provided with the erase operations figure that carries out in array of non-volatile memory cells, the cell row that array of non-volatile memory cells interconnects and is set to connect by another bias voltage;

The erase operations figure of Figure 18 for carrying out in array of non-volatile memory cells by a bias voltage setting, the cell row that array of non-volatile memory cells interconnects and is set to connect, and have floating end;

The erase operations figure of Figure 19 for carrying out in array of non-volatile memory cells by another bias voltage setting, the cell row that array of non-volatile memory cells interconnects and is set to connect, and have floating end;

Figure 20 is the programming flow diagram of carrying out in array of non-volatile memory cells, the cell row that array of non-volatile memory cells interconnects and is set to connect;

Figure 21 is the programming flow diagram of carrying out in array of non-volatile memory cells, the cell row that array of non-volatile memory cells interconnects and is set to connect, and have floating end;

Figure 22 is the reading operation figure that carries out in array of non-volatile memory cells, and the cell row that array of non-volatile memory cells interconnects and is set to connect is in an end operation of series connection;

Figure 23 is the reading operation figure that carries out in array of non-volatile memory cells, and the cell row that array of non-volatile memory cells interconnects and is set to connect is in the other end operation of series connection;

Figure 24 is the reading operation figure that carries out in array of non-volatile memory cells, and the cell row that array of non-volatile memory cells interconnects and is set to connect is in the two ends operation of series connection;

Figure 25 is the reading operation figure that carries out in array of non-volatile memory cells, the cell row that array of non-volatile memory cells interconnects and is set to connect, and have floating end;

The erase operations figure of Figure 26 for carrying out at non-volatile memory cells by a bias voltage setting, the cell row that non-volatile memory cells interconnects and is set to connect;

Figure 27 is for being provided with the erase operations figure that carries out at non-volatile memory cells, the cell row that non-volatile memory cells interconnects and is set to connect by another bias voltage;

The erase operations figure of Figure 28 for carrying out at non-volatile memory cells by a bias voltage setting, the cell row that non-volatile memory cells interconnects and is set to connect, and have floating end;

The erase operations figure of Figure 29 for carrying out at non-volatile memory cells by another bias voltage setting, the cell row that non-volatile memory cells interconnects and is set to connect, and have floating end;

Figure 30 is the programming flow diagram of carrying out at non-volatile memory cells, the cell row that non-volatile memory cells interconnects and is set to connect;

Figure 31 is the programming flow diagram of carrying out at non-volatile memory cells, the cell row that non-volatile memory cells interconnects and is set to connect, and have floating end;

Figure 32 is the reading operation figure that carries out at non-volatile memory cells, and the cell row that array of non-volatile memory cells interconnects and is set to connect is in an end operation of series connection;

Figure 33 is the reading operation figure that carries out at non-volatile memory cells, and the cell row that array of non-volatile memory cells interconnects and is set to connect is in the other end operation of series connection;

Figure 34 is the reading operation figure that carries out at non-volatile memory cells, and the cell row that array of non-volatile memory cells interconnects and is set to connect is in the two ends operation of series connection;

Figure 35 is the reading operation figure that carries out at non-volatile memory cells, the cell row that non-volatile memory cells interconnects ` and is set to connect, and have floating end;

Figure 36 A to Figure 36 C illustrates the sketch of other non-volatile memory cells with different charge storing structures;

Figure 37 is the sketch with integrated circuit of charge capturing storage unit array and control circuit.

The figure number explanation

110 grids, 120 top dielectric structures

130 charge-trapping structures, 134 electronics

140 end dielectric structure 150n+ doped source

160n+ doped-drain 170p doped substrate regions

210 first 220 second

250 memory cell, 433 electric charges

434 holes

510,520,530,540,1210,1220,1230,1240,1610,1620,1630,1640,1650,1660,1670,1680,1690,1810,1820,1830,1840,1850,1860,1870,1880 word lines

504,506,1203,1204,1205,1206,1603,1604,1605,1606,1607,1803,1804,1805,1806,1807,2603,2803 bit lines

502,1202,1602,1802,2602,2802 substrates

2610,2620,2630,2640,2650,2660,2670,2680,2690,2810,2820,2830,2840,2850,2860,2870,2880 grids

1010 second grids, 1020 first grids

1030 charge storing structures, 1040 oxide layers

3700 memory arrays, 3701 column decoders

3702 a plurality of word line 3703 row decoders

3704 plurality of bit lines, 3705 buses

3706 squares, 3707 buses

3709 bias voltages are provided with stater 3711 information incoming lines

3750 integrated circuits, 3715 information output lines

Claims

1, a kind of method of operating nonvolatile memory array, this nonvolatile memory array utilizes charge storage state to come store information, this nonvolatile memory comprises the non-volatile memory cells that is arranged in rows, each this non-volatile memory cells is included in first and second live stream node in the area, and comprise charge storing structure and one or more dielectric structure, at least one part of these one or more dielectric structures is between this charge storing structure and a gate-voltage source, and at least one part of these one or more dielectric structures is between this area and this charge storing structure, and this method comprises:

Carry out one or more task memories, comprising:

A bit line is applied bit line bias, and this bit line is electrically connected with first end of one of delegation non-volatile memory cells, the behavior arranged in series, make consecutive storage unit in this row adjacent this first and this second live stream node be electrically connected; And

Second end of one of this row non-volatile memory cells is floated.

2, the method for claim 1, wherein these one or more task memories comprise a programming operation, and between this programming operational period, this bit line bias is electrically connected with first end of one of delegation non-volatile memory cells, and it floats with this second end that makes this row non-volatile memory cells and takes place simultaneously.

3, the method for claim 1, wherein these one or more task memories comprise a reading operation, and during this reading operation, this bit line bias is electrically connected with first end of one of delegation non-volatile memory cells, and it floats with this second end that makes this row non-volatile memory cells and takes place simultaneously.

4, the method for claim 1, wherein these one or more task memories comprise a reading operation, and during this reading operation, this bit line bias is electrically connected with first end of one of delegation non-volatile memory cells, it floats with this second end that makes this row non-volatile memory cells and takes place simultaneously

Wherein, carrying out this reading operation is by measuring energy interband current component, to determine at least one this charge storage state.

5, the method for claim 1, wherein this area is the trap in Semiconductor substrate.

6, the method for claim 1, wherein each charge storage state stores one.

7, the method for claim 1, wherein each charge storage state stores a plurality of positions.

8, method as claimed in claim 15, wherein each charge storing structure is a nano crystal material.

9, the method for claim 1, wherein this charge storing structure is a nano crystal material, and wipe and the program bias setting, electronics is penetrated to this charge storing structure and from this charge storing structure by injecting electronics, to change this charge storage state.

10, the method for claim 1, wherein each charge storing structure is a kind of charge-trapping material.

11, the method for claim 1, wherein this charge storing structure is a kind of charge-trapping material, and wipe and the program bias setting, by inject electronics to this charge storing structure and injected hole to this charge storing structure, to change this charge storage state.

12, the method for claim 1, wherein each charge storing structure is a floating grid.

13, the method for claim 1, wherein each charge storing structure is a floating grid, and wipes and the program bias setting, reaches to this charge storing structure by the injection electronics and from this charge storing structure electronics is penetrated, to change this charge storage state.

14, a kind of nonvolatile memory integrated circuit of utilizing charge storage state to come store information comprises:

Nonvolatile memory array comprises plural line storage unit, and each this memory cell comprises:

Area has first live stream node and second live stream node;

Charge storing structure; And

One or more dielectric structures, these one or more dielectric structure at least a portion are between this charge storing structure and this area, and these one or more dielectric structure at least a portion are between this charge storing structure and gate-voltage source;

Wherein, each row and had first end and second end with arranged in series during this plural number was capable, and adjacent this first and this second live stream node of adjacent described memory cell in this each row are electrically connected;

Plurality of bit lines, each this bit line have a corresponding row in this plural number line storage unit, and between at least one operational period, at least one bit line is electrically connected with this first end of this corresponding row, and this second end of this corresponding row floats; And

A plurality of word lines offer this plurality of memory cells with this grid voltage.

15, integrated circuit as claimed in claim 14 also comprises:

A plurality of first channel transistors;

Between this at least one operational period, at least one bit line is via one of these a plurality of first channel transistors, and is electrically connected with this first end of this corresponding row.

16, integrated circuit as claimed in claim 14, wherein this at least one task memory comprises the programming operation, and between this programming operational period, this at least one bit line is electrically connected with this first end of this corresponding row of this non-volatile memory cells, and this second end of this corresponding row floats.

17, integrated circuit as claimed in claim 14, wherein these one or more task memories comprise reading operation, and during this reading operation, this at least one bit line is electrically connected with this first end of this corresponding row of non-volatile memory cells, and this second end of this corresponding row floats.

18, integrated circuit as claimed in claim 14, wherein these one or more task memories comprise reading operation, and during this reading operation, this at least one bit line is electrically connected with this first end of this corresponding row of non-volatile memory cells, and this second end of this corresponding row floats

Wherein carrying out this reading operation is by measuring energy interband current component, to determine at least one this charge storage state.

19, integrated circuit as claimed in claim 14, wherein each this charge storage state is to this charge storing structure that one of should memory cell.

20, integrated circuit as claimed in claim 14, wherein this area is the trap in Semiconductor substrate.

21, integrated circuit as claimed in claim 14, wherein each this charge storage state stores one.

22, integrated circuit as claimed in claim 14, wherein each charge storage state stores a plurality of positions.

23, integrated circuit as claimed in claim 14, wherein each charge storing structure is a nano crystal material.

24, integrated circuit as claimed in claim 14, wherein this charge storing structure is a nano crystal material, and wipe and the program bias setting, reach to this charge storing structure by the injection electronics and electronics is penetrated, to change this charge storage state from this charge storing structure.

25, integrated circuit as claimed in claim 14, wherein each charge storing structure is the charge-trapping material.

26, integrated circuit as claimed in claim 14, wherein this charge storing structure is the charge-trapping material, and wipe and the program bias setting, by inject electronics to this charge storing structure and injected hole to this charge storing structure, to change this charge storage state.

27, integrated circuit as claimed in claim 14, wherein each charge storing structure is a floating grid.

28, integrated circuit as claimed in claim 14, wherein each charge storing structure is a floating grid, and implement to wipe and the program bias setting, reach to this charge storing structure by the injection electronics and electronics is penetrated, to change this charge storage state from this charge storing structure.

29, a kind of integrated circuit of nonvolatile memory, the integrated circuit of this nonvolatile memory utilizes charge storage state to come store information, comprising:

The memory cell of delegation, each memory cell comprises:

Area has first live stream node and second live stream node;

Charge storing structure; And

Wherein, this row is with arranged in series, and has first end and second end, and adjacent this first and this second live stream node of consecutive storage unit in this row are electrically connected;

Bit line, between at least one operational period, this bit line is electrically connected with this first end of this row, and this second end of this row floats; And

Word line provides this grid voltage to this line storage unit.

30, integrated circuit as claimed in claim 29 also comprises:

First channel transistor;

Between this at least one operational period, this bit line is via this first channel transistor, and is electrically connected with this first end of this row.

31, integrated circuit as claimed in claim 29, wherein these one or more task memories comprise the programming operation, and between this programming operational period, this bit line is electrically connected with this first end of this row non-volatile memory cells, and this second end of this row floats.

32, integrated circuit as claimed in claim 29, wherein these one or more task memories comprise reading operation, and during this reading operation, this bit line is electrically connected with this first end of this row non-volatile memory cells, and this second end of this row floats.

33, integrated circuit as claimed in claim 29, wherein these one or more task memories comprise reading operation, and during this reading operation, this bit line is electrically connected with this first end of this row non-volatile memory cells, and this second end of this row floats,

34, integrated circuit as claimed in claim 29, wherein each this charge storage state is to this charge storing structure that one of should memory cell.

35, integrated circuit as claimed in claim 29, wherein this area is the trap in Semiconductor substrate.

36, integrated circuit as claimed in claim 29, wherein each this charge storage state stores one.

37, integrated circuit as claimed in claim 29, wherein each charge storage state stores a plurality of positions.

38, integrated circuit as claimed in claim 29, wherein each charge storing structure is a nano crystal material.

39, integrated circuit as claimed in claim 29, wherein this charge storing structure is a nano crystal material, and wipe and the program bias setting, reach to this charge storing structure by the injection electronics and electronics is penetrated, to change this charge storage state from this charge storing structure.

40, integrated circuit as claimed in claim 29, wherein each charge storing structure is the charge-trapping material.

41, integrated circuit as claimed in claim 29, wherein this charge storing structure is the charge-trapping material, and wipe and the program bias setting, by inject electronics to this charge storing structure and injected hole to this charge storing structure, to change this charge storage state.

42, integrated circuit as claimed in claim 29, wherein each charge storing structure is a floating grid.

43, integrated circuit as claimed in claim 29, wherein each charge storing structure is a floating grid, and implement to wipe and the program bias setting, reach to this charge storing structure by the injection electronics and electronics is penetrated, to change this charge storage state from this charge storing structure.