CN1949485A - Semiconductor structure and mfg. method thereof - Google Patents
Semiconductor structure and mfg. method thereof Download PDFInfo
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- CN1949485A CN1949485A CN 200510113377 CN200510113377A CN1949485A CN 1949485 A CN1949485 A CN 1949485A CN 200510113377 CN200510113377 CN 200510113377 CN 200510113377 A CN200510113377 A CN 200510113377A CN 1949485 A CN1949485 A CN 1949485A
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Abstract
The invention is a semiconductor structure located in the cutting street of a wafer and circling the chip region of the wafer, comprising multiple dielectric layers configured in the cutting street and plural patternized metal plates in each dielectric layer, where the patternized metal plate in each dielectric layer extends into part of the next dielectric layer.
Description
Technical field
The present invention relates to a kind of semiconductor structure and preparation method thereof, relate in particular to semiconductor structure that prevents the chip be full of cracks and preparation method thereof.
Background technology
Along with science and technology is maked rapid progress, integrated circuit component has almost reached immanent stage.Yet, the flow process that integrated circuit component is produced is very complicated, consist essentially of integrated circuit (IC) design, wafer manufacturing, wafer sort and wafer package four megastages such as (package), and approximately need be through hundreds of different steps, about one, bimestrial time consuming time just is accomplished.
For volume production and reduce manufacturing cost, wafer diameter develops 12 cun by four cun, five cun, six cun of the past, makes can make more multicore sheet simultaneously on the wafer.The manufacture process of integrated circuit component mainly is divided into three phases: the encapsulation of the manufacturing of silicon, the making of integrated circuit and integrated circuit component etc.In the manufacturing process of integrated circuit, can on wafer cutting path, form many monitoring patterns, for example alignment mark, supervision/measured pattern, testing electrical property pattern and production code member or the like usually.In addition, encapsulation can be said so and be finished the final stage of integrated circuit finished product, and its technology comprises quite complicated step, and the first step is exactly the wafer cutting.
On a silicon wafer, have a plurality of horizontal resection roads that are parallel to each other (scribe line) and a plurality of orthogonal perpendicular cuts road usually, in order to a plurality of chips are separated from one another.After the element on the wafer completes, utilize the Cutting Road cutting of diamond cutter (diamond blade), to obtain a plurality of chips along wafer.Owing to be coated with multiple different material layer on the wafer, therefore during the wafer cutting operation, be positioned at the material layer on the Cutting Road, can chap or the slight crack equivalent damage and on Cutting Road, produce because of the difference to some extent of material character each other.
Particularly, above-mentioned mentioned damage, at close chip corner place, promptly the Cutting Road infall can be the most serious, and form area of stress concentration.And, the chip that this corner is damaged, after finishing packaging technology, also can be because of the effect of some external stress, for example cold and hot variations in temperature, and make packaging body in the problem that causes slight crack expansion or delamination (delamination) at the interface, and wherein delamination is easy to generate especially at the interface of low dielectric constant material layer and other layers, and this is because the common not good cause of the adhesive force of low dielectric constant material layer and other dielectric layers or metal level.In the useful life that so will cause component failure or reduce element, cause expending of cost on the technology, and influence follow-up packaging technology and element reliability.
Summary of the invention
The purpose of this invention is to provide a kind of semiconductor structure, can avoid during the wafer cutting operation, cause chip corner to produce be full of cracks or slight crack.
Another object of the present invention provides a kind of manufacture method of semiconductor structure, utilizes the metal that forms in the dielectric layer around the chip, avoids chip corner to produce be full of cracks or slight crack.
The present invention proposes a kind of semiconductor structure, and it is positioned in the Cutting Road district of wafer, and around the chip region of wafer, and this semiconductor structure comprises and is disposed at the multilayer dielectric layer in the Cutting Road district in regular turn and is disposed at a plurality of pattern metal in each floor dielectric layer.Wherein, the pattern metal in each layer dielectric layer extends to and is arranged in the part dielectric layer of one deck down.
According to the described semiconductor structure of the embodiment of the invention, above-mentioned pattern metal has first and second portion, and second portion is positioned at the first below.
According to the described semiconductor structure of the embodiment of the invention, the width of above-mentioned first is identical with the width of second portion.
According to the described semiconductor structure of the embodiment of the invention, the width of above-mentioned first is greater than the width of second portion.
According to the described semiconductor structure of the embodiment of the invention, the pattern metal of one dielectric layer is staggered arrangement to the pattern metal in above-mentioned each layer dielectric layer with being arranged in down.
According to the described semiconductor structure of the embodiment of the invention, the pattern metal of one dielectric layer is connected the pattern metal in above-mentioned each layer dielectric layer with being arranged in down.
According to the described semiconductor structure of the embodiment of the invention, the material of above-mentioned pattern metal for example is a copper.
According to the described semiconductor structure of the embodiment of the invention, above-mentioned dielectric layer material for example is low-k (low-k) material.
According to the described semiconductor structure of the embodiment of the invention, above-mentioned advanced low-k materials for example be the fluorine silex glass (fluorosilicate, FSG).
The present invention also proposes a kind of manufacture method of semiconductor structure, at first, provides a substrate.Then, on substrate, form first dielectric layer.Then, on first dielectric layer, form second dielectric layer.Afterwards, form a plurality of pattern metal in second dielectric layer, these pattern metal extend in the part of first dielectric layer at least.
According to the manufacture method of the described semiconductor structure of the embodiment of the invention, the formation method of above-mentioned pattern metal for example is prior to forming a plurality of irrigation canals and ditches in second dielectric layer.Then, form a plurality of openings in second dielectric layer of irrigation canals and ditches below, these openings extend in the part of first dielectric layer at least.Afterwards, in irrigation canals and ditches and opening, insert metal material.
According to the manufacture method of the described semiconductor structure of the embodiment of the invention, the formation method of above-mentioned pattern metal for example is prior to forming a plurality of openings in second dielectric layer.Then, in part second dielectric layer around these open top, form a plurality of irrigation canals and ditches.Afterwards, in irrigation canals and ditches and opening, insert metal material.
According to the manufacture method of the described semiconductor structure of the embodiment of the invention, the material of above-mentioned pattern metal for example is a copper.
According to the manufacture method of the described semiconductor structure of the embodiment of the invention, the first above-mentioned dielectric layer and the second dielectric layer material for example are advanced low-k materials.
According to the manufacture method of the described semiconductor structure of the embodiment of the invention, above-mentioned advanced low-k materials for example is the fluorine silex glass.
The present invention is because of in each layer dielectric layer around the chip, all be formed with a plurality of pattern metal, utilize these pattern metal can avoid wafer when cutting, because stress influence causes the interface between each dielectric layer to produce the crack and chaps around chip, especially the corner of chip, and the useful life that makes component failure or reduce element, and cause expending of production cost, and then influence follow-up packaging technology and element reliability.In addition, semiconductor structure of the present invention does not need to increase extra processing step in the manufacture process of wafer, therefore can not increase manufacturing cost in addition.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A is the top view according to the semiconductor structure that the embodiment of the invention illustrated;
Figure 1B is the generalized section of a kind of semiconductor structure of being illustrated according to I-I ' section among Figure 1A;
Fig. 1 C is the generalized section according to the another kind of semiconductor structure that the embodiment of the invention illustrated;
Fig. 1 D is the generalized section according to another semiconductor structure that the embodiment of the invention illustrated;
Fig. 2 is according to the semiconductor structure that the embodiment of the invention illustrated and the top view of chip region;
Fig. 3 A to Fig. 3 C is the making flow process profile according to the semiconductor structure that the embodiment of the invention illustrated.
The main element symbol description
30: grid
31: gate dielectric layer
32: source/drain regions
33a, 33b: irrigation canals and ditches
34a, 34b: opening
100,100 ', 100 ": semiconductor structure
101,301: wafer
102,302: the Cutting Road district
104,304: chip region
106,108,110,306,308,310: dielectric layer
112,112a, 112b, 312,314: patterned metal layer
113,313: the interface
300: substrate
307,309,311: dual-damascene structure
Embodiment
Figure 1A is the top view according to the semiconductor structure that the embodiment of the invention illustrated.Figure 1B is the generalized section of a kind of semiconductor structure of being illustrated according to I-I ' section among Figure 1A.Fig. 1 C is the generalized section according to the another kind of semiconductor structure that the embodiment of the invention illustrated.Fig. 1 D is the generalized section according to another semiconductor structure that the embodiment of the invention illustrated.Fig. 2 is according to the semiconductor structure that the embodiment of the invention illustrated and the top view of chip region.
Please be simultaneously with reference to Figure 1A, Figure 1B and Fig. 2, semiconductor structure 100 is positioned in the Cutting Road district 102 of wafer 101, and, wherein for example have metal-oxide semiconductor (MOS) (MOS) transistor, other semiconductor elements or semiconductor circuit on the chip region 104 around the chip region 104 of wafer 101.Semiconductor structure 100 comprises dielectric layer 106,108,110 and pattern metal 112.Dielectric layer 106,108,110 is disposed in the Cutting Road district 102 in regular turn, and the material of dielectric layer 106,108,110 can be an advanced low-k materials, and wherein advanced low-k materials for example is the fluorine silex glass.The material of pattern metal 112 for example is a copper.Pattern metal 112 in each layer dielectric layer extends to respectively and is arranged in the part dielectric layer of one deck down.For instance, the pattern metal 112 that is arranged in dielectric layer 110 extends to the part dielectric layer 108 that is arranged in the below, and the pattern metal 112 that is arranged in dielectric layer 108 then extends to the part dielectric layer 106 that is arranged in the below.The purpose that pattern metal 112 extends to down the part dielectric layer of one deck is, when wafer 101 when cutting, because the effect of stress, interface 113 between each layer dielectric layer is easy to generate the be full of cracks or the phenomenon of delamination, and the pattern metal 112 that is arranged in each dielectric layer can stop the crack to continue to extend and cause the infringement of chip towards chip region 104.In the present embodiment, the pattern metal 112 in two layers of dielectric layer for example is to arrange in the mode that intermeshes up and down.
In addition, in another embodiment, when the pattern metal 112 in the semiconductor structure 100 ' extends to the part dielectric layer that is arranged in following one deck, also can link to each other with the pattern metal 112 that is arranged in following one dielectric layer, and directly extend in the dielectric layer 106 by dielectric layer 110, please refer to Fig. 1 C.In addition, please refer to Fig. 1 D, in another embodiment, semiconductor structure 100 " in pattern metal 112 also can be formed by metal 112a and metal 112b; metal 112a is positioned at metal 112b top; and the width of metal 112a is greater than the width of metal 112b, and wherein the material of metal 112a and metal 112b for example is a copper.
Fig. 3 A to Fig. 3 C is the making flow process profile according to the semiconductor structure that the embodiment of the invention illustrated.At first, please refer to Fig. 3 A, wafer 301 has Cutting Road district 302 and chip region 304.Be positioned on the substrate 300 of chip region 304 and be formed with MOS transistor, this MOS transistor comprises grid 30, gate dielectric layer 31 and source/drain regions 32.Then, form dielectric layer 306 on substrate 300, the material of dielectric layer 306 for example is an advanced low-k materials, and wherein advanced low-k materials for example is the fluorine silex glass.Then, forming metal interconnecting structure in dielectric layer 306, for example is dual damascene (dualdamascene) structure 307, and dual-damascene structure 307 electrically connects with source/drain regions 32, and wherein the material of dual-damascene structure 307 for example is a copper.
Then, please refer to Fig. 3 B, form dielectric layer 308 on dielectric layer 306, the material of dielectric layer 308 for example is an advanced low-k materials, and wherein advanced low-k materials for example is the fluorine silex glass.Then, form dual-damascene structure 309 and pattern metal 312 in dielectric layer 308, wherein the material of pattern metal 312 for example is a copper.It should be noted that pattern metal 312 and dual-damascene structure 309 form in same processing step simultaneously, the formation method for example is to carry out the etching step first time earlier, to form irrigation canals and ditches 33a and 33b in dielectric layer 308.Then, carry out the etching step second time, in the dielectric layer 308 of irrigation canals and ditches 33a, 33b below, to form opening 34a, 34b.It should be noted that, in this step, the dielectric layer 308 that is positioned at irrigation canals and ditches 33a below stops when being etched to dual-damascene structure 307, the dielectric layer 308 that is positioned at irrigation canals and ditches 33b below then can be continued downward etching dielectric layer 306 to one degree of depth, this degree of depth for example is between 200 ～3000 , is preferably 1500 .Afterwards, on substrate, form layer of metal material (not illustrating) and fill up irrigation canals and ditches 33a, 33b and opening 34a, 34b.Then, for example carry out planarisation step, to form dual-damascene structure 309 and pattern metal 312 with chemical mechanical polishing method.
In addition, in another embodiment, carry out first time etching step earlier in dielectric layer 308, to form opening 34a, 34b.Then, in the part dielectric layer 308 around opening 34a, the 34b top, form irrigation canals and ditches 33a, 33b again.Afterwards, in irrigation canals and ditches 33a, 33b and opening 34a, 34b, form dual-damascene structure 309 and pattern metal 312 again.
Afterwards, please refer to Fig. 3 C, form dielectric layer 310 on dielectric layer 308, the material of dielectric layer 310 for example is an advanced low-k materials, and wherein advanced low-k materials for example is the fluorine silex glass.Then, in dielectric layer 310, form dual-damascene structure 311 and pattern metal 314 in an identical manner.What deserves to be mentioned is, formed pattern metal 314 is staggered with pattern metal 312 below being positioned at and arranges in this step, therefore, when the effect of wafer 101 stress cutting causes the interface 313 between each layer dielectric layer to produce be full of cracks or delamination, can stop the crack to continue to extend and cause the infringement of chip by pattern metal 312,314 towards chip region 304.
It should be noted that, be to be that the present invention will be described for example in above embodiment with semiconductor structure with three layers of dielectric layer, be not in order to qualification the present invention, four layers, five layers or more multi-layered dielectric layer are adopted in the rete collocation in visual demand of user and the chip region.
In sum, when wafer cuts, can and chap around chip in generation crack, the interface between each dielectric layer because of stress influence, especially the corner of chip, therefore semiconductor structure of the present invention is formed in the Cutting Road district around the chip, can utilize the pattern metal in the semiconductor structure to stop the crack to continue to cause the infringement of chip towards the chip region extension, the useful life of avoiding component failure or reducing element, and cause expending of production cost, and then influence follow-up packaging technology and element reliability.In addition, semiconductor structure of the present invention is that the semiconductor element in chip region is made in the manufacture process of wafer, does not need to increase extra processing step, therefore can not increase manufacturing cost in addition.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, any those skilled in the art, under the premise without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is as the criterion when looking the claims person of defining.
Claims (15)
1. semiconductor structure is positioned in the Cutting Road district of a wafer and around a chip region of this wafer, this semiconductor structure comprises:
A plurality of dielectric layers are disposed in this Cutting Road district in regular turn; And
A plurality of pattern metal are disposed in each those dielectric layer, and extend to this dielectric layer of part that is arranged in the below.
2. semiconductor structure as claimed in claim 1, wherein those pattern metal have a first and a second portion, and this second portion is positioned at this first below.
3. semiconductor structure as claimed in claim 2, wherein the width of this first is identical with the width of this second portion.
4. semiconductor structure as claimed in claim 2, wherein the width of this first is greater than the width of this second portion.
5. semiconductor structure as claimed in claim 1, wherein those pattern metal in each those dielectric layer are staggered arrangement with those pattern metal of this dielectric layer that is arranged in the below.
6. semiconductor structure as claimed in claim 1, wherein those pattern metal in each those dielectric layer are connected with those pattern metal of this dielectric layer that is arranged in the below.
7. semiconductor structure as claimed in claim 1, wherein the material of those pattern metal comprises copper.
8. semiconductor structure as claimed in claim 1, wherein the material of those dielectric layers comprises advanced low-k materials.
9. semiconductor structure as claimed in claim 8, wherein this advanced low-k materials comprises the fluorine silex glass.
10. the manufacture method of a semiconductor structure comprises:
One substrate is provided;
On this substrate, form one first dielectric layer;
On this first dielectric layer, form one second dielectric layer; And
Form a plurality of pattern metal in this second dielectric layer, those pattern metal extend in this first dielectric layer of part at least.
11. the manufacture method of semiconductor structure as claimed in claim 10, wherein the formation method of those pattern metal comprises:
In this second dielectric layer, form a plurality of irrigation canals and ditches:
Form a plurality of openings in this second dielectric layer of those irrigation canals and ditches belows, those openings extend in this first dielectric layer of part at least; And
In those irrigation canals and ditches and those openings, insert a metal material.
12. the manufacture method of semiconductor structure as claimed in claim 10, wherein the formation method of those pattern metal comprises:
In this second dielectric layer, form a plurality of openings;
In this second dielectric layer of part around those open top, form a plurality of irrigation canals and ditches; And
In those irrigation canals and ditches and those openings, insert a metal material.
13. the manufacture method of semiconductor structure as claimed in claim 10, wherein the material of those pattern metal comprises copper.
14. the manufacture method of semiconductor structure as claimed in claim 10, wherein the material of this first dielectric layer and this second dielectric layer comprises advanced low-k materials.
15. the manufacture method of semiconductor structure as claimed in claim 14, wherein this advanced low-k materials comprises the fluorine silex glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101133779A CN100477175C (en) | 2005-10-11 | 2005-10-11 | Semiconductor structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101133779A CN100477175C (en) | 2005-10-11 | 2005-10-11 | Semiconductor structure and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN1949485A true CN1949485A (en) | 2007-04-18 |
| CN100477175C CN100477175C (en) | 2009-04-08 |
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| CNB2005101133779A Active CN100477175C (en) | 2005-10-11 | 2005-10-11 | Semiconductor structure and manufacturing method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194796A (en) * | 2010-03-18 | 2011-09-21 | 北大方正集团有限公司 | Wafer detection structure, manufacturing method thereof and wafer detection method |
| CN102760728A (en) * | 2011-04-27 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | Chip testing structure and testing method |
| CN102956567A (en) * | 2011-08-21 | 2013-03-06 | 南亚科技股份有限公司 | Crack stop structure and method for forming the same |
| CN112309991A (en) * | 2019-07-26 | 2021-02-02 | 华为技术有限公司 | Chip, preparation method thereof and electronic equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1187820C (en) * | 2002-02-06 | 2005-02-02 | 台湾积体电路制造股份有限公司 | Wafer structure |
-
2005
- 2005-10-11 CN CNB2005101133779A patent/CN100477175C/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194796A (en) * | 2010-03-18 | 2011-09-21 | 北大方正集团有限公司 | Wafer detection structure, manufacturing method thereof and wafer detection method |
| CN102760728A (en) * | 2011-04-27 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | Chip testing structure and testing method |
| CN102760728B (en) * | 2011-04-27 | 2015-04-01 | 中芯国际集成电路制造(上海)有限公司 | Chip testing structure and testing method |
| CN102956567A (en) * | 2011-08-21 | 2013-03-06 | 南亚科技股份有限公司 | Crack stop structure and method for forming the same |
| CN102956567B (en) * | 2011-08-21 | 2015-07-29 | 南亚科技股份有限公司 | Crack stop structure |
| CN112309991A (en) * | 2019-07-26 | 2021-02-02 | 华为技术有限公司 | Chip, preparation method thereof and electronic equipment |
| WO2021017961A1 (en) * | 2019-07-26 | 2021-02-04 | 华为技术有限公司 | Chip and preparation method therefor, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100477175C (en) | 2009-04-08 |
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