CN1945585A - RAM listing method and device in logic circuit design - Google Patents
RAM listing method and device in logic circuit design Download PDFInfo
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- CN1945585A CN1945585A CN 200610063298 CN200610063298A CN1945585A CN 1945585 A CN1945585 A CN 1945585A CN 200610063298 CN200610063298 CN 200610063298 CN 200610063298 A CN200610063298 A CN 200610063298A CN 1945585 A CN1945585 A CN 1945585A
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Abstract
This invention relates to a RAM example method in logic circuit designing, including the following steps: (a) reading the designed codes of logic circuits, obtaining the parameters in the codes that marks RAM modules, (b) finding the name of RAM units corresponding to the parameters in the encapsulation papers of united library, in which, the name of RAM units is corresponding to the RAM units,(c) according to the name, choosing the corresponding RAM units for the connection of input and output pins. The invention also provides a RAM example method in corresponding logic circuit designing and generating system.
Description
Technical field
The present invention relates to electronic technology field, more particularly, relate to RAM listing method and device in a kind of Logic Circuit Design.
Background technology
At ASIC (Application Specific Integrated Circuit, special IC) and FPGA (Field Programmable Gate Array, field programmable gate array) etc. in the circuit design, tend to use in a large number RAM (random access memory, random access memory), for example use RAM as FIFO, metadata cache etc., and the storage depth of these RAM is different with the wide also possibility of stored data bit.
Exampleization be meant make the use-case statement call with design code in routine assumed name's corresponding elements.The general only model of exampleization RAM in the Code Design of logical design, these routine assumed names are corresponding with cell name, the corresponding input and output pin of RAM in the comprehensive storehouse.As shown in Figure 1, be the graph of a relation of cell name in the routine assumed name that uses in the existing design and the comprehensive storehouse of RAM, cell name is corresponding by the RAM package file in routine assumed name and the comprehensive storehouse of RAM.In the code of logical design, if the degree of depth, bit wide or the type of the ram cell of exampleization (as RAM_0 and RAM_1 etc.) are different, promptly be considered to different ram cells, and each different ram cell has a RAM package file, and for example the package file of RAM_0 correspondence is RAM_0.v in the code; The package file of RAM_1 correspondence is RAM_1.v.The ram cell that exampleization is different must use different package files.These RAM package files externally provide the general-purpose interface that RAM uses in the design, the ram cell in the comprehensive storehouse of inner exampleization.When the synthesis tool of use such as DC (Design Compiler) comprehensively becomes side circuit with the logical design code, except reading in design code, also to read in the RAM package file, make synthesis tool, call ram cell corresponding in the comprehensive storehouse and finish combined process according to the RAM package file.
Owing to the necessary corresponding RAM package file of RAM different in the such scheme, and in ASIC design, tend to use a large amount of different RAM, in order to accomplish the corresponding RAM package file of a kind of RAM, the RAM name that requires to use in the design must be identical with the RAM name in the RAM package file, as for the RAM_0 among Fig. 1, use RAM_0 in its logical design code, then the RAM name in its package file also is necessary for RAM_0.Thereby must spended time and energy carry out the design of package file, design and maintenance workload are bigger.
In addition, because logical design now designs simultaneously usually by many people's division of labor, each designer can safeguard RAM tabulation and the RAM package file of oneself; If different designers has used identical RAM, but in code separately to RAM be named and different, the management of the package file of RAM is made troubles.
In addition, because the corresponding a kind of RAM package file of each RAM, this emulation to the RAM package file brings certain difficulty.Because the RAM package file does not have any association each other, therefore can't build a test environment carries out unified emulation.If for each RAM builds a kind of simulated environment, workload is huge, and is consuming time also oversize.Common way is that all RAM package files are built the ASIC verification environment in design at present, carry out emulation, but this emulation is consuming time oversize, and emulation testing excitation can't traverse all RAM, causes because of detecting the insufficient defective that can't find that circuit may exist.
Summary of the invention
The technical matters that the embodiment of the invention will solve is, at causing designing the problem big with maintenance workload, that emulation testing is consuming time owing to the RAM package file in the above-mentioned Logic Circuit Design, provide RAM listing method and device in a kind of Logic Circuit Design.
The technical solution adopted for the present invention to solve the technical problems is: construct the RAM listing method in a kind of Logic Circuit Design, may further comprise the steps:
(a) read the Logic Circuit Design code, obtain the parameter group of sign ram cell in the code;
(b) find the ram cell name corresponding with described parameter group by described parameter group in the package file of comprehensive storehouse, the ram cell name in the package file of described comprehensive storehouse is corresponding with the ram cell in the comprehensive storehouse;
(c) select ram cell corresponding in the comprehensive storehouse to carry out the connection of input and output pin according to described ram cell name.
In the RAM listing method in Logic Circuit Design of the present invention, comprise the corresponding relation between different parameters group and different ram cell names in the package file of described comprehensive storehouse, and the cell name of all ram cells in the described comprehensive storehouse package file comprehensive storehouse of using when comprising corresponding to example.
In the RAM listing method in Logic Circuit Design of the present invention, (c) also comprises afterwards in described step:
(d) do not carry out the ram cell that the input and output pin connects in identification and the deletion step (c).
In the RAM listing method in Logic Circuit Design of the present invention, comprise RAM type, the RAM degree of depth and RAM bit wide parameter in the described parameter group.
The present invention also provides the RAM example makeup in a kind of Logic Circuit Design to put, include: explanation module and the storage unit that stores comprehensive storehouse package file, comprise the corresponding relation between different parameters group and different ram cell names in the package file of described comprehensive storehouse, and described comprehensive storehouse package file comprises the cell name corresponding to all ram cells in the comprehensive storehouse of using in the exampleization;
Described explanation module reads parameter group in the Logic Circuit Design code, obtain corresponding ram cell name by described parameter group and obtain ram cell corresponding in the comprehensive storehouse according to described ram cell name and carry out the connection of input and output pin in the package file of described comprehensive storehouse.
RAM example makeup in Logic Circuit Design of the present invention also includes optimal module in putting, and described optimal module is used to discern and delete the ram cell that pin connects without described explanation module.
RAM example makeup in Logic Circuit Design of the present invention comprises RAM type, the RAM degree of depth and RAM bit wide parameter in putting in the described parameter group.
The present invention also provides a kind of system of formation logic circuit, comprise that example makeup puts, described example makeup is put and is included: explanation module and the storage unit that stores comprehensive storehouse package file, comprise the corresponding relation between different parameters group and different ram cell names in the package file of described comprehensive storehouse, and described comprehensive storehouse package file comprises the cell name corresponding to all ram cells in the comprehensive storehouse of using in the exampleization; Described explanation module reads the parameter group in the Logic Circuit Design code and carry out the connection of input and output pin by this parameter group after described comprehensive storehouse package file obtains ram cell corresponding the comprehensive storehouse.
In the system of formation logic circuit of the present invention, described example makeup is put and is also comprised optimal module, and described optimal module is used for discerning and deletion and the not corresponding ram cell of described Logic Circuit Design code parameter group.
In the system of formation logic circuit of the present invention, comprise RAM type, the RAM degree of depth and RAM bit wide parameter in the described parameter group.
The system of RAM example method in logic circuit designing of the present invention, device and formation logic circuit by using unified comprehensive storehouse package file, has avoided the conflict of RAM name, and has reduced the design and the maintenance workload of RAM package file, has improved design efficiency.And, when the logic function of design circuit, can arbitrarily use RAM example assumed name owing to adopt parameterized design, and needn't consider information such as the concrete degree of depth of RAM and width.Even change flow producer, also need not revise logical design.In addition, the present invention can not introduce the logical resource that has more and cause the design gate number to increase by optimizing the ram cell that deletion does not connect, and need not be the RAM package file of a correspondence of each RAM design, the workload that has therefore reduced the design of RAM package file and safeguarded.
In addition, owing to adopted unified comprehensive storehouse package file, can conveniently build independent RAM emulation and unify environment, all RAM are carried out unified emulation, the workload and the simulation time of RAM emulation have been reduced, and improved RAM emulation coverage rate, thereby reduced the error risk of ASIC design on RAM.
Description of drawings
Fig. 1 be in the prior art Logic Circuit Design RAM example assumed name and the comprehensive library unit name of RAM concern synoptic diagram;
Fig. 2 is the structural representation that the makeup of RAM example is put during Logic Circuit Design in the first embodiment of the invention;
Fig. 3 is the structural representation that the makeup of RAM example is put during Logic Circuit Design in the second embodiment of the invention;
Fig. 4 is to use the present invention to carry out the first embodiment synoptic diagram of exampleization;
Fig. 5 is to use the present invention to carry out the second embodiment synoptic diagram of exampleization;
Fig. 6 is the process flow diagram of RAM listing method during Logic Circuit Design in the embodiment of the invention.
Embodiment
As shown in Figure 2, in the first embodiment of the invention during Logic Circuit Design makeup of RAM example put 20 and read the Logic Circuit Design code and according to the parameter group in the logical circuit code, in package file, obtain corresponding ram cell by described parameter group, according to the ram cell in the comprehensive storehouse of described ram cell name selection RAM, and ram cell is carried out the connection of input and output pin.This RAM example makeup is put 20 and is included explanation module 21 and storage unit, stores a comprehensive storehouse package file 22 in this storage unit.
Comprehensive storehouse package file 22 includes the RAM parameter group used in the design code mapping relations between ram cell in the comprehensive storehouse.In the present embodiment, the cell name of all ram cells that comprehensive storehouse package file 22 uses when including exampleization, the file of the comprehensive storehouse package file 22 that this moment is corresponding RAM.v by name.All ram cells that use in the package file 22 exampleization Logic Circuit Design of comprehensive storehouse can call all ram cells in the comprehensive storehouse of RAM.When Code Design, different RAM exampleizations is all used this comprehensive storehouse package file 22.In this comprehensive storehouse package file 22, different RAM distinguish mutually by parameter group, and promptly parameter group is mapped to a concrete ram cell in the comprehensive storehouse.Comprise RAM type (TYPE), the RAM degree of depth (DEEPTH) and RAM bit wide parameter (WIDTH) in this parameter group.
In the Code Design of carrying out logical circuit, during exampleization RAM, use the parameter occurrence to be delivered in the package file of comprehensive storehouse such as The Automation Design language such as Verilog:
RAM #(TYPE，DEEPTH，WIDTH) U_RAM_0
Wherein TYPE, DEEPTH, WIDTH are the occurrences of corresponding concrete ram cell; U_RAM_0 is the routine assumed name who uses in the design code, each RAM example assumed name difference.When the design code with the logical design circuit comprehensively becomes circuit, explanation module 21 reads the parameter group in the Logic Circuit Design code, and in comprehensive storehouse package file 22, obtain corresponding ram cell name by this parameter group, thereby obtain ram cell corresponding in the comprehensive storehouse according to above-mentioned ram cell name, carry out the connection of this ram cell input and output pin then.
Because the actual corresponding unified comprehensive storehouse package file 22 of RAM example assumed name in the code, and example has been changed used all ram cells in this file, each RAM example assumed name in the then corresponding code can select real corresponding ram cell to carry out the connection of input and output pin by the parameter value that imports in the comprehensive storehouse package file 22, and all the other are unsettled with the input and output pin of the not corresponding ram cell of routine assumed name.
Because ASIC synthesis tool (as DC) is general can Automatic Optimal not to fall not have the ram cell that uses, the circuit after therefore comprehensive will call all ram cells in the unified package file, causes the circuit area change greatly.As shown in Figure 4, corresponding all ram cells of circuit after the RAM_i in the code is comprehensive, but have only the pin of the ram cell corresponding normally to connect with RAM_i, the pin of all the other unnecessary RAM is all unsettled.
Because the output pin of general RAM is a data line, the RAM that output pin does not all connect just can think untapped unnecessary RAM, can not have influence on the correctness of design.
As shown in Figure 3, in second embodiment of the invention, 30 storage unit that include explanation module 31 equally and store comprehensive storehouse package file 32 are put in the makeup of RAM example.In the present embodiment, the makeup of RAM example is put 30 and is also included optimal module 33.When comprehensive, optimal module 33 is used to discern the RAM that output pin does not all connect, and with these RAM that does not connect deletions.The script command that above-mentioned identification and deletion can use synthesis tool to provide is realized.As shown in Figure 5, for use the synoptic diagram after optimal module 33 is optimized when comprehensive.
As shown in Figure 6, be the process flow diagram of embodiment of the invention RAM example method in logic circuit designing.In the present embodiment, by calling of ram cell in the unified comprehensive storehouse of RAM package file realization RAM, thus the design of simplification RAM package file.It specifically may further comprise the steps:
Step S61: read the Logic Circuit Design code, obtain the parameter group of sign ram cell in the code.In the present embodiment, each parameter group comprises RAM type, the RAM degree of depth and RAM bit wide parameter.
Step S62: call ram cell in the comprehensive storehouse by comprehensive storehouse package file, and in the package file of comprehensive storehouse, use the described parameter set selection ram cell name corresponding with this parameter group.In the present embodiment, because therefore all ram cells in the comprehensive comprehensive storehouse of package file exampleization, storehouse will call all ram cells in the comprehensive storehouse in this step.In this comprehensive storehouse package file, distinguish different ram cells by different parameter group, a parameter group is mapped to a concrete ram cell.
Step S63: select ram cell in the comprehensive storehouse of RAM according to described ram cell name, and the ram cell of selecting is carried out the connection of input and output pin.The pin of other ram cells that call is then unsettled.
Certainly except using RAM type, the RAM degree of depth and RAM bit wide parameter identification ram cell, in actual applications, also can use other parameter group to identify ram cell.In addition, when the ram cell that synthesis tool can not Automatic Optimal have to use, then can use all unsettled ram cell of script command identification output pin of synthesis tool, and delete these ram cells.
Above-mentioned apparatus and method are applicable to the exampleization of special IC, field programmable gate array etc.
Through the checking of formal verification and instrument, use the logical circuit of apparatus and method exampleization of the present invention, the logic function of comprehensive back circuit and comprehensively preceding logical code is consistent, so the present invention do not change circuit function, is feasible and reliable.
Above-mentioned device and method can be applicable in the system of formation logic circuit, thereby realizes the ram cell exampleization in the Logic Circuit Design.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (10)
1, the RAM listing method in a kind of Logic Circuit Design is characterized in that, may further comprise the steps:
(a) read the Logic Circuit Design code, obtain the parameter group of sign ram cell in the code;
(b) find the ram cell name corresponding with described parameter group by described parameter group in the package file of comprehensive storehouse, the ram cell name in the package file of described comprehensive storehouse is corresponding with the ram cell in the comprehensive storehouse;
(c) select ram cell corresponding in the comprehensive storehouse to carry out the connection of input and output pin according to described ram cell name.
2, the RAM listing method in the Logic Circuit Design according to claim 1, it is characterized in that, comprise the corresponding relation between different parameters group and different ram cell names in the package file of described comprehensive storehouse, and the cell name of all ram cells in the described comprehensive storehouse package file comprehensive storehouse of using when comprising corresponding to example.
3, the RAM listing method in the Logic Circuit Design according to claim 1 is characterized in that, (c) also comprises afterwards in described step:
(d) do not carry out the ram cell that the input and output pin connects in identification and the deletion step (c).
4, the RAM listing method in the Logic Circuit Design according to claim 1 is characterized in that, comprises RAM type, the RAM degree of depth and RAM bit wide parameter in the described parameter group.
5, the makeup of the example of the RAM in a kind of Logic Circuit Design is put, it is characterized in that, include: explanation module and the storage unit that stores comprehensive storehouse package file, comprise the corresponding relation between different parameters group and different ram cell names in the package file of described comprehensive storehouse, and described comprehensive storehouse package file comprises the cell name corresponding to all ram cells in the comprehensive storehouse of using in the exampleization;
Described explanation module reads parameter group in the Logic Circuit Design code, obtain corresponding ram cell name by described parameter group and obtain ram cell corresponding in the comprehensive storehouse according to described ram cell name and carry out the connection of input and output pin in the package file of described comprehensive storehouse.
6, the makeup of the example of the RAM in the Logic Circuit Design according to claim 5 is put, and it is characterized in that, also includes optimal module, and described optimal module is used to discern and delete the ram cell that pin connects without described explanation module.
7, the makeup of the example of the RAM in the Logic Circuit Design according to claim 5 is put, and it is characterized in that, comprises RAM type, the RAM degree of depth and RAM bit wide parameter in the described parameter group.
8, a kind of system of formation logic circuit, it is characterized in that, comprise that example makeup puts, described example makeup is put and is included: explanation module and the storage unit that stores comprehensive storehouse package file, comprise the corresponding relation between different parameters group and different ram cell names in the package file of described comprehensive storehouse, and described comprehensive storehouse package file comprises the cell name corresponding to all ram cells in the comprehensive storehouse of using in the exampleization; Described explanation module reads the parameter group in the Logic Circuit Design code and carry out the connection of input and output pin by this parameter group after described comprehensive storehouse package file obtains ram cell corresponding the comprehensive storehouse.
9, the system of formation logic circuit according to claim 8 is characterized in that, described example makeup is put and also comprised optimal module, and described optimal module is used for discerning and deletion and the not corresponding ram cell of described Logic Circuit Design code parameter group.
10, the system of formation logic circuit according to claim 8 is characterized in that, comprises RAM type, the RAM degree of depth and RAM bit wide parameter in the described parameter group.
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| CNB2006100632986A CN100483428C (en) | 2006-10-24 | 2006-10-24 | RAM listing method and device in logic circuit design |
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| CNB2006100632986A CN100483428C (en) | 2006-10-24 | 2006-10-24 | RAM listing method and device in logic circuit design |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107895087A (en) * | 2017-11-29 | 2018-04-10 | 中科亿海微电子科技（苏州）有限公司 | The method and system that the emulation of PLD module level automatically generates with code |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107895087A (en) * | 2017-11-29 | 2018-04-10 | 中科亿海微电子科技（苏州）有限公司 | The method and system that the emulation of PLD module level automatically generates with code |
| CN107895087B (en) * | 2017-11-29 | 2021-02-26 | 中科亿海微电子科技（苏州）有限公司 | Method and system for automatically generating module-level simulation configuration code of programmable logic circuit |
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