CN115729752A - Register checking method and device and storage medium - Google Patents

Abstract

The embodiment of the application provides a register checking method and device and a storage medium, and the method comprises the following steps: reading a register address and register data in a target chip; sequentially searching an address node corresponding to the register address and at least one register segmentation sub-node corresponding to the address node from the multi-layer register index; analyzing at least one register segmentation sub-node to obtain at least one register segmentation information, and converting register data into at least one register value based on the at least one register segmentation information; respectively searching a value subnode corresponding to each register segmentation subnode from the multi-layer register index based on at least one register value to obtain at least one value subnode; and according to the at least one value sub-node, retrieving at least one register interpretation data segment from a register interpretation database corresponding to the multi-layer register index so as to realize register check based on the at least one register interpretation data segment.

Description

Register checking method and device, and storage medium

technical field

The present application relates to the field of registers, in particular to a method and device for checking registers, and a storage medium.

Background technique

In the process of driver development based on the chip and system (System On Chip, SOC) platform, or chip verification (Chip Validation, CV), if there is a problem with the system, the value of the register will be checked to confirm whether it is consistent with the actual configuration to verify.

At present, the inspection of registers can be done by driving the CPU to send register read instructions to the system bus, and the SOC platform returns the required data, or use the Trace32 (emulator) tool to send register read instructions through the international standard test protocol (Joint TestAction Group, JTAG) port. Fetch instructions, and the SOC platform returns the required data; then refer to the hardware specification standard document to locate the problem register.

However, a SOC platform has a large number of registers, and a single problem will also be associated with several or even more than a dozen registers, resulting in low checking efficiency and time-consuming problems.

Contents of the invention

Embodiments of the present application provide a register checking method and device, and a storage medium, which can improve checking efficiency and reduce time-consuming problems.

The technical scheme of the present application is realized like this:

In the first aspect, the embodiment of the present application proposes a register checking method, the method including:

Read the register address and register data in the target chip; sequentially search for the address node corresponding to the register address and at least one register segment sub-node corresponding to the address node from the multi-layer register index;

Parse the at least one register segment sub-node to obtain at least one register segment information, and convert the register data into at least one register value based on the at least one register segment information; the number of the at least one register value is the same as The number of the at least one register segment child node is the same;

Based on the at least one register value, search for a value sub-node corresponding to each register segment sub-node from the multi-layer register index to obtain at least one value sub-node;

According to the at least one value subnode, at least one register interpretation data segment is retrieved from the register interpretation database corresponding to the multi-level register index, so as to implement register checking based on the at least one register interpretation data segment.

In the second aspect, the embodiment of the present application proposes a device for checking registers, and the device includes:

The reading unit is used to read the register address and register data in the target chip;

A search unit, configured to sequentially search for the address node corresponding to the register address and at least one register segment sub-node corresponding to the address node from the multi-layer register index;

A parsing unit, configured to parse the at least one register segment sub-node to obtain at least one register segment information;

A conversion unit, configured to convert the register data into at least one register value based on the at least one register segment information; the number of the at least one register value is the same as the number of sub-nodes of the at least one register segment;

The search unit is further configured to respectively search for a value sub-node corresponding to each register segment sub-node from the multi-layer register index based on the at least one register value, to obtain at least one value sub-node;

The retrieval unit is configured to retrieve at least one register interpretation data segment from the register interpretation database corresponding to the multi-level register index according to the at least one value subnode, so as to implement register checking based on the at least one register interpretation data segment.

In a third aspect, the embodiment of the present application provides a device for checking registers, the device includes: a processor, a memory, and a communication bus; when the processor executes the running program stored in the memory, the method described in any one of the above is implemented.

In a fourth aspect, the embodiment of the present application provides a storage medium on which a computer program is stored, and when the computer program is executed by a processor, the method described in any one of the above is implemented.

The embodiment of the present application provides a register checking method and device, and a storage medium. The method includes: reading the register address and register data in the target chip; sequentially searching the address node and address node corresponding to the register address from the multi-layer register index Corresponding to at least one register segment sub-node; parse at least one register segment sub-node to obtain at least one register segment information, and convert register data into at least one register value based on at least one register segment information; the number of at least one register value The same as the number of at least one register segment sub-node; based on at least one register value, search for a value sub-node corresponding to each register segment sub-node from the multi-layer register index, and obtain at least one value sub-node; according to at least one The value sub-node retrieves at least one register interpretation data segment from the register interpretation database corresponding to the multi-level register index, so as to implement register checking based on the at least one register interpretation data segment. Using the above implementation scheme, the multi-layer register index and the register definition database corresponding to the multi-layer register index are preset, and after reading the register address and register segment information in the target chip, at least one value is determined based on the multi-layer register index sub-node, and retrieve at least one register interpretation data segment from the register interpretation database based on at least one value sub-node, so that the interpretation data corresponding to the register can be quickly located, thereby improving inspection efficiency and reducing time-consuming problems.

Description of drawings

FIG. 1 is a flowchart of a register checking method provided in an embodiment of the present application;

Fig. 2 is the flowchart of a kind of dictionary file generating method that the embodiment of the present application provides;

FIG. 3 is a schematic diagram of the composition of an exemplary piece of hardware specification standard document provided by the embodiment of the present application;

FIG. 4 is a schematic structural diagram of an exemplary four-layer binary tree chain register index provided by an embodiment of the present application;

FIG. 5 is a schematic flow diagram of an exemplary SOC software debugging method provided in an embodiment of the present application;

FIG. 6 is a structural schematic diagram 1 of a register checking device provided by an embodiment of the present application;

FIG. 7 is a second structural schematic diagram of a device for checking registers provided by an embodiment of the present application.

Detailed ways

It should be understood that the specific embodiments described here are only used to explain the present application. It is not intended to limit the application.

The embodiment of the present application provides a register checking method, as shown in Figure 1, the method may include:

S101. Read the register address and register data in the target chip; sequentially search for an address node corresponding to the register address and at least one register segment sub-node corresponding to the address node from the multi-layer register index.

A method for checking registers proposed in the embodiment of the present application may be applicable to a scenario where system troubleshooting is performed based on registers in a SoC chip.

In the embodiment of the present application, the device for register indexing can be any device with communication and storage functions, such as tablet computer, mobile phone, personal computer (Personal Computer, PC), notebook computer, wearable device and other devices.

It should be noted that on the platform that needs to be debugged, the CPU is driven to dump the register address of the SOC and the register data in the register address. This process needs to load and run the register dump command to read the register address and register data in the target chip. data. In the embodiment of the present application, the register dump instruction may be pre-designed based on specific implementation logic, such as implementing segmentation or screening processing for a large number of registers.

In the embodiment of the present application, after the register address and register data in the target chip are read, the register address and register data may be saved as a binary file data.bin.

It should be noted that after reading the register address and register data in the target chip, it is necessary to search for the corresponding register interpretation data from the hardware specification standard document. In order to improve the search efficiency, in the embodiment of this application, for the hardware Specification standard documents, from which register-related information useful for hardware debugging is extracted to generate multi-layer register indexes and register definition databases corresponding to multi-layer register indexes, which together form a dictionary corresponding to hardware specification standard documents document. The register checking device directly searches the interpretation data of the search register in the SOC through the dictionary file. First, after the register address and register data are read, the address node corresponding to the register address and at least one register segment sub-node corresponding to the address node are sequentially searched from the multi-layer register index.

In the embodiment of the present application, the structure of the multi-layer register index is a multi-layer binary tree chain index, wherein the first layer register index in the multi-layer register index is composed of a group of address nodes, each of the first layer register index An address node points to a group of register segment sub-nodes in the second-level register index, and each register segment sub-node in the second-level register index points to a group of value sub-nodes in the third-level register index; a group of address nodes 1. A group of register sub-nodes and a group of value sub-nodes are composed of a single-linked list structure; among them, a group of address nodes saves the address information of the registers in the hardware specification standard document, and a group of register sub-nodes saves the hardware specification standard The segment information corresponding to the address information of the register in the document, and the value range corresponding to the segment information corresponding to the address information of the register in the hardware specification standard document is stored in a group of value sub-nodes.

Specifically, based on the above-mentioned multi-layer register index structure, after reading the register address and register data in the target chip, from the first layer register index, find the address node corresponding to the register address, and from the second layer register index Determine at least one register segment child node pointed to by the address node in .

Specifically, the process of generating a multi-layer register index and register definition database includes:

S201. Extract the address information of the register, segment information corresponding to the address information, value range corresponding to the segment information, and interpretation data for each value within the value range from the original hardware specification standard document.

In the embodiment of this application, the register-related information in the original hardware specification standard document includes: the address information of the register, the segment information corresponding to the address information, the value range corresponding to the segment information, and each value within the value range interpretation data.

Figure 3 is an original hardware specification standard document. The regOffset field describes the address information of this register. The fieldRange stores the internal offset start and internal offset end of each register. The storage format is [internal offset end: internal Offset start], the fieldRange field describes the segment information of this register and the value range corresponding to the segment information. Specifically, refer to Figure 3. The register is usually 32bit unsigned int data. For the register whose regOffset is 0x0000000, fieldRange is [0:0], [1:1], [2:2], [3:3], [31:4], it can be seen that [0:0] occupies 1 bit, [1:1] occupies 1 bit, [2:2] occupies 1 bit, [3:3] occupies 1 bit, and [31:4] occupies 28 bits, then the segmentation information of 0x0000000 is 1 bit, 1 bit, 1 bit, 1 bit, 28 bits, and the value range of 1 bit is 0 -1, the value range of 28bit is 0-2 ²⁸ ; the fieldDescription field describes the interpretation data of the segmentation information.

S202. Establish a register interpretation database according to the interpretation data.

In the embodiment of the present application, a blank register interpretation database is established, and after obtaining the interpretation data corresponding to each value, each piece of interpretation data is stored in the blank register interpretation database to obtain the register interpretation database.

S203. Based on the hierarchical correspondence between the address information of the register, the segment information corresponding to the address information, and the value range corresponding to the segment information, a multi-layer register index is established.

In the embodiment of the present application, since the structure of the multi-layer register index is a multi-layer binary tree chain index, firstly, the index structure of the multi-layer binary tree chain index is set based on the hierarchical correspondence, and the index structure is a multi-layer register index The first-level register index in is composed of a set of address nodes, each address node in the first-level register index points to a set of register segment child nodes in the second-level register index, and each register in the second-level register index The segment sub-nodes point to a group of value sub-nodes in the third-level register index; a group of address nodes, a group of register segment sub-nodes and a group of value sub-nodes are composed of a single linked list structure. Afterwards, the address information of the register is sequentially saved to a group of address nodes, the segment information corresponding to the address information is sequentially saved to a group of register segment sub-nodes, and the value range corresponding to the segment information is sequentially saved to a group of fetch nodes in the value child node.

It should be noted that, for the singly linked list structure, each node will point to the next node of its same type, or point to the head pointer of its sub-linked list at the same time. If the node is the last node of the singly linked list structure, the node will point to empty node.

It should be noted that before storing the address information of the registers in a group of address nodes in sequence, the address information of the registers is sorted according to the size of the offset address value to obtain the sorted address information, and then the sorted The address information is stored in a group of address nodes in turn. At this time, the obtained binary tree can be guaranteed to be an ordered binary tree, which can improve the efficiency of register checking and comparison.

It should be noted that, in the process of setting a group of register segment subnodes, the reserved segment information in the segment information corresponding to the address information of the register can be proposed first to obtain the adjusted segment information, and then, based on the adjusted The segmentation information sets a set of register segment subnodes. The number of sub-nodes of a group of register segments can be greatly reduced, thereby reducing the complexity of the multi-layer register index, and reducing the storage size of the multi-layer register index.

Referring to Figure 3, the fieldName of fieldRand[31:4] is Reserved, indicating that the segment information is reserved segment information. The reserved segment information is reserved for future expansion and is currently not used, so [ 31:4] corresponding register segment child nodes, thus reducing the branch nodes of the binary tree structure.

S204. According to the corresponding relationship between the interpretation data and each value within the value range, establish a corresponding relationship between the multi-layer register index and the register definition database.

In the embodiment of the present application, since one value corresponds to one piece of interpretation data, the corresponding relationship between the multi-layer register index and the register interpretation database can be established according to the correspondence between the interpretation data and the value.

It should be noted that a fourth-level register index can also be added to the multi-level register index. The fourth-level register index stores value interpretation information, and each value sub-node in the third-level register index points to the fourth An interpretation information identifier in the layer register index, and then according to the corresponding relationship between the interpretation information identifier and the interpretation data, establish the corresponding relationship between the multi-layer register index and the register interpretation database. The specific three-level register index structure or the four-level register index structure of the multi-level register index can be selected according to actual conditions, and is not specifically limited in this embodiment of the present application.

Based on the steps described in S201-S204, the dictionary file corresponding to the original hardware specification standard document is generated. Taking the binary tree chain register index of the four-layer structure as an example, as shown in Figure 4, it is the binary tree chain register index of the four-layer structure and Schematic diagram of the structure of the dictionary file composed of the index paraphrase database.

The first-level register index: saves the offset address of the register, its right node points to the offset address of the next register, and its left node points to the segment information of this register, that is, the second-level register index node in Figure 4, The internal information of its structure is:

The second-level register index: it saves the current segment information of the register, its right node points to the next segment information in the register, and its left node points to different value information in the current segment information, that is, The internal information of the structure of the third-level index register node in 4 is:

The third-level register index: saves a value information in a certain segment information in the register, for example, the possible value of a 3-bit field will be {3'b0, 3'b1, 3'b10, 3'b11 , 3'b100...}, its right node points to the next value information in a certain segment information in the register, and its left node points to the interpretation information identified by a value information in a certain segment information in the register, That is, the fourth layer index register node in Figure 4, the internal information of its structure is:

The fourth layer index register: all nodes save the interpretation information identification identified by a value information in a segment information in the register, and obtain specific interpretation data from the register interpretation database through the interpretation information identification.

It should be noted that after the dictionary file corresponding to the original hardware specification standard document is generated, the dictionary file can be saved as an original hardware specification standard dictionary file in binary file format.

S102. Parse at least one register segment sub-node to obtain at least one register segment information, and convert register data into at least one register value based on at least one register segment information; the quantity of at least one register value is related to at least one register segment sub-node the same amount.

After the address node corresponding to the register address and at least one register segment sub-node corresponding to the address node are sequentially searched from the multi-layer register index, at least one register segment sub-node must be parsed to obtain at least one register segment information, and based on at least A register segmentation information that converts register data into at least one register value.

In the embodiment of the present application, the register segment information is stored in the register segment sub-node, so that each register segment sub-node is parsed separately to obtain the register segment information corresponding to each register segment sub-node.

In the embodiment of the present application, the register segment information is the start offset and end offset corresponding to the register segment sub-node, and at least one register segment information can be determined based on at least one start offset and at least one corresponding end offset Occupying at least one bit value; then, based on the at least one bit value, dividing the register data into at least one piece of register data; converting the at least one piece of register data to obtain at least one register value.

It should be noted that at least one piece of register data is composed of an arrangement of 0 and 1, therefore, at least one piece of register data is converted into a decimal value to determine at least one register value.

Exemplarily, referring to FIG. 3, the storage form of fieldRange is [internal offset end: internal offset start], for the register whose regOffset is 0x0000004, fieldRange is [1:0], [3:2], [5: 4], [9:6], [10:10], [31:11], it can be seen that [1:0] occupies 2 bits, [3:2] occupies 2 bits, [5:4] occupies 2 bits, [9: 6] occupies 4 bits, [10:10] occupies 1 bit, and [31:11] occupies 21 bits, then the segmentation information of 0x0000004 is 2bit, 2bit, 2bit, 4bit, 1bit, 21bit, then divide the register data inside the register of 0x0000004 It is 6 pieces of data, the first 4 pieces of data are 2 pieces of data, the value is 00, 01, 10 or 11, the 5th piece of data is 1 piece of data, the value is 0 or 1, the value of the 6th piece of data is 21 pieces data. Afterwards, convert the 6 segments of data into decimal values to determine the values of 6 registers.

S103. Based on at least one register value, respectively search for a value sub-node corresponding to each register segment sub-node from the multi-level register index, to obtain at least one value sub-node.

In the embodiment of the present application, based on at least one register value, a value-taking sub-node corresponding to each register segment sub-node is searched from the third-level register index in the multi-level register index, and at least one value-taking sub-node is obtained.

Exemplarily, if the value of the register is 3, the third value sub-node corresponding to the sub-node of the register segment is searched from the third-level register index.

S104. According to at least one value subnode, retrieve at least one register interpretation data segment from the register interpretation database corresponding to the multi-level register index, so as to implement register checking based on the at least one register interpretation data segment.

In the embodiment of the present application, after at least one value-taking sub-node is determined, a register interpretation data segment corresponding to each value-taking sub-node is retrieved from the register interpretation database to obtain at least one register interpretation data segment, and the at least one register The interpretation data segment constitutes the interpretation data of the corresponding register.

Furthermore, after obtaining the interpreted data of the register, the interpreted data of the register can be saved and printed for debugging and reference.

Furthermore, in the actual debugging process, the expected value of the register can also be preset in the hardware specification standard document, and then the expected value of each register is compared with the above-mentioned obtained register value, and the specific realization of the register can be determined according to the comparison result. Whether the function is the function expected to be realized by the hardware specification standard document. The specific debugging process can be implemented according to the actual situation, and is not specifically limited in this embodiment of the present application.

It can be understood that the multi-layer register index and the register definition database corresponding to the multi-layer register index are preset, and after reading the register address and register segment information in the target chip, at least one value is determined based on the multi-layer register index sub-node, and retrieve at least one register interpretation data segment from the register interpretation database based on at least one value sub-node, so that the interpretation data corresponding to the register can be quickly located, thereby improving inspection efficiency and reducing time-consuming problems.

Based on the above-mentioned embodiments, the embodiment of the present application proposes a SOC software debugging method, as shown in FIG. 5, the method may include:

1. Extract the original hardware specification standard text from the original hardware specification standard document, and extract useful information for hardware debugging, including regOffset, fieldRange and fieldDescription.

2. Use regOffset and fieldRange to build a binary tree chain index with a multi-layer structure, and build the dictionary data of the binary tree chain index according to fieldDescription; the binary tree chain index and dictionary data together form a dictionary file.

3. Save the dictionary file as a standard dictionary file of the original hardware specification according to the binary file format.

4. Load register dump instruction.

5. Drive the processor to execute the register dump instruction on the target platform, and dump the register address and register data.

6. Save the register address and register data as a data file in binary file format.

7. Use the original hardware specification standard dictionary file and data file for data analysis to obtain the specific interpretation data of the register.

Specifically, read in the index node of the original hardware specification standard dictionary file, and obtain the regOffset of each node; then, use regOffset as the data offset, and read the register data of the offset from the data file, and the register data is usually 32bit unsigned integer; parse the child node 1 of regOffset to obtain its internal segment information fieldRange; divide the register data into multiple segments of data based on fieldRange, and determine the value information corresponding to each segment of data, and parse the child node 1 based on the value information The child node 1x of the multi-segment data respectively obtains the multi-segment interpretation data segment corresponding to the multi-segment data, and the multi-segment interpretation data segment constitutes the specific interpretation data of the register.

8. Save the specific interpretation data of the register for debugging and reference.

Based on the above embodiments, the embodiment of the present application provides a register checking device 1 . As shown in Figure 6, the device 1 includes:

The reading unit 10 is used to read the register address and register data in the target chip;

A search unit 11, configured to sequentially search for the address node corresponding to the register address and at least one register segment sub-node corresponding to the address node from the multi-layer register index;

The parsing unit 12 is configured to parse the at least one register segment sub-node to obtain at least one register segment information;

A conversion unit 13, configured to convert the register data into at least one register value based on the at least one register segment information; the number of the at least one register value is the same as the number of child nodes of the at least one register segment;

The search unit 11 is further configured to search for a value sub-node corresponding to each register segment sub-node from the multi-layer register index based on the at least one register value, to obtain at least one value sub-node;

A retrieval unit 14, configured to retrieve at least one register interpretation data segment from the register interpretation database corresponding to the multi-level register index according to the at least one value subnode, so as to implement register checking based on the at least one register interpretation data segment .

Optionally, the device further includes: an extraction unit and an establishment unit;

The extraction unit is configured to extract address information of the register, segment information corresponding to the address information, value range corresponding to the segment information, and interpretation data for each value within the value range from the original hardware specification standard document;

The establishment unit is configured to establish the register interpretation database according to the interpretation data; based on the address information of the register, the segment information corresponding to the address information, and the value range corresponding to the segment information Hierarchical correspondence, establishing the multi-layer register index; according to the correspondence between the interpretation data and each value in the value range, establishing the correspondence between the multi-layer register index and the register interpretation database .

Optionally, the device further includes: a setting unit and a saving unit;

The setting unit is configured to set the index structure of the multi-layer register index according to the hierarchical correspondence, wherein the above-mentioned index structure is that the first-level register index in the multi-layer register index consists of a group of address nodes , each address node in the first-level register index points to a group of register segment sub-nodes in the second-level register index, and each register segment sub-node in the second-level register index points to a third-level register index A group of value subnodes in; the group of address nodes, the group of register segment subnodes and the group of value subnodes are composed of a single linked list structure;

The saving unit is configured to sequentially save the address information of the register to the group of address nodes, sequentially save the segment information corresponding to the address information to the group of register segment sub-nodes, and The value range corresponding to the segment information is sequentially saved to the set of value sub-nodes.

Optionally, the establishment unit is further configured to establish the multi-layer register index and the Describe the corresponding relationship of the register definition database.

Optionally, the device further includes: a sorting unit;

The sorting unit is configured to sort the address information of the register according to the size of the offset address value, and obtain the sorted address information;

The saving unit is further configured to sequentially save the sorted address information into the group of address nodes.

Optionally, the device further includes: an adjustment unit;

The adjustment unit is configured to remove the reserved segment information in the segment information corresponding to the address information to obtain adjusted segment information;

The setting unit is further configured to set the group of register segment child nodes based on the adjusted segment information.

Optionally, the register segment information is a start offset and an end offset corresponding to register segment subnodes, and the device further includes: a determination unit and a division unit;

The determining unit is configured to determine at least one bit value occupied by the at least one register segment information based on at least one start offset and at least one corresponding end offset;

The division unit is configured to divide the register data into at least one piece of register data based on the at least one bit value;

The conversion unit 13 is further configured to convert the at least one piece of register data into a binary system to obtain the at least one register value.

A register inspection device provided in an embodiment of the present application reads the register address and register data in the target chip; sequentially searches the address node corresponding to the register address and at least one register segment sub-node corresponding to the address node from the multi-layer register index; Parsing at least one register segment child node, obtaining at least one register segment information, and converting the register data into at least one register value based on the at least one register segment information; the number of at least one register value and the number of at least one register segment child node Same; based on at least one register value, search for a value sub-node corresponding to each register segment sub-node from the multi-level register index, and obtain at least one value sub-node; according to at least one value sub-node, from the multi-level register At least one register interpretation data segment is retrieved from the register interpretation database corresponding to the index, so as to implement register checking based on the at least one register interpretation data segment. It can be seen that the device proposed in this embodiment presets the multi-layer register index and the register definition database corresponding to the multi-layer register index. After reading the register address and register segment information in the target chip, the multi-layer register index Determine at least one value sub-node, and retrieve at least one register interpretation data segment from the register interpretation database based on at least one value sub-node, so that the interpretation data corresponding to the register can be quickly located, thereby improving inspection efficiency and reducing time-consuming problems .

Fig. 7 is a schematic diagram of the composition and structure of a register checking device 1 provided by the embodiment of the present application II. In practical applications, based on the same disclosed concept of the above embodiment, as shown in Fig. 7, the device 1 of this embodiment includes: Processor 15 , memory 16 and communication bus 17 .

In the process of the specific embodiment, the above-mentioned reading unit 10, searching unit 11, analyzing unit 12, converting unit 13, retrieving unit 14, extracting unit, establishing unit, setting unit, saving unit, sorting unit, adjusting unit, determining The unit and the dividing unit can be realized by a processor 15 located on the device 1, and the above-mentioned processor 15 can be an application-specific integrated circuit (ASIC, Application Specific Integrated Circuit), a digital signal processor (DSP, Digital Signal Processor), digital signal processing image processing device (DSPD, Digital Signal Processing Device), programmable logic image processing device (PLD, Programmable Logic Device), field programmable gate array (FPGA, Field Programmable Gate Array), CPU, controller, microcontroller, microprocessor at least one of . It can be understood that, for different devices, the electronic device used to implement the above processor function may also be other, which is not specifically limited in this embodiment.

In the embodiment of the present application, the above-mentioned communication bus 17 is used to realize connection and communication between the processor 15 and the memory 16; when the above-mentioned processor 15 executes the running program stored in the memory 16, the following register checking method is implemented:

Reading the register address and register data in the target chip; sequentially searching the address node corresponding to the register address and at least one register segment sub-node corresponding to the address node from the multi-layer register index; parsing the at least one register segment sub-node, Obtaining at least one register segment information, and converting the register data into at least one register value based on the at least one register segment information; the number of the at least one register value and the number of child nodes of the at least one register segment Same; based on the at least one register value, search for a value subnode corresponding to each register segment subnode from the multi-layer register index to obtain at least one value subnode; according to the at least one value subnode A node, retrieving at least one register interpretation data segment from the register interpretation database corresponding to the multi-level register index, so as to implement register checking based on the at least one register interpretation data segment.

Further, the above-mentioned processor 15 is also configured to extract the address information of the register, the segment information corresponding to the address information, the value range corresponding to the segment information, and each value within the value range from the original hardware specification standard document. the interpretation data; establish the register interpretation database according to the interpretation data; based on the hierarchical correspondence between the address information of the register, the segment information corresponding to the address information, and the value range corresponding to the segment information , establishing the multi-level register index; establishing a corresponding relationship between the multi-level register index and the register definition database according to the corresponding relationship between the interpretation data and each value in the value range.

Further, the above-mentioned processor 15 is also configured to set the index structure of the multi-layer register index according to the hierarchical correspondence, wherein the above-mentioned index structure is that the first-layer register index in the multi-layer register index consists of a Each address node in the first-level register index points to a group of register segment sub-nodes in the second-level register index, and each register segment sub-node in the second-level register index points to the first A group of value subnodes in the three-layer register index; the group of address nodes, the group of register segment subnodes and the group of value subnodes are composed of a single linked list structure; the address information of the register Sequentially saving to the group of address nodes, sequentially saving the segment information corresponding to the address information to the group of register segment sub-nodes, sequentially saving the value range corresponding to the segment information to the In a set of value child nodes.

Further, the above-mentioned processor 15 is also configured to establish the multi-layer register index and the The register defines the corresponding relationship of the database.

Further, the above-mentioned processor 15 is also configured to sort the address information of the registers according to the size of the offset address value to obtain the sorted address information; and save the sorted address information to the set of address node.

Further, the above-mentioned processor 15 is further configured to remove the reserved segment information in the segment information corresponding to the address information to obtain adjusted segment information; set the A set of register segment subnodes.

Further, the register segment information is the start offset and end offset corresponding to the sub-nodes of the register segment,

The above-mentioned processor 15 is further configured to determine at least one bit value occupied by the at least one register segment information based on at least one start offset and at least one corresponding end offset; based on the at least one bit value, the The register data is divided into at least one piece of register data; the at least one piece of register data is converted into a base to obtain the at least one register value.

An embodiment of the present application provides a storage medium on which a computer program is stored. The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors and applied to registers. In the inspection device, the computer program implements the register inspection method as described above.

It should be noted that, in this document, the term "comprising", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element.

Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware, but in many cases the former is better implementation. Based on this understanding, the technical solution of the present disclosure can be embodied in the form of a software product in essence or the part that contributes to the related technology. The computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk, etc.) ) includes several instructions to make an image display device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the methods described in various embodiments of the present disclosure.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the protection scope of the present application.

Claims (10)

1. A register checking method, the method comprising:

reading a register address and register data in a target chip; sequentially searching an address node corresponding to the register address and at least one register segmented sub-node corresponding to the address node from the multi-layer register index;

analyzing the at least one register segmentation sub-node to obtain at least one register segmentation information, and converting the register data into at least one register value based on the at least one register segmentation information; the number of the at least one register value is the same as the number of the at least one register segment child node;

based on the at least one register value, respectively searching a value subnode corresponding to each register segmentation subnode from the multi-layer register index to obtain at least one value subnode;

and according to the at least one value sub-node, retrieving at least one register interpretation data segment from a register interpretation database corresponding to the multi-layer register index, so as to realize register check based on the at least one register interpretation data segment.

2. The method according to claim 1, wherein before sequentially searching the address node corresponding to the register address and the at least one register segment sub-node corresponding to the address node from the multi-layer register index, the method further comprises:

extracting address information of a register, segmentation information corresponding to the address information, a value range corresponding to the segmentation information and interpretation data of each value in the value range from an original hardware specification standard document;

establishing the register paraphrasing database according to the interpretation data;

establishing the multi-layer register index based on the address information of the register, the segmentation information corresponding to the address information and the hierarchy corresponding relationship between the value ranges corresponding to the segmentation information;

and establishing the corresponding relation between the multilayer register index and the register paraphrase database according to the corresponding relation between the interpretation data and each value in the value range.

3. The method according to claim 2, wherein the establishing the multi-level register index based on a hierarchical correspondence between address information of the register, segment information corresponding to the address information, and a value range corresponding to the segment information includes:

setting an index structure of the multilayer register indexes according to the hierarchical correspondence, wherein the index structure is that a first layer register index in the multilayer register indexes is composed of a group of address nodes, each address node in the first layer register index points to a group of register segment sub-nodes in a second layer register index, and each register segment sub-node in the second layer register index points to a group of value sub-nodes in a third layer register index; the group of address nodes, the group of register segmentation sub-nodes and the group of value sub-nodes are composed of a singly linked list structure;

sequentially storing the address information of the register into the group of address nodes, sequentially storing the segmentation information corresponding to the address information into the group of register segmentation sub-nodes, and sequentially storing the value range corresponding to the segmentation information into the group of value sub-nodes.

4. The method of claim 3, wherein establishing a correspondence between the multi-level register index and the register paraphrase database based on the correspondence between the interpretation data and each value in the range of values comprises:

and establishing the corresponding relation between the multi-layer register index and the register paraphrase database by pointing each dereferencing child node in the third-layer register index to corresponding interpretation data in the register paraphrase database.

5. The method of claim 3, further comprising:

sorting the address information of the register according to the size of the offset address value to obtain the sorted address information;

and sequentially storing the sequenced address information into the group of address nodes.

6. The method of claim 3, further comprising:

removing reserved subsection information in subsection information corresponding to the address information to obtain adjusted subsection information;

setting the set of register segment sub-nodes based on the adjusted segment information.

7. The method of claim 1, wherein the register segment information is a start offset and an end offset corresponding to a register segment subnode, and wherein converting the register data into at least one register value based on the at least one register segment information comprises:

determining at least one bit value occupied by the at least one register segment information based on at least one start offset and a corresponding at least one end offset;

dividing the register data into at least one segment of register data based on the at least one bit value;

and carrying out binary conversion on the at least one segment of register data to obtain the at least one register value.

8. A register checking apparatus, characterized in that the apparatus comprises:

the reading unit is used for reading the register address and the register data in the target chip;

the searching unit is used for sequentially searching an address node corresponding to the register address and at least one register segmentation sub-node corresponding to the address node from the multi-layer register index;

the analysis unit is used for analyzing the at least one register segmentation sub-node to obtain at least one register segmentation information;

a conversion unit for converting the register data into at least one register value based on the at least one register segmentation information; the number of the at least one register value is the same as the number of the at least one register segment child node;

the searching unit is further configured to search, based on the at least one register value, one value subnode corresponding to each register segment subnode from the multi-layer register index, to obtain at least one value subnode;

and the retrieval unit is used for retrieving at least one register interpretation data segment from a register interpretation database corresponding to the multi-layer register index according to the at least one value sub-node so as to realize register check based on the at least one register interpretation data segment.

9. A register checking apparatus, characterized in that the apparatus comprises: a processor, a memory; the processor, when executing the execution program stored in the memory, implements the method of any of claims 1-7.

10. A storage medium on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 7.

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