CN1945414A - Pixel structure - Google Patents
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- CN1945414A CN1945414A CN 200610147041 CN200610147041A CN1945414A CN 1945414 A CN1945414 A CN 1945414A CN 200610147041 CN200610147041 CN 200610147041 CN 200610147041 A CN200610147041 A CN 200610147041A CN 1945414 A CN1945414 A CN 1945414A
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Abstract
The invention is a pixel structure, includes the following components. The Scanning lines and data lines are on the base plate. The first, second and third thin-film transistor respectively connects with the scanning line electrically. The second and third thin-film transistor channel has the same ratio of width to length, which is larger than the first one. The first, second and third share line is respectively set under the three pixel electrodes, in which, the first and second ones meet electricity linking with the first voltage, and the third one links with the second voltage. When this pixel structure is drive, the first, second and third thin-film transistors will produce different charging rate, to improve the color deflection.
Description
Technical field
The invention relates to a kind of dot structure, and particularly relevant for a kind of dot structure of LCD.
Background technology
Thin Film Transistor-LCD (TFT-LCD) because have that high image quality, space utilization efficient are good, low consumpting power, advantageous characteristic such as radiationless, thereby become the main flow in market gradually.At present, market is towards characteristics such as height contrast (High Contrast Ratio), rapid reaction and wide viewing angles for the performance requirement of LCD.Can reach the technology of wide viewing angle requirement at present, multi-zone vertical alignment nematic (Multi-domain Vertically Alignment is for example arranged, MVA), multiple domain horizontal direction matching (Multi-domainHorizontal Alignment, MHA), twisted nematic adds visual angle expansion film (Twisted Nematic plus wideviewing film, TN+film) and the transverse electric field form (In-Plane Switching, IPS).
Though the Thin Film Transistor-LCD of multi-zone vertical alignment nematic can reach the purpose of wide viewing angle, there is the problem of colour cast (color washout) in it also is for This is what people generally disapprove of.So-called colour cast refers to as the user when watching the shown image of display, can see the image of different color contrast with the different angles of viewing and admiring, and for example the user can see white partially image when watching than the angle of deflection.
Present someone proposes to solve the method for above-mentioned colour cast, and it comprises compensate film (retardation film), the reduction cell gap (cell gap) that adopts combination A plate (A-plate) and C plate (C-plate) or form two kinds of liquid crystal capacitances in single dot structure.Yet, adopt the effect of the compensate film compensation of making up A plate and C plate limited, can reduce yield and brightness (brightness) and reduce cell gap.As for the method that in single dot structure, forms two kinds of liquid crystal capacitances,, therefore can cause problems such as showing inhomogeneous (mura) and image retention owing to need to use extra dielectric layer.
Summary of the invention
The purpose of this invention is to provide a kind of dot structure,, keep yield and brightness, and solve the problem that shows inhomogeneous and image retention to improve the problem of colour cast.
For reaching above-mentioned or other purpose, the present invention proposes a kind of dot structure.This dot structure comprises data line, at least one sweep trace, the first film transistor, second thin film transistor (TFT), the 3rd thin film transistor (TFT), first pixel electrode, second pixel electrode, the 3rd pixel electrode, first common lines, second common lines and the 3rd common lines.Wherein data line and sweep trace are disposed on the substrate.The first film transistor, second thin film transistor (TFT) and the 3rd thin film transistor (TFT) are electrically connected with data line and scanning linear respectively, and first, second and the 3rd thin film transistor (TFT) have the first channel breadth length ratio, second channel breadth length ratio and the 3rd channel breadth length ratio respectively, wherein the first channel breadth length ratio is less than the second channel breadth length ratio, and the second channel breadth length ratio is identical with the 3rd channel breadth length ratio.In addition, first pixel electrode, second pixel electrode and the 3rd pixel electrode are electrically connected with first, second and the 3rd thin film transistor (TFT) respectively.On the other hand, first common lines, second common lines and the 3rd common lines are disposed at the below of first, second and the 3rd pixel electrode respectively, wherein first and second common lines can be electrically connected to one first voltage, and the 3rd common lines can be electrically connected to one second voltage.
In one embodiment of this invention, described first, second and the 3rd thin film transistor (TFT) be jointly with the part of scanning linear as its grid.In addition, first, second and the 3rd thin film transistor (TFT) be jointly with a source electrode being electrically connected with data line as source electrode.In addition, the drain electrode of first, second and the 3rd thin film transistor (TFT) is to be electrically connected with first, second and third pixel electrode respectively.
In one embodiment of this invention, described at least one sweep trace comprises first sweep trace and second sweep trace.First and second thin film transistor (TFT) can be electrically connected with first sweep trace, and the 3rd thin film transistor (TFT) can be electrically connected with second sweep trace.In addition, first and second thin film transistor (TFT) be jointly with the some of first scanning linear as its grid, and first and second thin film transistor (TFT) be jointly with the source electrode that is electrically connected with data line as its source electrode.In addition, the drain electrode of first and second thin film transistor (TFT) is to be electrically connected with first and second pixel electrode respectively.On the other hand, the 3rd thin film transistor (TFT) is that some with second scanning linear is as its grid.The source electrode of the 3rd thin film transistor (TFT) can be electrically connected with data line, and the drain electrode meeting of the 3rd thin film transistor (TFT) is electrically connected with the 3rd pixel electrode.
In one embodiment of this invention, the second described voltage is alternating voltage.
In one embodiment of this invention, described dot structure more comprises several protrusions (protrusions), is disposed at the top of first, second and the 3rd pixel electrode.
In one embodiment of this invention, more comprise in described first, second and the 3rd pixel electrode and dispose several slits (slits).
In one embodiment of this invention, described dot structure more comprises first contact hole, second contact hole and the 3rd contact hole, with so that first, second and the 3rd pixel electrode are electrically connected with first, second and the 3rd thin film transistor (TFT) respectively, wherein first, second and the 3rd contact hole are the corresponding respectively tops that is disposed at first, second and the 3rd common lines.
For reaching described or other purpose, the present invention reintroduces a kind of dot structure.This dot structure comprises data line, at least one sweep trace, the first film transistor, second thin film transistor (TFT), the 3rd thin film transistor (TFT), impedance layer, first pixel electrode, second pixel electrode, the 3rd pixel electrode, first common lines, second common lines and the 3rd common lines.Wherein data line and sweep trace are disposed on the substrate.The first film transistor, second thin film transistor (TFT) and the 3rd thin film transistor (TFT) are electrically connected with data line and scanning linear respectively, and have the first channel breadth length ratio, second channel breadth length ratio and the 3rd channel breadth length ratio respectively.Wherein the first channel breadth length ratio, second channel breadth length ratio are identical with the 3rd channel breadth length ratio.In addition, impedance layer and the first film transistor series connection.First pixel electrode, second pixel electrode and the 3rd pixel electrode are electrically connected with first, second and the 3rd thin film transistor (TFT) respectively.First common lines, second common lines and the 3rd common lines are disposed at the below of first, second and the 3rd pixel electrode respectively.Wherein first and second common lines can be electrically connected to first voltage, and the 3rd common lines can be electrically connected to second voltage.
In one embodiment of this invention, described impedance layer is an amorphous silicon layer.
In one embodiment of this invention, described impedance layer is to be connected in series with the first film transistor drain.
In one embodiment of this invention, described first, second and the 3rd thin film transistor (TFT) are to use this a part of scanning linear as its grid jointly.First, second and the 3rd thin film transistor (TFT) be jointly with a source electrode being electrically connected with data line as its source electrode, and the drain electrode of first, second and the 3rd thin film transistor (TFT) is to be electrically connected with first, second and third pixel electrode respectively.
In one embodiment of this invention, at least one described sweep trace comprises first sweep trace and second sweep trace.First and second thin film transistor (TFT) can be electrically connected with first sweep trace, and the 3rd transistor can be electrically connected with second sweep trace.In addition, first and second thin film transistor (TFT) is common to use the first a part of scanning linear as its grid, and first and second thin film transistor (TFT) be jointly with a source electrode being electrically connected with data line as its source electrode.The drain electrode of first and second thin film transistor (TFT) is to be electrically connected with first and second pixel electrode respectively.In addition, the 3rd thin film transistor (TFT) is that second scanning linear with some is as its grid.The source electrode of the 3rd thin film transistor (TFT) can be electrically connected with data line, and the drain electrode meeting of the 3rd thin film transistor (TFT) is electrically connected with the 3rd pixel electrode.
In one embodiment of this invention, the second described voltage is alternating voltage.
In one embodiment of this invention, described dot structure more comprises several protrusions (protrusions), and it is disposed at the top of first, second and the 3rd pixel electrode.
In one embodiment of this invention, more comprise in described first, second and the 3rd pixel electrode and dispose several slits (slits).
In one embodiment of this invention, described dot structure more comprises first contact hole, second contact hole and the 3rd contact hole, with so that first, second and the 3rd pixel electrode be electrically connected with first, second and the 3rd thin film transistor (TFT) respectively.Wherein first, second and the 3rd contact hole are the corresponding respectively tops that is disposed at first, second and the 3rd common lines.
The present invention is because of adopting described structure, therefore when driving this dot structure, first pixel electrode, second pixel electrode and the 3rd pixel electrode have different magnitudes of voltage, so can be so that the liquid crystal molecule on the dot structure have multiple angle of inclination, thus improve the problem of colour cast.
Description of drawings
Figure 1A is the top view of a kind of dot structure of the first embodiment of the present invention.
Figure 1B is the sectional view that the profile line I-I along Figure 1A is illustrated.
Fig. 1 C is the enlarged drawing of the sign scope C1 of Figure 1A.
Fig. 1 D is the enlarged drawing of the sign scope C2 of Figure 1A.
Fig. 2 is the top view of a kind of pixel electrode of another embodiment of the present invention.
Fig. 3 A is the top view of a kind of dot structure of the second embodiment of the present invention.
Fig. 3 B is the sectional view that the profile line II-II along Fig. 3 A is illustrated.
Fig. 4 is the top view of the dot structure of further embodiment of this invention.
Drawing reference numeral:
100: substrate
102: data line
102a: source electrode
103a: first drain electrode
103b: second drain electrode
103c: the 3rd drain electrode
104a: first sweep trace
104b: second sweep trace
106a: the first film transistor
106b: second thin film transistor (TFT)
106c: the 3rd thin film transistor (TFT)
107a: first channel
107b: second channel
107c: the 3rd channel
108a: first pixel electrode
108b: second pixel electrode
108c: the 3rd pixel electrode
109: dielectric layer
110a: first common lines
110b: second common lines
110c: the 3rd common lines
111: protrusion or slit
112: gate insulation layer
114,118a: semiconductor layer
114a, 118b: ohmic contact layer
116a: first contact hole
116b: second contact hole
116c: the 3rd contact hole
118: impedance layer
I-I, II-II: profile line
C1, C2: sign scope
L1, L2, L3: length
V1: first voltage
V2: second voltage
W1, W2, W3: width
W1/L1: the first channel breadth length ratio
W2/L2: second channel breadth length ratio
W3/L3: the 3rd channel breadth length ratio
Embodiment
For described and other purpose, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
For the color offset phenomenon of the Thin Film Transistor-LCD that solves multi-zone vertical alignment nematic, the present invention proposes a kind of dot structure, and it has three pixel electrodes.These three pixel electrodes are electrically connected with three thin film transistor (TFT)s respectively.When driving this dot structure, these three thin film transistor (TFT)s can produce different charge rates, thereby can be so that the liquid crystal molecule on this dot structure produces different angles of inclination, and then solve the problem of colour cast.More specifically, the deviser can adjust channel length and the ratio of channel width, the circuit arrangement of common lines and the resistivity of drain electrode of thin film transistor (TFT), thereby produces different charge rates.Below utilize first embodiment and second embodiment to be described in detail.
First embodiment:
Figure 1A is the top view of a kind of dot structure of the first embodiment of the present invention, and Figure 1B is the sectional view that the profile line I-I along Figure 1A is illustrated, and Fig. 1 C is the enlarged drawing of the sign scope C1 of Figure 1A, and Fig. 1 D is the enlarged drawing of the sign scope C2 of Figure 1A.
Please be simultaneously with reference to Figure 1A and Figure 1B, dot structure of the present invention comprises substrate 100, data line 102, the first sweep trace 104a, the second sweep trace 104b, the first film transistor 106a, the second thin film transistor (TFT) 106b, the 3rd thin film transistor (TFT) 106c, the first pixel electrode 108a, the second pixel electrode 108b, the 3rd pixel electrode 108c, the first common lines 110a, the second common lines 110b and the 3rd common lines 110c.Wherein data line 102, the first sweep trace 104a and the second sweep trace 104b are disposed on the substrate 100.The first film transistor 106a, the second thin film transistor (TFT) 106b and the 3rd thin film transistor (TFT) 106c are electrically connected with data line 102 and the first sweep trace 104a and the second sweep trace 104b respectively.In addition, the first pixel electrode 108a, the second pixel electrode 108b and the 3rd pixel electrode 108c are electrically connected with the first film transistor 106a, the second thin film transistor (TFT) 106b and the 3rd thin film transistor (TFT) 106c respectively.
In addition, the first common lines 110a, the second common lines 110b and the 3rd common lines 110c are disposed at the below of the first pixel electrode 108a, the second pixel electrode 108b and the 3rd pixel electrode 108c respectively.In addition, this dot structure also comprises one dielectric layer 109, it is disposed under the first pixel electrode 108a, the second pixel electrode 108b and the 3rd pixel electrode 108c, and be positioned at substrate 100 tops, use so that the first pixel electrode 108a, the second pixel electrode 108b and the 3rd pixel electrode 108c and data line 102 electrical isolation.The first common lines 110a, the second common lines 110b and the 3rd common lines 110c are the bottom electrodes as reservior capacitor (storagecapacitor).The first film transistor 106a, the second thin film transistor (TFT) 106b and the 3rd thin film transistor (TFT) 106c have the first drain electrode 103a, the second drain electrode 103b, the 3rd drain electrode 103c respectively, respectively as the top electrode of reservior capacitor, and the dielectric layer between upper and lower electrode (for example dielectric layer 112) is the capacitance dielectric layer as reservior capacitor.
Please be simultaneously with reference to Figure 1A to Fig. 1 D, the first film transistor 106a, the second thin film transistor (TFT) 106b and the 3rd thin film transistor (TFT) 106c have the first channel 107a, second channel 107b and the 3rd channel 107c respectively.The first channel 107a, second channel 107b and the 3rd channel 107c have length L 1, L2, L3, width W 1, W2 and W3 respectively.What deserves to be mentioned is that dot structure of the present invention more utilizes the ratio of channel width and channel length so that the respective pixel electrode has different charge rate magnitudes of voltage.More specifically, the first film transistor 106a, the second thin film transistor (TFT) 106b and the 3rd thin film transistor (TFT) 106c have the first channel breadth length ratio W1/L1, second channel breadth length ratio W2/L2 and the 3rd channel breadth length ratio W3/L3 respectively.Wherein the first channel breadth length ratio W1/L1 is less than second channel breadth length ratio W2/L2, and second channel breadth length ratio W2/L2 is identical with the 3rd channel breadth length ratio W3/L3.
On the other hand, the first common lines 110a and the second common lines 110b can be electrically connected to the first voltage V1, and the 3rd common lines 110c can be electrically connected to the second voltage V2.Wherein the first voltage V1 for example is a fixed voltage or ground connection (grounded), and the second voltage V2 for example is an alternating voltage.This alternating voltage is the signal of a rising in the picture frame time of positive polarity (positive polarity) (frame time), and is the signal of a decline in the picture frame time of negative polarity (negative polarity).Thus, when driving this dot structure, the 3rd pixel electrode 108c will make it have bigger voltage (greater than the voltage of the first pixel electrode 108a and the second pixel electrode 108b) because of this alternating voltage capacitance coupling effect, so can make the liquid crystal molecule of the 3rd pixel electrode 108c top have different angles of inclination, thereby improve the problem of colour cast with the liquid crystal molecule of the first pixel electrode 108a and second pixel electrode 108b top.
Moreover present embodiment is that the dot structure with a kind of LCD of multiregional vertical align is an example, and therefore the first pixel electrode 108a, the second pixel electrode 108b and the 3rd pixel electrode 108c top disposes protrusion (protrusion) 111.In another embodiment, each pixel electrode is to dispose a plurality of slits (slits) 111.Yet the present invention is not limited to this, and in other words, this dot structure can also be applied in the LCD of other kind.
By described design, the magnitude of voltage of the second pixel electrode 108b that is electrically connected with the second thin film transistor (TFT) 106b can equal the magnitude of voltage with the 3rd pixel electrode 108c of the 3rd thin film transistor (TFT) 106c, and the magnitude of voltage of the magnitude of voltage of the second pixel electrode 108b that is electrically connected with the second thin film transistor (TFT) 106b, the first pixel electrode 108a that can be electrically connected greater than the first film transistor 106a.And because the 3rd pixel electrode 108c can be because the alternating voltage coupling effect, therefore the voltage of the 3rd pixel electrode 108c can be greater than the voltage of the second pixel electrode 108b, the voltage of the second pixel electrode 108b can be again greater than the voltage of the first pixel electrode 108a.
Hence one can see that, if only consider the influence that the channel breadth length ratio is caused, then when driving this dot structure, the magnitude of voltage of the second pixel electrode 108b can equal the magnitude of voltage of the 3rd pixel electrode 108c, and the magnitude of voltage of the second pixel electrode 108b can be greater than the magnitude of voltage of the first pixel electrode 108a.Yet by as can be known described, because the second voltage V2 can further improve the magnitude of voltage of the 3rd pixel electrode 108c, so when driving this dot structure, the first pixel electrode 108a, the second pixel electrode 108b and the 3rd pixel electrode 108c will have three kinds of different magnitudes of voltage.So, because the liquid crystal molecule of this dot structure top can have three kinds of different angles of inclination, therefore can improve the problem of colour cast effectively.And if this dot structure is applied to the LCD of multiregional vertical align, this design that makes each dot structure have three kinds of different magnitudes of voltage, can be so that the LCD of this multiregional vertical align has more multizone (domains), to improve the problem of colour cast.
Please continue the D with reference to Figure 1A to Fig. 1, the parts of the first film transistor 106a, the second thin film transistor (TFT) 106b and the 3rd thin film transistor (TFT) 106c comprise source electrode 102A, the first drain electrode 103a, the second drain electrode 103b, the 3rd drain electrode 103c, gate insulation layer 112, semiconductor layer 114 and ohmic contact layer 114a.Wherein the first drain electrode 103a, the second drain electrode 103b, the 3rd drain electrode 103c belong to the first film transistor 106a, the second thin film transistor (TFT) 106b and the 3rd thin film transistor (TFT) 106c respectively.In addition, source electrode 102a, gate insulation layer 112, semiconductor layer 114 and ohmic contact layer 114a are respectively the parts of the first film transistor 106a, the second thin film transistor (TFT) 106b and the 3rd thin film transistor (TFT) 106c in different positions.Wherein gate insulation layer 112 covers substrate 100, the first sweep trace 104a and the second sweep trace 104b.Semiconductor layer 114 is positioned on the gate insulation layer 112 of the first sweep trace 104a and second sweep trace 104b top.Source electrode 102a is positioned on the semiconductor layer 114.The first drain electrode 103a and the second drain electrode 103b are positioned on the gate insulation layer 112 of first sweep trace 104a top, and the 3rd drain electrode 103c is positioned on the gate insulation layer 112 of second sweep trace 104b top.Ohmic contact layer 114a is between source electrode 102a, the first drain electrode 103a, the second drain electrode 103b, the 3rd drain electrode 103c and semiconductor layer 114.
In addition, the first film transistor 106a and the second thin film transistor (TFT) 106b for example are electrically connected with the first sweep trace 104a, and the 3rd thin film transistor (TFT) 106c for example is electrically connected with the second sweep trace 104a.In the present embodiment, the first film transistor 106a and the second thin film transistor (TFT) 106b for example be jointly with the part of the first sweep trace 104a as grid, and jointly with a source electrode 102a being electrically connected with data line 102 as source electrode.In addition, the 3rd thin film transistor (TFT) 106c for example is that a part with the second sweep trace 104b is as grid.The source electrode 102a of the 3rd thin film transistor (TFT) 106c for example can be electrically connected with data line 102, and the 3rd drain electrode 103c of the 3rd thin film transistor (TFT) 106c for example can be electrically connected with the 3rd pixel electrode 108c.In the present embodiment, because three thin film transistor (TFT)s all are as grid, so this pixel electrode has high aperture opening ratio (aperture ratio) with sweep trace.
Fig. 2 is the top view of a kind of pixel electrode of another embodiment of the present invention.Please refer to Fig. 2, in another embodiment, three thin film transistor (TFT)s more can be all with the first sweep trace 104a as grid, and omit the second sweep trace 104b, as shown in Figure 2.In Fig. 2, the first film transistor 106a, the second thin film transistor (TFT) 106b and the 3rd thin film transistor (TFT) 106c for example be jointly with the source electrode 102a that is electrically connected with data line 102 as its source electrode, and its first drain electrode 103a, the second drain electrode 103b and the 3rd 103c that drains is electrically connected with the first pixel electrode 108a, the second pixel electrode 108b and the 3rd pixel electrode 108c respectively.Since each thin film transistor (TFT) all be a part with sweep trace as grid, so this dot structure can have higher aperture opening ratio.Wherein, Fig. 2 and Figure 1A only have described difference, and identical parts adopt identical label, and these parts of repeat specification no longer.Certainly, dot structure of the present invention is not as limit, and in other words, each thin film transistor (TFT) also can adopt the various grids that are electrically connected sweep trace.
Please continue with reference to Figure 1A, this dot structure more can comprise the first contact hole 116a, the second contact hole 116b and the 3rd contact hole 116c, uses so that the first pixel electrode 108a, the second pixel electrode 108b and the 3rd pixel electrode 108c are electrically connected with the first film transistor 106a, the second thin film transistor (TFT) 106b and the 3rd thin film transistor (TFT) 106c respectively.Wherein the first contact hole 116a, the second contact hole 116b and the 3rd contact hole 116c for example are the corresponding respectively tops that is disposed at the first common lines 110a, the second common lines 110b and the 3rd common lines 110c.
In the present invention, be that the width of the channel by adjusting thin film transistor (TFT) is bestowed different voltage with the ratio of length and in common lines, so that the thin film transistor (TFT) in three zones of single dot structure has different charge rates.Therefore, when driving dot structure, three pixel electrodes can have different voltage.Below utilize the dot structure of second embodiment that the another kind of application mode of this notion is described.
Second embodiment:
Fig. 3 A is the top view of a kind of dot structure of the second embodiment of the present invention, and Fig. 3 B is the sectional view that the profile line II-II along Fig. 3 A is illustrated.Wherein identical with the dot structure of first embodiment parts will be represented with identical label, and only describe at the part different with first embodiment.In addition, the application mode of the various extensions of the dot structure of first embodiment also can be applied in the dot structure of second embodiment.
Please refer to Fig. 3 A and Fig. 3 B, different with the dot structure of first embodiment is that the first channel breadth length ratio W1/L1, second channel breadth length ratio W2/L2 and the 3rd channel breadth length ratio W3/L3 three of this dot structure are all identical.In addition, similarly, the first common lines 110a and the second common lines 110b are electrically connected with the first voltage V1, and the 3rd common lines 110c is electrically connected with the second voltage V2.Wherein, the first voltage V1 for example is direct current or ground connection, and the second voltage V2 for example is an alternating voltage.In addition, this dot structure has more one deck impedance layer 118, and it is in order to increase by the resistance value of the first drain electrode 103a, and the resistance value that makes the first drain electrode 103a is greater than the second drain electrode 103b and the 3rd drain electrode 103c.
In this embodiment, though the first channel breadth length ratio W1/L1, second channel breadth length ratio W2/L2 and the 3rd channel breadth length ratio W3/L3 three are all identical, but because the transistorized first drain electrode 103a of the first film has higher resistance value, and the 3rd common lines 110c can be electrically connected with the second voltage V2, therefore when driving this dot structure, the magnitude of voltage of the first pixel electrode 108a is less than the magnitude of voltage of the second pixel electrode 108b, and the 3rd pixel electrode 108c will make its voltage rise because of the coupling effect of alternating voltage.Thus, the first pixel electrode 108a, the second pixel electrode 108b and the 3rd pixel electrode 108c can have three kinds of different magnitudes of voltage, so the liquid crystal molecule on this dot structure can have three kinds of angles of inclination, to improve the problem of colour cast.
Please continue the B with reference to Fig. 3, impedance layer 118 is made of semiconductor layer 118a and ohmic contact layer 118b.In the manufacture process of this dot structure, semiconductor layer 118a forms simultaneously with semiconductor layer 114.Semiconductor layer 114 and semiconductor layer 118a for example are one deck amorphous silicon layers.In addition, ohmic contact layer 114a and 118b form simultaneously, and its formation method for example is that described amorphous silicon layer is mixed.It should be noted that in the present embodiment impedance layer 118 for example is to be connected in series with the first drain electrode 103a of the first film transistor 106a, thereby increase by the resistance value of the first drain electrode 103a.Certainly, the second drain electrode 103b or the 3rd drain electrode 103c also can be connected in series with other impedance layer, with the resistance value of each drain electrode of adjustment, thereby meet various design specificationss.
In order to increase the aperture opening ratio of this dot structure, also can adopt the design of Fig. 4.Fig. 4 is the top view of the dot structure of further embodiment of this invention.Please refer to Fig. 4, the first film transistor 106a, the second thin film transistor (TFT) 106b and the 3rd thin film transistor (TFT) 106c all are as grid with the first sweep trace 104a.In addition, this dot structure has also omitted the second sweep trace 104b, and the part source electrode 102a on the second sweep trace 104b.
In three thin film transistor (TFT)s of each described embodiment,, channel design can be become different shape in order to make its channel breadth length ratio that specific relation be arranged.Yet the present invention does not limit the shape of the channel of thin film transistor (TFT), gets final product so long as can make its channel breadth length ratio have its specific relation.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (20)
1. dot structure, described dot structure comprises:
One data line and at least one sweep trace are disposed on the substrate;
One the first film transistor, one second thin film transistor (TFT) and one the 3rd thin film transistor (TFT), be electrically connected with described data line and described scanning linear, and this first, second and the 3rd thin film transistor (TFT) have one first channel breadth length ratio, a second channel breadth length ratio and one the 3rd channel breadth length ratio respectively, wherein this first channel breadth length ratio is less than this second channel breadth length ratio, and this second channel breadth length ratio is identical with the 3rd channel breadth length ratio;
One first pixel electrode, one second pixel electrode and one the 3rd pixel electrode are electrically connected with described first, second and the 3rd thin film transistor (TFT) respectively; And
One first common lines, one second common lines and one the 3rd common lines, be disposed at the below of described first, second and the 3rd pixel electrode respectively, wherein this first and second common lines can be electrically connected to one first voltage, and the 3rd common lines can be electrically connected to one second voltage.
2. dot structure as claimed in claim 1, wherein said first, second and the 3rd thin film transistor (TFT) be jointly with the part of described scanning linear as its grid, this first, second and the 3rd thin film transistor (TFT) be jointly with the one source pole that is electrically connected with described data line as its source electrode, and this first, second and the drain electrode of the 3rd thin film transistor (TFT) be to be electrically connected with the 3rd pixel electrode with described first, second respectively.
3. dot structure as claimed in claim 1, wherein said at least one sweep trace comprises one first sweep trace and one second sweep trace, described first and second thin film transistor (TFT) can be electrically connected with this first sweep trace, and described the 3rd thin film transistor (TFT) can be electrically connected with this second sweep trace.
4. dot structure as claimed in claim 3, wherein said first and second thin film transistor (TFT) be jointly with the some of described first scanning linear as its grid, this first and second thin film transistor (TFT) be jointly with the one source pole that is electrically connected with described data line as its source electrode, the drain electrode of this first and second thin film transistor (TFT) is to be electrically connected with described first and second pixel electrode respectively.
5. dot structure as claimed in claim 3, wherein said the 3rd thin film transistor (TFT) is that some with described second scanning linear is as its grid, and the source electrode of the 3rd thin film transistor (TFT) can be electrically connected with described data line, and the drain electrode meeting of the 3rd thin film transistor (TFT) is electrically connected with described the 3rd pixel electrode.
6. dot structure as claimed in claim 1, wherein said second voltage is an alternating voltage.
7. dot structure as claimed in claim 1 more comprises a plurality of protrusions, is disposed at the top of described first, second and the 3rd pixel electrode.
8. as claim 1 or 7 described dot structures, more comprise in wherein said first, second and the 3rd pixel electrode and dispose a plurality of slits.
9. dot structure as claimed in claim 1, more comprise one first contact hole, one second contact hole and one the 3rd contact hole, with so that described first, second and the 3rd pixel electrode be electrically connected with described first, second and the 3rd thin film transistor (TFT) respectively, wherein this first, second and the 3rd contact hole be the corresponding respectively top that is disposed at described first, second and the 3rd common lines.
10. dot structure, described dot structure comprises:
One data line and at least one sweep trace are disposed on the substrate;
One the first film transistor, one second thin film transistor (TFT) and one the 3rd thin film transistor (TFT), be electrically connected with described data line and described scanning linear respectively, and have one first channel breadth length ratio, a second channel breadth length ratio and one the 3rd channel breadth length ratio respectively, wherein this first channel breadth length ratio, this second channel breadth length ratio are identical with the 3rd channel breadth length ratio;
One impedance layer is with described the first film transistor series connection;
One first pixel electrode, one second pixel electrode and one the 3rd pixel electrode are electrically connected with described first, second and the 3rd thin film transistor (TFT) respectively; And
One first common lines, one second common lines and one the 3rd common lines, be disposed at the below of described first, second and the 3rd pixel electrode respectively, wherein this first and second common lines can be electrically connected to one first voltage, and the 3rd common lines can be electrically connected to one second voltage.
11. dot structure as claimed in claim 10, wherein said impedance layer comprises an amorphous silicon layer.
12. dot structure as claimed in claim 10, wherein said impedance layer are to be connected in series with described the first film transistor drain.
13. dot structure as claimed in claim 10, wherein said first, second and the 3rd thin film transistor (TFT) are to use a part of described scanning linear as its grid jointly, this first, second and the 3rd thin film transistor (TFT) be jointly with the one source pole that is electrically connected with described data line as its source electrode, and this first, second and the drain electrode of the 3rd thin film transistor (TFT) be to be electrically connected with described first, second and third pixel electrode respectively.
14. dot structure as claimed in claim 10, wherein said at least one sweep trace comprises one first sweep trace and one second sweep trace, described first and second thin film transistor (TFT) can be electrically connected with this first sweep trace, and described the 3rd transistor can be electrically connected with this second sweep trace.
15. dot structure as claimed in claim 14, wherein said first and second thin film transistor (TFT) is that common described first scanning linear of some that uses is as its grid, this first and second thin film transistor (TFT) be jointly with the one source pole that is electrically connected with described data line as its source electrode, the drain electrode of this first and second thin film transistor (TFT) is to be electrically connected with described first and second pixel electrode respectively.
16. dot structure as claimed in claim 14, wherein said the 3rd thin film transistor (TFT) is that described second scanning linear with some is as its grid, and the source electrode of the 3rd thin film transistor (TFT) can be electrically connected with described data line, and the drain electrode meeting of the 3rd thin film transistor (TFT) is electrically connected with described the 3rd pixel electrode.
17. dot structure as claimed in claim 10, wherein said second voltage is an alternating voltage.
18. dot structure as claimed in claim 10 more comprises a plurality of protrusions, is disposed at the top of described first, second and the 3rd pixel electrode.
19., more comprise in wherein said first, second and the 3rd pixel electrode and dispose a plurality of slits as claim 10 or 18 described dot structures.
20. dot structure as claimed in claim 10, more comprise one first contact hole, one second contact hole and one the 3rd contact hole, with so that described first, second and the 3rd pixel electrode be electrically connected with described first, second and the 3rd thin film transistor (TFT) respectively, wherein this first, second and the 3rd contact hole be the corresponding respectively top that is disposed at described first, second and the 3rd common lines.
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| CNB2006101470419A CN100451795C (en) | 2006-11-13 | 2006-11-13 | Pixel structure |
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| CN100451795C CN100451795C (en) | 2009-01-14 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101546075B (en) * | 2008-03-24 | 2010-12-01 | 中华映管股份有限公司 | Multi-domain vertical alignment (MVA) pixel structure |
| CN104345509A (en) * | 2013-08-02 | 2015-02-11 | 三星显示有限公司 | Liquid crystal display |
| CN105445966A (en) * | 2014-08-18 | 2016-03-30 | 群创光电股份有限公司 | Low-color-cast display panel |
| CN107290905A (en) * | 2016-04-12 | 2017-10-24 | 三星显示有限公司 | Liquid crystal display device |
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| TWI412858B (en) | 2010-12-29 | 2013-10-21 | Au Optronics Corp | Pixel structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS62182717A (en) * | 1986-02-06 | 1987-08-11 | Nec Corp | Liquid crystal display device |
| JP2737757B2 (en) * | 1997-02-27 | 1998-04-08 | セイコーエプソン株式会社 | Liquid crystal device |
| CN1261918C (en) * | 2002-04-10 | 2006-06-28 | 友达光电股份有限公司 | Driving circuit for display device |
| CN1504816A (en) * | 2002-11-28 | 2004-06-16 | 友达光电股份有限公司 | Dot structure and manufacturing method thereof |
| CN1288486C (en) * | 2003-04-11 | 2006-12-06 | 广辉电子股份有限公司 | Liquid crystal display with double-film transister pixel structure |
| TW200428688A (en) * | 2003-06-05 | 2004-12-16 | Au Optronics Corp | Organic light-emitting display and its pixel structure |
| CN100368916C (en) * | 2005-07-11 | 2008-02-13 | 友达光电股份有限公司 | Vertical arrangement (VA type) liquid crystal display device |
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- 2006-11-13 CN CNB2006101470419A patent/CN100451795C/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101546075B (en) * | 2008-03-24 | 2010-12-01 | 中华映管股份有限公司 | Multi-domain vertical alignment (MVA) pixel structure |
| CN104345509A (en) * | 2013-08-02 | 2015-02-11 | 三星显示有限公司 | Liquid crystal display |
| CN105445966A (en) * | 2014-08-18 | 2016-03-30 | 群创光电股份有限公司 | Low-color-cast display panel |
| CN105445966B (en) * | 2014-08-18 | 2019-04-02 | 群创光电股份有限公司 | The display panel of low colour cast |
| CN107290905A (en) * | 2016-04-12 | 2017-10-24 | 三星显示有限公司 | Liquid crystal display device |
| CN108363246A (en) * | 2018-02-26 | 2018-08-03 | 惠科股份有限公司 | Display panel and curved surface display device |
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| Publication number | Publication date |
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| CN100451795C (en) | 2009-01-14 |
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