CN1941178A - Memory device having latch for charging or discharging data input/output line - Google Patents
Memory device having latch for charging or discharging data input/output line Download PDFInfo
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- CN1941178A CN1941178A CNA2006101100322A CN200610110032A CN1941178A CN 1941178 A CN1941178 A CN 1941178A CN A2006101100322 A CNA2006101100322 A CN A2006101100322A CN 200610110032 A CN200610110032 A CN 200610110032A CN 1941178 A CN1941178 A CN 1941178A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2227—Standby or low power modes
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Abstract
A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes: a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.
Description
Technical field
The present invention relates to a kind of semiconductor storage, and more specifically, relate to a kind of semiconductor storage that is used to prevent the latch units and the leakage current of the data input/output line that is connected with this latch units.
Background technology
Semiconductor storage is categorized as state on and the non-state on (for example, standby and self refresh mode) that is used to carry out read or write operation.When semiconductor storage is in when being used for carrying out the state on of read or write operation, change according to the logic level that reads or write data such as data I/O (I/O) line of universe data I/O line and local area data I/O line.When semiconductor storage was in the non-state on, it was unsteady so that prevent that coupling from reaching to fix data I/O line by latch units with logic level " height " or logic level " low ".
Fig. 1 illustrates the latch units of traditional semiconductor memory devices and the block diagram of universe data I/O line.
Go out as shown, in traditional semiconductor memory devices, have universe data GIO＜0:15〉16 universe data I/O lines 10 be connected with latch units 20 so that no matter semiconductor device is to be in the state also that right and wrong prevent that all universe data I/O line 10 from floating in the state on.Therefore, universe data I/O line 10 is kept logic level " height " or " low " of reading or write data, and it was before latched by latch units 20.
If no matter semiconductor device is to be in the state also right and wrong in the state, universe data I/O line 10 is all kept the logic level that reads or write data that had before been latched by latch units 20, and then universe data I/O line 10 and latch units 20 consume unnecessary electric current according to previous logic level by latch units 20 latched data.
Under the situation of double data rate Synchronous Dynamic Random Access Memory (DDR SDRAM), use 32 universe data I/O lines 10; Under the situation of DDR2 SDRAM, use 64 universe data I/O lines 10; And under the situation of DDR3 SDRAM, use 128 universe data I/O lines 10.When quick operation semiconductor storage, the unnecessary electric current that universe data I/O line 10 and latch units 20 are consumed increases, thereby makes direct current (CD) deterioration.
Summary of the invention
Therefore, purpose of the present invention is for providing a kind of semiconductor storage, and it is used to reduce be in non-universe data input/output line and unnecessary leak current that latch units consumed on the time when this semiconductor storage.
According to an aspect of the present invention, provide a kind of semiconductor storage, it has state on and the non-state on that is used to carry out read or write operation, and this semiconductor storage comprises: data I/O (I/O) line; Latch units, it is used to prevent that this data I/O line from floating; And charhing unit, it is used to control this latch units, when being in the non-state on when this semiconductor storage to this data I/O line charging.
According to a further aspect in the invention, provide a kind of semiconductor storage, it has state on and the non-state on that is used to carry out read or write operation, and this semiconductor storage comprises: data I/O (I/O) line; Latch units, it is used to prevent that this data I/O line from floating; And discharge cell, it is used to control this latch units, when being in the non-state on when this semiconductor storage to this data I/O line discharge.
According to another aspect of the invention, provide a kind of semiconductor storage, it has state on and the non-state on that is used to carry out read or write operation, and this semiconductor storage comprises: data I/O (I/O) line; Last zip deposit receipt unit, it draws this data I/O line on being used for when this semiconductor storage is in non-state on; Pull-down latch unit, it is used for drop-down this data I/O line when this semiconductor storage is in non-state on; And selected cell, it is used for optionally driving the unit of zip deposit receipt this on and this pull-down latch unit one.
Description of drawings
According in conjunction with the accompanying drawings to the following description of preferred embodiment, of the present invention above and other purpose and feature will become obviously, wherein:
Fig. 1 is the latch units of traditional semiconductor memory devices and the block diagram of universe data I/O line;
Fig. 2 is for being used for the block diagram to the semiconductor storage of the latch units of universe data I/O line charge or discharge according to having of the first embodiment of the present invention;
Fig. 3 is the detailed diagram of the selective signal generator shown in Fig. 2;
Fig. 4 is being used under the situation of standby based on clock enable signal and the RAS idle signal block diagram to the last zip deposit receipt unit of universe data I/O line charging according to second embodiment of the invention;
Fig. 5 is used under the situation of standby based on clock enable signal and the RAS idle signal block diagram to the last zip deposit receipt unit of universe data I/O line charging for a third embodiment in accordance with the invention;
Fig. 6 is used under the situation of standby based on clock enable signal and the RAS idle signal block diagram to the pull-down latch unit of universe data I/O line discharge for a fourth embodiment in accordance with the invention;
Fig. 7 is being used under the situation of standby based on clock enable signal and the RAS idle signal block diagram to the pull-down latch unit of universe data I/O line discharge according to a fifth embodiment of the invention;
Fig. 8 is being used under the situation of standby based on the block diagram of clock enable signal to the last zip deposit receipt unit of universe data I/O line charging according to a sixth embodiment of the invention;
Fig. 9 is being used under the situation of standby based on the block diagram of clock enable signal to the last zip deposit receipt unit of universe data I/O line charging according to a seventh embodiment of the invention;
Figure 10 is being used under the situation of standby based on the block diagram of clock enable signal to the pull-down latch unit of universe data I/O line discharge according to the eighth embodiment of the present invention;
Figure 11 is being used under the situation of standby based on the block diagram of clock enable signal to the pull-down latch unit of universe data I/O line discharge according to the ninth embodiment of the present invention;
Figure 12 is being used under the situation of self refresh mode based on the block diagram of self refresh signal to the last zip deposit receipt unit of universe data I/O line charging according to the tenth embodiment of the present invention;
Figure 13 is being used under the situation of self refresh mode based on the block diagram of self refresh signal to the last zip deposit receipt unit of universe data I/O line charging according to the 11st embodiment of the present invention;
Figure 14 is being used under the situation of self refresh mode based on the block diagram of self refresh signal to the pull-down latch unit of universe data I/O line discharge according to the 12nd embodiment of the present invention; And
Figure 15 is being used under the situation of self refresh mode based on the block diagram of self refresh signal to the pull-down latch unit of universe data I/O line discharge according to the 13rd embodiment of the present invention.
Embodiment
Hereinafter, will describe in detail with reference to the accompanying drawings according to semiconductor storage of the present invention.
Fig. 2 is for being used for the block diagram to the semiconductor storage of the latch units of universe data I/O line charge or discharge according to having of the first embodiment of the present invention.
Go out as shown, semiconductor storage comprises universe data I/O (I/O) line 100, latch units, charhing unit, discharge cell and selected cell 300.
Latch units is coupled to universe data I/O line 100, and prevents that universe data I/O line 100 from floating.When semiconductor storage non-on the time, charhing unit via latch units to universe data I/O line 100 chargings.When semiconductor storage non-on the time, discharge cell via latch units to universe data I/O line 100 discharges.Selected cell 300 optionally drives in charhing unit and the discharge cell.
Charhing unit and a part of latch units are expressed as zip deposit receipt unit 200 herein; And discharge cell and another part latch units be expressed as pull-down latch unit 400.
Selected cell 300 comprises selects signal generation unit 310 and multiplexer 320.Select signal generation unit 310 to produce and select signal SELB so which in zip deposit receipt unit 200 and the pull-down latch unit 400 definite selection go up.Multiplexer 320 is selected in zip deposit receipt unit 200 and the pull-down latch unit 400 and is driven selected unit based on selecting signal SELB.
Next the method that is used for optionally driving zip deposit receipt unit 200 and pull-down latch unit 400 is described.
At first, relatively by the measured amount of leakage current that in universe data I/O line 100, flows of proving installation, with the transistor of selecting by selected cell 300 that in last zip deposit receipt unit 200 or pull-down latch unit 400, has in mobile amount of leakage current.
When the amount of leakage current that in universe data I/O line 100, flows during, universe data I/O line 100 is discharged to ground voltage VSS so that the saving magnitude of current greater than the amount of leakage current that in the transistor of last zip deposit receipt unit 200 or pull-down latch unit 400, flows.Otherwise, promptly, the amount of leakage current that flows in universe data I/O line 100 is less than the amount of leakage current that flows in the transistor of last zip deposit receipt unit 200 or pull-down latch unit 400, by supply voltage (for example, week polygonal voltage VPERI) to universe data I/O line 100 charging, so that prevent unnecessary current drain.
In the present invention, the non-state on of semiconductor storage comprises standby and self refresh mode.Specifically, effect of the present invention maximizes in standby or self refresh mode.
In addition, universe data I/O line 100 can not only comprise local area data I/O line, and can comprise all data I/O line, and it fixes with logic level " height " or " low " by latch units so that prevent universe data I/O line 100 unsteady or couplings.
In addition, the present invention can comprise zip deposit receipt unit 200 and pull-down latch unit 400 and not have selected cell 300.
Fig. 3 is the detailed diagram of the selective signal generator 310 shown in Fig. 2.
Go out as shown, selective signal generator 310 comprises a plurality of MOS transistor, fuse FUSE1 and a plurality of inversion device.
The one PMOS transistor P1, fuse FUSE1 and the first nmos pass transistor N1 to the, three nmos pass transistor N3 are connected in series between all polygonal voltage VPERI and the ground voltage VSS.Each of the one PMOS transistor P1 and the first nmos pass transistor N1 all has the grid that is used to be received in the test mode select signal TM_SEL that enables during the test pattern.Each of the second nmos pass transistor N2 and the 3rd nmos pass transistor N3 all has the grid that is used to receive all polygonal voltage VPERI.After test pattern, the fixing logic level of selecting signal SELB of fuse FUSE1.The first inversion device IV4 has input terminal, and it is coupled to the common terminal of the first nmos pass transistor N1 and fuse FUSE1; The second inversion device IV5 has input terminal, and it is coupled to the lead-out terminal of the first inversion device IV4; And the 3rd inversion device IV6 has the input terminal that the lead-out terminal with the second inversion device IV5 couples and is used to export the lead-out terminal of selecting signal SELB.The 4th nmos pass transistor N4 is coupled between the common terminal of ground voltage VSS and the first nmos pass transistor N1 and fuse FUSE1, and it has the grid of the output that is used to receive the first nmos pass transistor IV4.
When activating test mode select signal TM_SEL, also use logic level " height " to activate and select signal SELB with logic level " height ".As a result, make universe data I/O line 100 discharges be logic level " low ".Otherwise, promptly when cancelling activation test mode select signal TM_SEL with logic level " low ", also use logic level " low " to cancel and activate selection signal SELB.As a result, make universe data I/O line 100 be charged as logic level " height ".
As described above, when between charge period at least one universe data I/O line 100 being cancelled when activating to logic level " low ", the present invention can reduce mobile leakage current in the transistor in last zip deposit receipt unit 200 or pull-down latch unit 400.Similarly, when when interdischarge interval activates at least one universe data I/O line 100 for logic level " height ", may reduce the leakage current that flows in the transistor in last zip deposit receipt unit 200 or pull-down latch unit 400.
Hereinafter, to Figure 15,, detailed description is used for that the last zip deposit receipt first 200 of 100 chargings of universe data I/O line and discharge and pull-down latch unit 400 are not had selected cell 300 with reference to figure 4 according to other embodiments of the invention.
Fig. 4 is being used for during standby based on clock enable signal and the RAS idle signal block diagram to the last zip deposit receipt unit of universe data I/O line charging according to a second embodiment of the present invention.
Go out as shown, the last zip deposit receipt 200A of unit comprises charhing unit 220A and latch units 240A.Charhing unit 220A determines the logic level of the charging signals CH_SIG that produces by combination clock enable signal CKE and RAS idle signal RAS_IDLE.
Fig. 5 is used for during standby based on clock enable signal and the RAS idle signal block diagram to the last zip deposit receipt unit of universe data I/O line charging for a third embodiment in accordance with the invention.
Go out as shown, the last zip deposit receipt 200B of unit comprises charhing unit 220B and latch units 240B.Charhing unit 220B determines the logic level of the charging signals CH_SIG that produces by combination clock enable signal CKE and RAS idle signal RAS_IDLE.
Charhing unit 220B comprises the first inversion device INV3 and a NAND door NAND2.The first inversion device INV3 receives RAS idle signal RAS_IDLE and with its counter-rotating.The one NAND door NAND2 carries out the NAND computing to the output of the clock enable signal CKE and the first inversion device INV3, and charging signals CH_SIG is outputed to latch units 240B.
With reference to figure 4 and Fig. 5, if being cancelled to activate, the clock enable signal CKE of the enabled state of expression clock signal is logic level " low ", or the RAS idle signal RAS_IDLE that standby is shown is activated as logic level " height ", then charhing unit via latch units with logic level " height " to universe data I/O line charging.
Fig. 6 illustrates being used for during standby based on clock enable signal and RAS idle signal of a fourth embodiment in accordance with the invention and to the block diagram of the pull-down latch unit of universe data I/O line discharge.
Go out as shown, pull-down latch unit 400A comprises discharge cell 420A and latch units 440A.Discharge cell 420A determines the logic level of the discharge signal DISCH_SIG that produces by combination clock enable signal CKE and RAS idle signal RAS_IDLE.
Discharge cell 420A comprises the first inversion device INV5 and a NAND door NAND3.The first inversion device INV5 receives RAS idle signal RAS_IDLE and with its counter-rotating.The one NAND door NAND3 carries out the NAND computing to the output of the clock enable signal CKE and the first inversion device INV5, and discharge signal DISCH_SIG is outputed to latch units 440A.
Latch units 440A comprises the first NOR gate NOR3 and the second inversion device INV6.The one NOR door NOR3 has a lead-out terminal that is used to receive the input terminal of discharge signal DISCH_SIG and is coupled to universe data I/O line 100.The second inversion device INV6 reverses the output of a NOR door NOR3, and will output to another input terminal of a NOR door NOR3 through the signal of counter-rotating.
Fig. 7 be illustrate according to a fifth embodiment of the invention be used for during standby based on clock enable signal and RAS idle signal and to the block diagram of the pull-down latch unit of universe data I/O line discharge.
Go out as shown, pull-down latch unit 400B comprises discharge cell 420B and latch units 440B.Discharge cell 420B determines the logic level of the discharge signal DISCH_SIG that produces by combination clock enable signal CKE and RAS idle signal RAS_IDLE.
Discharge cell 420B comprises the first inversion device INV7 and a NOR door NOR4.The first inversion device INV7 receive clock enable signal CKE and with its counter-rotating.The one NOR door NOR4 carries out the NOR computing to the output of the RAS idle signal RAS_IDLE and the first inversion device INV7, and discharge signal DISCH_SIG is outputed to latch units 440B.
Latch units 440B comprises a NAND door NAND4 and the second inversion device INV8.The one NAND door NAND4 has an input terminal that is used to receive discharge signal DISCH_SIG.The second inversion device INV8 reverses the output of a NAND door NAND4, and will output to another input terminal of a universe data I/O line 100 and a NAND door NAND4 through the signal of counter-rotating.
Referring to Fig. 6 and Fig. 7, if being cancelled to activate, clock enable signal CKE is logic level " low ", and RAS idle signal RAS_IDLE is activated as logic level " height ", and then discharge cell discharges to universe data I/O line with logic level " low " via latch units.
Fig. 8 be illustrate according to a sixth embodiment of the invention be used for during standby based on the clock enable signal and to the block diagram of the last zip deposit receipt unit of universe data I/O line charging.
Go out as shown, the last zip deposit receipt 200C of unit comprises charhing unit 220C and latch units 240C.Charhing unit 220C determines the logic level of charging signals CH_SIG based on clock enable signal CKE.
Charhing unit 220C receive clock enable signal CKE also outputs to latch units 240C with this clock enable signal CKE as charging signals CH_SIG.
Fig. 9 be illustrate according to a seventh embodiment of the invention be used for during standby based on the clock enable signal and to the block diagram of the last zip deposit receipt unit of universe data I/O line charging.
Go out as shown, the last zip deposit receipt 200D of unit comprises charhing unit 220D and latch units 240D.Charhing unit 220D determines the logic level of charging signals CH_SIG based on clock enable signal CKE.
Charhing unit 220D comprises the first inversion device INV10, and it is used for the counter-rotating with clock enable signal CKE, and will output to latch units 240D as charging signals CH_SIG through the signal of counter-rotating.
Latch units 240D comprises a NOR door NOR5 and the second inversion device INV11.The one NOR door NOR5 has an input terminal that is used to receive charging signals CH_SIG.The second inversion device INV11 reverses the output of a NOR door NOR5, and will output to another input terminal of a universe data I/O line 100 and a NOR door NOR5 through the signal of counter-rotating.
Referring to Fig. 8 and Fig. 9, if being cancelled to activate, the clock enable signal CKE of the enabled state of expression clock signal is logic level " low ", then charhing unit charges to universe data I/O line with logic level " height " via latch units.
Figure 10 illustrates according to being used for during standby based on the clock enable signal of the eighth embodiment of the present invention and to the block diagram of the pull-down latch unit of universe data I/O line discharge.
Go out as shown, pull-down latch unit 400C comprises discharge cell 420C and latch units 440C.Discharge cell 420C determines the logic level of discharge signal DISCH_SIG based on clock enable signal CKE.
Figure 11 illustrates according to being used for during standby based on the clock enable signal of the ninth embodiment of the present invention and to the block diagram of the pull-down latch unit of universe data I/O line discharge.
Go out as shown, pull-down latch unit 400D comprises discharge cell 420D and latch units 440D.Discharge cell 420D determines the logic level of discharge signal DISCH_SIG based on clock enable signal CKE.
Discharge cell 420D receive clock enable signal CKE, and this clock enable signal CKE outputed to latch units 440D as discharge signal DISCH_SIG.
Latch units 440D comprises a NAND door NAND6 and the first inversion device INV14.The one NAND door NAND6 has an input terminal that is used to receive discharge signal DISCH_SIG.The first inversion device INV14 reverses the output of a NAND door NAND6, and will output to another input terminal of a universe data I/O line 100 and a NAND door NAND6 through the signal of counter-rotating.
With reference to Figure 10 and Figure 11, if being cancelled to activate, the clock enable signal CKE of the enabled state of expression clock signal is logic level " low ", then discharge cell discharges to universe data I/O line with logic level " low " via latch units.
Figure 12 illustrates according to being used for during self refresh mode based on the self refresh signal of the tenth embodiment of the present invention and to the block diagram of the last zip deposit receipt unit of universe data I/O line charging.
Go out as shown, the last zip deposit receipt 200E of unit comprises charhing unit 220E and latch units 240E.Charhing unit 220E determines the logic level of charging signals CH_SIG based on self refresh signal SREF.
Figure 13 illustrates according to being used for during self refresh mode based on the self refresh signal of the 11st embodiment of the present invention and to the block diagram of the last zip deposit receipt unit of universe data I/O line charging.
Go out as shown, the last zip deposit receipt 200F of unit comprises charhing unit 220F and latch units 240F.Charhing unit 220F determines the logic level of charging signals CH_SIG based on self refresh signal SREF.
With reference to Figure 12 and Figure 13, if the self refresh signal SREF of expression self refresh mode is activated as logic level " height ", then charhing unit charges to universe data I/O line with logic level " height " via latch units.
Figure 14 illustrates according to being used for during self refresh mode based on the self refresh signal of the 12nd embodiment of the present invention and to the block diagram of the pull-down latch unit of universe data I/O line discharge.
Go out as shown, pull-down latch unit 400E comprises discharge cell 420E and latch units 440E.Discharge cell 420E determines the logic level of discharge signal DISCH_SIG based on self refresh signal SREF.
Discharge cell 420E is received from update signal SREF, and self refresh signal SREF is outputed to latch units 440E as discharge signal DISCH_SIG.
Latch units 440E comprises a NOR door NOR8 and the first inversion device INV18.The one NOR door NOR8 has a lead-out terminal that is used to receive the input terminal of discharge signal DISCH_SIG and is coupled to universe data I/O line 100.The first inversion device INV18 reverses the output of a NOR door NOR8, and will output to another input terminal of a NOR door NOR8 through the signal of counter-rotating.
Figure 15 illustrates according to being used for during self refresh mode based on the self refresh signal of the 13rd embodiment of the present invention and to the block diagram of the pull-down latch unit of universe data I/O line discharge.
Go out as shown, pull-down latch unit 400F comprises discharge cell 420F and latch units 440F.Discharge cell 420F determines the logic level of discharge signal DISCH_SIG based on self refresh signal SREF.
With reference to Figure 14 and Figure 15, if self refresh signal SREF is activated as logic level " height ", then discharge cell discharges to universe data I/O line with logic level " low " via latch units.
As described above, in the present invention, semiconductor storage is cancelled the signal that activates universe data I/O line based on notice and to universe data I/O line 100 charge or discharge, for example, this signal is clock enable signal CKE and RAS idle signal RAS_IDLE under the situation of standby, and is self refresh signal SREF under the situation of self refresh mode.Therefore, by to universe data I/optionally charge or discharge of O line 100, may reduce to flow through the leakage current of zip deposit receipt unit 200 or pull-down latch unit 400 and universe data I/O line 100.In addition, may improve the characteristic of the direct current (DC) of semiconductor storage.
The application's case contains the theme of the korean patent application case submitted in Korean Patent office relevant on September 29th, 2005 and on Dec 28th, 2005 2005-91566 number and 2005-132577 number, and the full content of this patent application case is incorporated herein by reference.
Though described the present invention, it should be obvious to a one skilled in the art that and under situation about not breaking away from, to make variations and modifications as hereinafter the spirit and scope of the present invention that claim limited in conjunction with specific embodiment.
Claims (46)
1. semiconductor storage, it has state on and the non-state on that is used to carry out read or write operation, and this semiconductor storage comprises:
Data I/O (I/O) line;
Latch units, it is used to prevent that this data I/O line from floating; And
Charhing unit, it is used to control this latch units, when being in this non-state on when this semiconductor storage to this data I/O line charging.
2. according to the semiconductor storage of claim 1, wherein this non-state on comprises standby and self refresh mode.
3. according to the semiconductor storage of claim 2, wherein this charhing unit is determined the logic level of the output signal of this latch units based on the clock enable signal and the charging signals that column address strobe (RAS) idle signal that changes this standby produces of the enabled state of the clock signal of representing this semiconductor storage by combination.
4. according to the semiconductor storage of claim 2, wherein this charhing unit is determined the logic level of the output signal of this latch units based on the charging signals that the clock enable signal of enabled state of the clock signal by using this semiconductor storage of expression produces.
5. according to the semiconductor storage of claim 2, wherein this charhing unit is determined the logic level of the output signal of this latch units based on the charging signals that produces by the self refresh signal that uses this self refresh mode of transformation.
6. semiconductor storage, it has state on and the non-state on that is used to carry out read or write operation, and this semiconductor storage comprises:
Data I/O (I/O) line;
Latch units, it is used to prevent that this data I/O line from floating; And
Discharge cell, it is used to control this latch units, when being in this non-state on when this semiconductor storage to this data I/O line discharge.
7. according to the semiconductor storage of claim 6, wherein this non-state on comprises standby and self refresh mode.
8. according to the semiconductor storage of claim 7, wherein this discharge cell is determined the logic level of the output signal of this latch units based on the clock enable signal and the discharge signal that column address strobe (RAS) idle signal that changes this standby produces of the enabled state of the clock signal of representing this semiconductor storage by combination.
9. according to the semiconductor storage of claim 7, wherein this discharge cell is determined the logic level of the output signal of this latch units based on the discharge signal that the clock enable signal of the enabled state of the clock signal by using this semiconductor storage of expression produces.
10. according to the semiconductor storage of claim 7, wherein this discharge cell is determined the logic level of the output signal of this latch units based on the discharge signal that produces by the self refresh signal that uses this self refresh mode of transformation.
11. a semiconductor storage, it has state on and the non-state on that is used to carry out read or write operation, and this semiconductor storage comprises:
Data I/O (I/O) line;
Last zip deposit receipt unit, it draws this data I/O line on being used for when this semiconductor storage is in this non-state on;
Pull-down latch unit, it is used for drop-down this data I/O line when this semiconductor storage is in this non-state on; And
Selected cell, its be used for optionally driving on this zip deposit receipt unit and this pull-down latch unit it
12. according to the semiconductor storage of claim 11, wherein non-state on comprises standby and self refresh mode.
13., wherein should go up zip deposit receipt unit and comprise according to the semiconductor storage of claim 12:
Latch units, it is used to prevent that this data I/O line from floating; And
Charhing unit, it is used to control this latch units, when being in this non-state on when this semiconductor storage to this data I/O line charging.
14. semiconductor storage according to claim 13, wherein this charhing unit is determined the logic level of the output signal of this latch units based on the clock enable signal and the charging signals that column address strobe (RAS) idle signal that changes this standby produces of the enabled state of the clock signal of representing this semiconductor storage by combination.
15. according to the semiconductor storage of claim 14, wherein this charhing unit comprises:
First inversion device, it is used for this clock enable signal counter-rotating; And
The NOR door, it is used for the NOR computing is carried out in the output of this RAS idle signal and this first inversion device, so that described charging signals is outputed to described latch units.
16. according to the semiconductor storage of claim 15, wherein this latch units comprises:
The NAND door, it has the lead-out terminal that an input terminal and that is used to receive this charging signals is coupled to this data I/O line; And
Second inversion device, it is used for the output counter-rotating with this NAND door, and will be somebody's turn to do another input terminal that outputs to this NAND door through the signal of counter-rotating.
17. according to the semiconductor storage of claim 14, wherein this charhing unit comprises:
First inversion device, it is used for this RAS idle signal counter-rotating; And
The NAND door, it is used for the NAND computing is carried out in the output of this clock enable signal and this first inversion device, so that described charging signals is outputed to described latch units.
18. according to the semiconductor storage of claim 17, wherein this latch units comprises:
The NOR door, it has the input terminal that is used to receive this charging signals; And
Second inversion device, it is used for the output counter-rotating with this NOR door, and will be somebody's turn to do this data I/O line that outputs to another input terminal that is coupled to this NOR door through the signal of counter-rotating.
19. semiconductor storage according to claim 13, wherein this charhing unit is determined the logic level of the output signal of this latch units based on the charging signals that the clock enable signal of the enabled state of the clock signal by using this semiconductor storage of expression produces.
20. according to the semiconductor storage of claim 19, wherein this latch units comprises:
The NAND door, it has the lead-out terminal that an input terminal and that is used to receive this charging signals is coupled to this data I/O line; And
Inversion device, it is used for the output counter-rotating with this NAND door, and will be somebody's turn to do another input terminal that outputs to this NAND door through the signal of counter-rotating.
21. according to the semiconductor storage of claim 19, wherein this charhing unit comprises first inversion device, it is used for this clock enable signal counter-rotating, and the signal that will be somebody's turn to do through counter-rotating outputs to this latch units as this charging signals.
22. according to the semiconductor storage of claim 21, wherein this latch units comprises:
The NOR door, it has an input terminal that is used to receive this charging signals; And
Second inversion device, it is used for the output counter-rotating with this NOR door, and will be somebody's turn to do this data I/O line that outputs to another input terminal that is coupled to this NOR door through the signal of counter-rotating.
23. according to the semiconductor storage of claim 13, wherein this charhing unit is determined the logic level of the output signal of this latch units based on the charging signals that produces by the self refresh signal that uses this self refresh mode of transformation.
24. according to the semiconductor storage of claim 23, wherein this charhing unit comprises first inversion device, it is used for this self refresh signal counter-rotating, and the signal that will be somebody's turn to do through counter-rotating outputs to this latch units as this charging signals.
25. according to the semiconductor storage of claim 24, wherein this latch units comprises:
The NAND door, it has the lead-out terminal that an input terminal and that is used to receive this charging signals is coupled to this data I/O line; And
Second inversion device, it is used for the output counter-rotating with this NAND door, and will be somebody's turn to do another input terminal that outputs to this NAND door through the signal of counter-rotating.
26. according to the semiconductor storage of claim 23, wherein this latch units comprises:
The NOR door, it has an input terminal that is used to receive this charging signals; And
Inversion device, it is used for the output counter-rotating with this NOR door, and will be somebody's turn to do this data I/O line that outputs to another input terminal that is coupled to this NOR door through the signal of counter-rotating.
27. according to the semiconductor storage of claim 12, wherein this pull-down latch unit comprises:
Latch units, it is used to prevent that this data I/O line from floating; And
Discharge cell, it is used to control this latch units, when being in this non-state on when this semiconductor storage to this data I/O line discharge.
28. semiconductor storage according to claim 27, wherein this discharge cell is determined the logic level of the output signal of this latch units based on the clock enable signal and the discharge signal that column address strobe (RAS) idle signal that changes this standby produces of the enabled state of the clock signal of representing this semiconductor storage by combination.
29. according to the semiconductor storage of claim 28, wherein this discharge cell comprises:
First inversion device, it is used for this RAS idle signal counter-rotating; And
The NAND door, it is used for the NAND computing is carried out in the output of this clock enable signal and this first inversion device, thereby this discharge signal is outputed to this latch units.
30. according to the semiconductor storage of claim 29, wherein this latch units comprises:
The NOR door, it has the lead-out terminal that an input terminal and that is used to receive this discharge signal is coupled to this data I/O line; And
Second inversion device, it is used for the output counter-rotating with this NOR door, and will be somebody's turn to do another input terminal that outputs to this NOR door through the signal of counter-rotating.
31. according to the semiconductor storage of claim 28, wherein this discharge cell comprises:
First inversion device, it is used for this clock enable signal counter-rotating; And
The NOR door, it is used for the NOR computing is carried out in the output of this RAS idle signal and this first inversion device, thereby this discharge signal is outputed to this latch units.
32. according to the semiconductor storage of claim 31, wherein this latch units comprises:
The NAND door, it has an input terminal that is used to receive this discharge signal; And
Second inversion device, it is used for the output counter-rotating with this NAND door, and will be somebody's turn to do this data I/O line that outputs to another input terminal that is coupled to this NAND door through the signal of counter-rotating.
33. semiconductor storage according to claim 27, wherein this discharge cell is determined the logic level of the output signal of this latch units based on the discharge signal that the clock enable signal of the enabled state of the clock signal by using this semiconductor storage of expression produces.
34. according to the semiconductor storage of claim 33, wherein this discharge cell comprises first inversion device, it is used for this clock enable signal counter-rotating, and the signal that will be somebody's turn to do through counter-rotating outputs to this latch units as this discharge signal.
35. according to the semiconductor storage of claim 34, wherein this latch units comprises:
The NOR door, it has the lead-out terminal that an input terminal and that is used to receive this discharge signal is coupled to this data I/O line; And
Second inversion device, it is used for the output counter-rotating with this NOR door, and will be somebody's turn to do another input terminal that outputs to this NOR door through the signal of counter-rotating.
36. according to the semiconductor storage of claim 33, wherein this latch units comprises:
The NAND door, it has an input terminal that is used to receive this discharge signal; And
Inversion device, it is used for the output counter-rotating with this NAND door, and will be somebody's turn to do this data I/O line that outputs to another input terminal that is coupled to this NAND door through the signal of counter-rotating.
37. according to the semiconductor storage of claim 27, wherein this discharge cell is determined the logic level of the output signal of this latch units based on the discharge signal that produces by the self refresh signal that uses this self refresh mode of transformation.
38. according to the semiconductor storage of claim 37, wherein this latch units comprises:
The NOR door, it has the lead-out terminal that an input terminal and that is used to receive this discharge signal is coupled to this data I/O line; And
Inversion device, it is used for the output counter-rotating with this NOR door, and will be somebody's turn to do another input terminal that outputs to this NOR door through the signal of counter-rotating.
39. according to the semiconductor storage of claim 37, wherein this discharge cell comprises first inversion device, it is used for this self refresh signal counter-rotating, and the signal that will be somebody's turn to do through counter-rotating outputs to this latch units as this discharge signal.
40. according to the semiconductor storage of claim 39, wherein this latch units comprises:
The NAND door, it has an input terminal that is used to receive this discharge signal; And
Second inversion device, it is used for the output counter-rotating with a NAND door, and will be somebody's turn to do this data I/O line that outputs to another input terminal that is coupled to a NAND door through the signal of counter-rotating.
41. according to the semiconductor storage of claim 12, wherein this selected cell comprises:
Select the signal generation unit, it is used for producing in response to the test mode select signal that enables the selection signal during test pattern; And
Multi-task unit, it is used for based on this selection signal is one of this data I/this charhing unit of O line options and this discharge cell.
42. according to the semiconductor storage of claim 41, wherein this multi-task unit comprises:
Inversion device, it is used for this selection signal counter-rotating;
First transmission gate, it is used for the output in response to this selection signal and this inversion device, and the output of the latch units of will charging transfers to this data I/O line; And
Second transmission gate, it is used for the output in response to this selection signal and this inversion device, and the output of the latch units of will discharging transfers to this data I/O line.
43. according to the semiconductor storage of claim 41, wherein this selection signal generation unit comprises fuse, this fuse is used for fixing the logic level of this selection signal after this test pattern.
44. according to the semiconductor storage of claim 41, wherein this selection signal generation unit comprises:
First MOS transistor, it has a grid that is coupled to the terminal of supply voltage and is used to receive this test mode select signal;
Fuse, it has the terminal that another terminal with this first MOS transistor couples;
Second MOS transistor, it is coupled between another terminal of ground voltage and this fuse, and has the grid that is used to receive this test mode select signal; And
The inversion device of odd number, it is coupled to the common terminal of this fuse and this second MOS transistor, thereby exports this selection signal.
45. according to the semiconductor storage of claim 11, wherein this data I/O line comprises universe data I/O (I/O) line.
46. according to the semiconductor storage of claim 11, wherein this data I/O line comprises local area data I/O (I/O) line.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20050091566 | 2005-09-29 | ||
| KR91566/05 | 2005-09-29 | ||
| KR1020050132577A KR100665905B1 (en) | 2005-09-29 | 2005-12-28 | Memory device having data line latch for charging or discharging of data input/output line |
| KR132577/05 | 2005-12-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1941178A true CN1941178A (en) | 2007-04-04 |
| CN1941178B CN1941178B (en) | 2011-05-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101100322A Expired - Fee Related CN1941178B (en) | 2005-09-29 | 2006-07-28 | Memory device having latch for charging or discharging data input/output line |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR100665905B1 (en) |
| CN (1) | CN1941178B (en) |
| TW (1) | TWI356420B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105320197A (en) * | 2014-06-19 | 2016-02-10 | 旺宏电子股份有限公司 | Integrated circuit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5006739A (en) | 1987-06-15 | 1991-04-09 | Hitachi, Ltd. | Capacitive load drive circuit |
| US4882507B1 (en) * | 1987-07-31 | 1993-03-16 | Output circuit of semiconductor integrated circuit device | |
| KR970013728A (en) * | 1995-08-16 | 1997-03-29 | 김주용 | Data output buffer |
| JP3846293B2 (en) | 2000-12-28 | 2006-11-15 | 日本電気株式会社 | Feedback type amplifier circuit and drive circuit |
| JP2005190565A (en) * | 2003-12-25 | 2005-07-14 | Seiko Epson Corp | Ferroelectric memory device, electronic equipment and driving method |
-
2005
- 2005-12-28 KR KR1020050132577A patent/KR100665905B1/en active IP Right Grant
-
2006
- 2006-06-30 TW TW095123988A patent/TWI356420B/en not_active IP Right Cessation
- 2006-07-28 CN CN2006101100322A patent/CN1941178B/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105320197A (en) * | 2014-06-19 | 2016-02-10 | 旺宏电子股份有限公司 | Integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1941178B (en) | 2011-05-04 |
| TW200713320A (en) | 2007-04-01 |
| KR100665905B1 (en) | 2007-01-11 |
| TWI356420B (en) | 2012-01-11 |
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