CN1937600A - Equalizer and equalizing method - Google Patents

Abstract

Provided are an equalizer and an equalization method. There is provided an equalizer that includes: a first extracting circuit extracting a plurality of pilot symbols from an inputted signal; an inverse Fourier transform circuit inversely Fourier transforming the extracted plurality of pilot symbols, and computing a complex gain per path; a second extracting circuit extracting a plurality of paths by using the complex gains; a Fourier transform circuit Fourier transforming the extracted paths; and an equalization computing circuit extracting phase components of the Fourier-transformed paths, and carrying out multiplication by using the inputted signal and the extracted phase components.

Description

Equalizer and equalization methods

Technical field

The present invention relates to OFDM (Orthogonal Frequency Division Multiplexing: the demodulation of the signal after digital modulation OFDM), the particularly equalizer (equalizer) and the equalization methods of use frequency pilot sign (pilotsymbol).

Background technology

In ground-wave digital broadcasting (ISDB-T), adopted anti-multipath to disturb stronger OFDM digital modulation mode.For to carrying out demodulation,, scattered pilot (scattered pilot) mode of scattered pilot symbol on frequency direction and time orientation is arranged as separating the amplitude phase reference that calls by the signal (hereinafter referred to as ofdm signal) after the modulation of OFDM modulation system.

Patent documentation 1 discloses the OFDM demodulating equipment, particularly disclose a kind of for the distortion of removing propagation path equilibrium treatment and carry out the automatic equalizer of inverse fourier transform.Existing OFDM demodulating equipment receives the signal with frame structure, and this frame structure comprises: the propagation path of frame symbol, continued access frame symbol is inferred with figure signal and continued access propagation path and is inferred the data symbol of using figure signal.And existing OFDM demodulating equipment is characterised in that: use propagation path to infer with figure signal and infer transfer function, use the transfer function of being inferred to carry out the equilibrium of data symbol.

[patent documentation 1] spy opens 2000-22661

[patent documentation 2] spy opens 2005-45664

[patent documentation 3] spy opens 2004-153811

But, because the OFDM demodulating equipment of patent documentation 1 is a prerequisite with the signal that receives aforesaid frame structure, so there are the following problems: the signal that can not be dispersed with the data structure of frequency pilot sign to the data symbol that is used for ground-wave digital broadcasting carries out demodulation.

In addition, the IFFF circuit 5-1 of the ofdm signal receiving system of patent documentation 2 comprises up-to-date 1 symbolic component and the discrete guide-frequency signal of past 4 symbolic components is carried out invert fast fourier transformation (paragraph [0015]).But the ofdm signal receiving system of patent documentation 2 only makes the signal behind the invert fast fourier transformation pass through LPF, can not remove the noise contribution that comprises in the zone that LPF passes through in advance.Therefore, there are the following problems for the ofdm signal receiving system of patent documentation 2: along with the increase of the noise that comprises in the received signal, the error that transfer path is inferred the result becomes big, makes the receiving feature variation.

In addition, the ofdm signal balancer of patent documentation 3 discloses 4 symbol delay portions (Fig. 5).But patent documentation 3 does not use inverse fourier transform, but the frequency pilot sign of the same subcarrier that is present in the 4th symbol in front is carried out relatively.Therefore, there are the following problems: can not know the variation of the transfer function of transfer path before the frequency pilot sign of the same subcarrier that manifests behind 4 symbols occurs, be easy to generate when 4 symbols change with the transfer function of interior transfer path and can not correctly carry out balanced situation.

Summary of the invention

Therefore, the objective of the invention is to: a kind of equalizer and equalization methods that the signal of the data structure that is dispersed with frequency pilot sign in the data symbol is carried out demodulation is provided.

A kind of equalizer of the present invention possesses: first extracts circuit, extracts a plurality of frequency pilot signs from input signal; The inverse fourier transform circuit carries out inverse fourier transform to a plurality of frequency pilot signs that extract, and calculates the complex gain amount in each path; Second extracts circuit, uses the complex gain amount, extracts a plurality of paths; Fourier transform circuit carries out Fourier transform to the path of extracting; And the balancing operational circuit, the phase component in the path behind the extraction Fourier transform uses the phase component that extracts that input signal is carried out equilibrium.

In addition, a kind of equalization methods of the present invention is: extract a plurality of frequency pilot signs from input signal, the a plurality of frequency pilot signs that extract are carried out inverse fourier transform, calculate the complex gain amount in each path, use the complex gain amount, extract a plurality of paths, Fourier transform is carried out in the path of extracting, the phase component in the path behind the extraction Fourier transform uses the phase component that extracts that input signal is carried out equilibrium.

According to equalizer of the present invention and equalization methods, can carry out demodulation to the signal of the data structure that is dispersed with frequency pilot sign in the data symbol.

Description of drawings

Fig. 1 is the chart of the configuration relation of expression frequency pilot sign and data symbol.

Fig. 2 is the block diagram of expression equalizer of the present invention.

Fig. 3 is the chart of complex gain amount in each path of expression inverse discrete Fourier transformer inverse-discrete.

Fig. 4 is the complex gain amount in each path is represented in expression with quantity of power a chart.

Fig. 5 is the chart of the complex gain amount in the expression path of extracting.

Fig. 6 is the block diagram of structure of the equalizer of expression embodiment 4.

Fig. 7 is the real part composition of each complex gain amount of expression and the chart of time relation.

Fig. 8 is the block diagram of structure of the equalizer of expression embodiment 5.

Fig. 9 is the block diagram of structure of the equalizer of expression embodiment 6.

Figure 10 is the block diagram of structure of the equalizer of expression embodiment 7.

Figure 11 is the block diagram of structure of the equalizer of expression embodiment 8.

Figure 12 is the block diagram of structure of the equalizer of expression embodiment 9.

Figure 13 is the block diagram of structure of the equalizer of expression embodiment 10.

Figure 14 is the block diagram of structure of the equalizer of expression embodiment 11.

Figure 15 is the block diagram of structure of the equalizer of expression embodiment 12.

Figure 16 is the block diagram of structure of the equalizer of expression embodiment 13.

Embodiment

At first, use Fig. 1 that the frame structure of the configuration relation of frequency pilot sign in the scattered pilot mode of expression the present invention use and data symbol is described.The longitudinal axis express time of figure (OFDM symbol), transverse axis is represented frequency.Black circle expression frequency pilot sign among the figure, white circle expression data symbol.In this embodiment, the configuration of same-sign, the cycle with 1 time in 4 OFDM symbols occurs.But, be not limited to this cycle certainly.

Below, use accompanying drawing that equalizer of the present invention and equalization methods are described.

Embodiment 1

Below, equalizer and the equalization methods of embodiment 1 described.When the notion of using Fig. 1 to the equalizer of embodiment 1 and equalization methods described, the equalizer of embodiment 1 and equalization methods used the frequency pilot sign of the OFDM symbol of current (for example t3), and current OFDM symbol is carried out demodulation.

Fig. 2 is the block diagram of the structure of expression equalizer of the present invention.Equalizer of the present invention comprises that the channel of the input signal IN of input behind the Fourier transform infers portion 200 and balancing operational portion 210.Herein, input signal is to be signal after unit carries out Fourier transform with 1 OFDM symbol.

Channel is inferred portion 200 and comprised: frequency pilot sign extracts circuit 201, inverse discrete Fourier transformer inverse-discrete circuit 202, threshold value comparison circuit 203, adjunct circuit 204 and fast Fourier transform circuit 205.

Frequency pilot sign extracts circuit 201 and extract frequency pilot sign from the input signal that is mixed with frequency pilot sign and data symbol.Frequency pilot sign is dispersed in the input signal with predetermined period, and frequency pilot sign extracts circuit 201 and uses this cycle that obtains from the outside to extract frequency pilot sign.Herein, the concrete image that extracts is described.For the purpose of simple, frequency pilot sign is designated as P, data symbol is designated as D.For example, when the data arrangement of input signal was assumed to DDDPDDDPDDDPDDD, the image of so-called extraction was meant D is replaced into 0 (zero).At this moment, the data arrangement of the signal after the extraction is 000P000P000P000.

Inverse discrete Fourier transformer inverse-discrete circuit 202 and frequency pilot sign extract circuit 201 and are connected, and have the inverse discrete Fourier transformer inverse-discrete of presumable time of delay of width, obtain the complex gain amount in the path of respectively arriving.In addition, the complex gain amount not only comprises the transfer function of the transfer path of delay path, also comprises noise and arithmetic eror.Herein, Fig. 3 is expression obtains by inverse discrete Fourier transformer inverse-discrete, the arrive chart of complex gain amount in path respectively.The path 300 of the maximum complex gain amount of expression is estimated to be the signal of directly coming receiving system from the dispensing device of ofdm signal among the figure.On the other hand, path 301～302 is estimated to be: between the transceiver of ofdm signal by barriers such as mansion make ofdm signal reflection, compare the signal that detours with the signal of direct arrival.In addition, path 303 is estimated to be the signal that is produced by noise or arithmetic eror.In addition, inverse discrete Fourier transformer inverse-discrete circuit 202 uses formula as described below to carry out conversion.Herein, the sinusoidal wave coefficient e that uses in the inverse discrete Fourier transformer inverse-discrete ^-j0Because of the insertion position difference of frequency pilot sign, so, need make sinusoidal wave coefficient variable by each OFDM symbol.

(formula 1)

$\mathrm{SP}\_\mathrm{res}(t,1)=\underset{k=0}{\overset{\mathrm{sp}\_\mathrm{num}}{\mathrm{\Σ}}}\mathrm{SP}\_\mathrm{sc}(t,k)e^{j2\mathrm{\π}\[\mathrm{fsp}1\left(t\right)+\mathrm{stp}\×k\]\×\frac{l}{\mathrm{fft}\_\mathrm{num}}}$

Herein, t is the OFDM symbol time, and l is time of delay, and k is the frequency pilot sign number, SP_res (t, l) be the complex gain amount, (t l) is transfer function and the noise of heavily taking advantage of on frequency pilot sign to SP_sc, fsp1 (t) is the subcarrier position at the minimum frequency pilot sign of frequency, stp is the subcarrier frequency interval of frequency pilot sign, and sp_num is the number of the frequency pilot sign of use during transfer path is inferred, and fft_num is that Fourier transform is counted.In addition, in the present invention, showing the inverse discrete Fourier transformer inverse-discrete circuit, still, can certainly be the invert fast fourier transformation circuit.

Then, use Fig. 4 and Fig. 5 that threshold value comparison circuit 203 is described.Fig. 4 is the chart of expression from the quantity of power in the path of respectively arriving that the complex gain amount is calculated.Fig. 5 is the chart of the complex gain amount in the expression path of extracting.Herein, in the OFDM symbol that has with the frequency pilot sign of the subcarrier interval of equalization configuration, compare with effective OFDM symbol lengths, width time of delay of the complex gain amount that can infer in theory is inverse width time of delay before of the subcarrier interval of frequency pilot sign.For example, in ground-wave digital broadcasting, to 1 frequency pilot sign of 12 subcarrier configurations.Become 1/12nd of effective OFDM symbol lengths the time of delay of the complex gain amount that therefore, can infer in theory.That is, in threshold value comparison circuit 203, the complex gain amount that is compared is 1/12nd of the complex gain amount integral body that obtains by inverse discrete Fourier transformer inverse-discrete.

At first, the complex gain amount of threshold value comparison circuit 203 from obtaining by inverse discrete Fourier transformer inverse-discrete obtained the power in each path.Then, threshold value comparison circuit 203 extracts the path 300 of maximum power in the power of being obtained.And threshold value comparison circuit 203 is set relative threshold value 400 according to this maximum power, extracts the path 300～302 with threshold value power more than 400.For example, obtain according to maximum power and be present in predetermined power amount δ with interior path.And the complex gain amount in this path of output, former state ground, path of 203 pairs of extractions of threshold value comparison circuit is to the path output " 0 (zero) " that is not extracted.Herein, threshold value comparison circuit 203 uses formulas Extraction path as described below.

(formula 2)

$\mathrm{SP}\_\mathrm{ph}(t,1)=\left\{\begin{array}{cc}\mathrm{SP}\_\mathrm{res}(t,l)& \mathrm{SP}\_\mathrm{res}(t,l{)}^2\&GreaterEqual;a\&times;\mathrm{SP}\_\mathrm{res}(t,l\max {)}^2\\ 0& \mathrm{SP}\_\mathrm{res}(t,l{)}^2<a\&times;\mathrm{SP}\_\mathrm{res}(t,l\max {)}^2\end{array}\right.$

Herein, t is the OFDM symbol time, and l is time of delay, l _MaxBe the time of delay of the complex gain amount of maximum power, SP_ph (t) is output of threshold ratio, and (t l) is the complex gain amount to SP_res, and α is threshold operation coefficient and 1＞α.

Adjunct circuit 203 is connected with threshold value comparison circuit 202, " 0 (zero) " laggard line output of additional predetermined number in the output of threshold value comparison circuit 202.As mentioned above, compare with effective OFDM symbol lengths, width time of delay of presumable in theory complex gain amount is inverse width time of delay before of the subcarrier interval of frequency pilot sign.The complex gain amount that has alleviated noise and arithmetic eror in threshold value comparison circuit 202 has only this of width time of delay, in order to be undertaken the transfer path of all subcarriers is inferred by Fourier transform, and just must be to all Fourier transforms input value of counting.Therefore, the later time zone of width time of delay that herein needs passing threshold is relatively obtained appends " 0 ".In other words, when the later time zone of width time of delay that passing threshold comparison circuit 202 is obtained applies the value with power, just become and have the arrival path in the time of delay that is equivalent to this time location that applies.Also mean the path of not arriving in this time of delay because append " 0 ", so it is important appending " 0 " herein.

Balancing operational portion 210 comprises updating vector translation circuit 211 and mlultiplying circuit 212.

Updating vector translation circuit 211 extracts the phase component of inferring corresponding to the transfer path of each subcarrier.Because the value that transfer path is inferred has real number and imaginary number, so, generate phase component by the computing of using real number and imaginary number.And being transformed to becomes the laggard line output of the complex conjugate value of phase component.That is, the output of real number former state is exported after the imaginary number reversed polarity.In addition, updating vector translation circuit 211 uses formula as described below to carry out conversion.

(formula 3)

$\cos \left({\tan }^{-1}\left(\frac{\mathrm{Im}}{\mathrm{Re}}\right)\right)-j\sin \left({\tan }^{-1}\left(\frac{\mathrm{Im}}{\mathrm{Re}}\right)\right)$

Mlultiplying circuit 212 with plural number to receiving ofdm signal and carrying out fast fourier transform and multiplying is carried out in the value of each subcarrier that obtains and the output of updating vector translation circuit 211.Thus, offset the phase place rotation that in transfer path, is subjected to, demodulated output data OUT.

As mentioned above, equalizer and equalization methods according to embodiment 1 are provided with threshold value, and the so lower-powered plural number of erased noise or arithmetic eror subtracts the amount of pushing away.Therefore, the equalizer of embodiment 1 and equalization methods, its transfer path estimation error diminishes, and is better at the receiving feature of noise.

And then, according to equalizer and the equalization methods of embodiment 1, unlike existing OFDM demodulating equipment, carry out calculation process repeatedly, can correctly take out with once-through operation and infer the required plural attenuation of transfer path.And then, because do not need to preestablish repeat number, so, even existence have powerful plural number more than the number of repetition subtract the amount of pushing away time of delay the position situation under (delay path very many reception environment under), can not leak yet and get correct transfer path and infer the plural number of needed time of delay of position and subtract the amount of pushing away.Under the very many reception environments of delay path, subtracting the mode of the amount of pushing away and time of delay by the plural number of directly inferring existing transfer path obtains good reception characteristics easily.

And then, according to equalizer and the equalization methods of embodiment 1, infer because carry out transfer path with 1 OFDM symbol, so, under the transfer path characteristic situation different, also can follow by each OFDM symbol of quick decay etc., better at the receiving feature of decay.

Embodiment 2

The path extraction method of the equalizer of embodiment 2 and equalization methods is different with embodiment 1.In the threshold value comparison circuit of embodiment 1, use and extract the path by the complex gain amount being carried out a square quantity of power of obtaining.On the other hand, in the threshold value comparison circuit of embodiment 2, use the real number of complex gain amount and the absolute value of imaginary number to extract the path.

If specifically describe, the threshold value comparison circuit of embodiment 2 is obtained the real number of complex gain amount in each path that obtains and the absolute value of imaginary number in inverse discrete Fourier transformer inverse-discrete circuit 202, by each path the absolute value of real number and imaginary number is carried out add operation.Threshold ratio has the path of add operation result for maximum complex gain amount than circuit extraction.And the threshold value comparison circuit is set relative threshold value according to this maximum add operation result, extracts the path with the above add operation result of threshold value.For example, obtain according to the add operation result of maximum and be present in predetermined value with interior path.And the threshold value comparison circuit is exported the complex gain amount in this path to the path former state of extracting, for the path output " 0 (zero) " that is not extracted.Herein, the threshold value comparison circuit uses formulas Extraction path as described below.

(formula 4)

$\mathrm{SP}\_\mathrm{ph}(t,l)=\left\{\begin{array}{cc}& \mathrm{Re}\{\mathrm{SP}\_\mathrm{res}(t,l)\}+\mathrm{Im}\{\mathrm{SP}\_\mathrm{res}(t,l)\}\\ \mathrm{SP}\_\mathrm{res}(t,l)& \&GreaterEqual;\mathrm{\&alpha;}\&times;\&lsqb;\mathrm{Re}\{\mathrm{SP}\_\mathrm{res}(t,l\max )\}+\mathrm{Im}\{\mathrm{SP}\_\mathrm{res}(t,l\max )\}\&rsqb;\\ 0& \mathrm{Re}\{\mathrm{SP}\_\mathrm{res}(t,l)\}+\mathrm{Im}\{\mathrm{SP}\_\mathrm{res}(t,l)\}\\ & <\mathrm{\&alpha;}\&times;\&lsqb;\mathrm{Re}\{\mathrm{SP}\_\mathrm{res}(t,l\max )\}+\mathrm{Im}\{\mathrm{SP}\_\mathrm{res}(t,l\max )\}\&rsqb;\end{array}\right.$

Herein, t is the OFDM symbol time, and l is time of delay, l _MaxBe the time of delay that becomes maximum add operation result's complex gain amount, SP_ph (t) is output of threshold ratio, and (t l) is the complex gain amount to SP_res, and α is threshold operation coefficient and 1＞α.

As mentioned above, according to equalizer and the equalization methods of embodiment 2, need not to carry out a square calculating for the performance number of obtaining each path.Therefore, the equalizer of embodiment 2 and equalization methods also can use in the demodulation that requires fast processing.

Embodiment 3

The transform method of the equalizer of embodiment 3 and the updating vector of equalization methods is different with embodiment 1 and 2.Embodiment 1 and 2 updating vector translation circuit only extract the phase component of inferring corresponding to the transfer path of each subcarrier.On the other hand, the updating vector translation circuit of embodiment 3 extracts phase component and amplitude.

If specifically describe, the updating vector translation circuit of embodiment 3 uses formula as described below to become the updating vector of the inverse of each subcarrier.

(formula 5)

$\mathrm{SubC}\_T=\frac{\mathrm{Re}\&lsqb;\mathrm{SubC}\&rsqb;-\mathrm{jIm}\&lsqb;\mathrm{SubC}\&rsqb;}{\mathrm{Re}\&lsqb;\mathrm{SubC}{\&rsqb;}^2+\mathrm{Im}\&lsqb;\mathrm{SubC}{\&rsqb;}^2}$

Herein, SubC_T is a updating vector, and SubC is that the transfer path of each subcarrier is inferred the result.

As mentioned above, according to equalizer and the equalization methods of embodiment 3, can be corresponding to the orthogonal amplitude mapping mode that comprises amplitude information (Quadrature Amplitude Modulation:QAM).

In addition, the updating vector translation circuit of embodiment 3 is capable of being combined in the equalizer and equalization methods of embodiment 2.At this moment, equalizer after the combination and equalization methods can have embodiment 2 Hes

The effect of embodiment 3.

Embodiment 4

Then, use accompanying drawing that equalizer and the equalization methods of embodiment 4 are described.Herein, when using Fig. 1 that the notion of the equalizer of embodiment 4 and equalization methods is described, the equalizer of embodiment 4 and equalization methods use the frequency pilot sign of the OFDM symbol of the frequency pilot sign of OFDM symbol of current (for example t3) and the 2nd symbol in front (for example t1), and the OFDM symbol of the 1st symbol in front (for example t2) is carried out demodulation.

Fig. 6 is the block diagram of structure of the equalizer of expression embodiment 4.The equalizer of embodiment 4 comprises 1 symbol delay circuit 600, channel and infers portion 610 and balancing operational portion 210.For the structure identical, omit its explanation herein, with previous embodiment.

1 symbol delay circuit 600 comprises random access memory (hereinafter referred to as RAM), makes input signal postpone to be equivalent to time of 1 symbol, the input signal after the output delay.

Channel is inferred portion 610 and comprised: frequency pilot sign extracts circuit 201, inverse discrete Fourier transformer inverse-discrete circuit 202,2 symbol delay circuit 611, add circuit 612, threshold value comparison circuit 203, adjunct circuit 204 and fast Fourier transform circuits 205.

2 symbol delay circuit 611 comprise RAM, make the time that postpones to be equivalent to 2 symbols from the complex gain amount of inverse discrete Fourier transformer inverse-discrete circuit 202 outputs, the complex gain amount after the output delay.

612 pairs of complex gain amount and complex gain amounts after the delay of 2 symbol delay circuit, 611 outputs from 202 outputs of inverse discrete Fourier transformer inverse-discrete circuit of add circuit are carried out add operation.Herein, add circuit 612 uses 2 values (the complex gain amount after the delay of exporting from the complex gain amount of inverse discrete Fourier transformer inverse-discrete circuit 202 outputs with from 2 symbol delay circuit 611), width time of delay of the complex gain amount that can infer in theory thus, is 1/6th of effective OFDM symbol lengths.Therefore, the complex gain amount of handling in add circuit 612 is from 1/6th of 1/6th and complex gain amount integral body after the delay of 2 symbol delay circuit, 611 outputs of the complex gain amount integral body of inverse discrete Fourier transformer inverse-discrete circuit 202 outputs.In addition, for 2 symbol delay circuit 611, in the complex gain amount that receives from inverse discrete Fourier transformer inverse-discrete circuit 202 is that add circuit 202 can be handled the complex gain amount integral body after the delay of 2 symbol delay circuit, 611 outputs certainly under 1/6th situation of the complex gain amount integral body of inverse discrete Fourier transformer inverse-discrete circuit 202 outputs., use accompanying drawing herein, the work of add circuit 612 is described.Fig. 7 is the real part composition of each complex gain amount of expression and the chart of time relation.The solid line of chart be enter effective OFDM symbol lengths 1/6th with interior real part composition, the dotted line of chart be do not enter effective OFDM symbol lengths 1/6th with interior real part composition.That is, the real part composition of the dotted line of chart is not the operand composition of this add circuit 612.According to add circuit 612, offset, stay with phase constituent from the complex gain amount of inverse discrete Fourier transformer inverse-discrete circuit 202 output and the anti-phase composition of complex gain amount after the delay of 2 symbol delay circuit, 611 outputs.For example, in the identical moment, exist after the delay of 2 symbol delay circuit, 611 outputs complex gain amount 701 and under the situation of the complex gain amount 702 of inverse discrete Fourier transformer inverse-discrete circuit 202 outputs, it is homophase, thus, add circuit 612 is calculated 2 the complex gain amounts 703 after the complex gain amount that add.On the other hand, in the identical moment, exist after the delay of 2 symbol delay circuit, 611 outputs complex gain amount 704 and under the situation of the complex gain amount 705 of inverse discrete Fourier transformer inverse-discrete circuit 202 outputs, it is anti-phase, thus, add circuit 612 is calculated the difference (complex gain amount 706) of 2 complex gain amounts.

Balancing operational portion 210 carries out multiplying with plural number to the input signal that postpones 1 symbol and the output of updating vector translation circuit 211.Thus, offset the phase place rotation that is subjected in the transfer path, demodulated output data OUT.

As mentioned above, according to equalizer and the equalization methods of embodiment 4, play the effect of equalizer and the equalization methods of embodiment 1.

And then, according to equalizer and the equalization methods of embodiment 4, infer owing to use 2 OFDM symbols to carry out transfer path, so, under the very little situation of the variation of the transfer function of transfer path, can carry out than inferring the more high-precision equilibrium of transfer path with 1 OFDM symbol.

And then, according to equalizer and the equalization methods of embodiment 4, infer, so the subcarrier configuration of scattered pilot symbol is identical with 6 subcarrier cycles owing to use 2 OFDM symbols to carry out transfer path.Therefore, the time width that can carry out the arrival path that transfer path infers is to carry out transfer path 2 times when inferring with 1 symbol.Therefore, the equalizer of embodiment 4 and equalization methods can carry out equilibrium to longer delay path of arrival time.

And then, according to equalizer and the equalization methods of embodiment 4, use the scattered pilot symbol that comprises in 1 OFDM symbol of the front and back of carrying out the OFDM symbol after transfer path is proofreaied and correct to carry out transfer path of equal valuely and infer.Therefore, even because of decay waits the transfer function change that makes transfer path, the equalizer of embodiment 4 and equalization methods also can make error reduce.

Embodiment 5

Then, use accompanying drawing that equalizer and the equalization methods of embodiment 5 are described.Herein, when the notion of using Fig. 1 to the equalizer of embodiment 5 and equalization methods describes, identical with equalizer and the equalization methods of embodiment 4, the equalizer of embodiment 5 and equalization methods use the frequency pilot sign of the OFDM symbol of the frequency pilot sign of OFDM symbol of current (for example t3) and 2 symbols of the front mat woven of fine bamboo strips (for example t1), and the OFDM symbol of the 1st symbol in front (for example t2) is carried out demodulation.

Fig. 8 is the block diagram of structure of the equalizer of expression embodiment 5.The equalizer of embodiment 5 comprises 1 symbol delay circuit 600, channel and infers portion 800 and balancing operational portion 210.Herein, omit to the explanation of previous embodiment same structure.

Channel is inferred portion 800 and comprised: frequency pilot sign extracts 201,2 symbol delay circuit 611 of circuit, frequency pilot sign is arranged circuit 801, inverse discrete Fourier transformer inverse-discrete circuit 202, threshold value comparison circuit 203, adjunct circuit 204 and fast Fourier transform circuit 205.

2 symbol delay circuit 611 of embodiment 5 comprise RAM, make at frequency pilot sign and extract the time that the frequency pilot sign that extracts in the circuit 201 postpones to be equivalent to 2 symbols, the frequency pilot sign after the output delay.

The frequency pilot sign that frequency pilot sign is arranged after 801 pairs of frequency pilot signs that extracted of circuit and the delay synthesizes, the frequency pilot sign after output is synthetic.For example, the data arrangement of the frequency pilot sign after the data arrangement of the frequency pilot sign that extracts is 000P000P000, delay is under the situation of 0P000P000P0, and the data arrangement of the frequency pilot sign after synthesizing is 0P0P0P0P0P0.Herein, P represents frequency pilot sign.

The inverse discrete Fourier transformer inverse-discrete circuit 202 of embodiment 5 is obtained the complex gain amount in the path of respectively arriving according to the frequency pilot sign of arranging from frequency pilot sign behind circuit 801 outputs synthetic.

As mentioned above, according to equalizer and the equalization methods of embodiment 5, play the equalizer of embodiment 1 and embodiment 4 and the effect of equalization methods.

Embodiment 6

Then, use accompanying drawing that equalizer and the equalization methods of embodiment 6 are described.Herein, when using Fig. 1 that the equalizer of embodiment 6 and equalization methods are described, the equalizer of embodiment 6 and equalization methods use the frequency pilot sign of the OFDM symbol of the frequency pilot sign of OFDM symbol of 2 symbols of frequency pilot sign, the front mat woven of fine bamboo strips (for example t3) of OFDM symbol of the 1st symbol in frequency pilot sign, front (for example t4) of OFDM symbol of current (for example t5) and the 3rd symbol in front (for example t2), and the OFDM symbol of the 1st symbol in front (for example t4) is carried out demodulation.

Fig. 9 is the block diagram of structure of the equalizer of expression embodiment 6.The equalizer of embodiment 6 comprises 1 symbol delay circuit 600, channel and infers portion 900 and balancing operational portion 210.Herein, omit to the explanation of previous embodiment same structure.

Channel is inferred portion 900 and comprised: frequency pilot sign extracts circuit 201,920,2 symbol delay circuit of 910,1 symbol delay circuit of inverse discrete Fourier transformer inverse-discrete circuit 930,3 symbol delay circuit 940, add circuit 950, threshold value comparison circuit 203, adjunct circuit 204 and fast Fourier transform circuits 205.

Inverse discrete Fourier transformer inverse-discrete circuit 910 carries out the work identical with aforesaid inverse discrete Fourier transformer inverse-discrete circuit 202.And, the operation result before inverse discrete Fourier transformer inverse-discrete circuit 910 kept before implementing computing next time.

1 symbol delay circuit 920 comprises RAM, makes from the complex gain amount of inverse discrete Fourier transformer inverse-discrete circuit 910 outputs to postpone to be equivalent to the time of 1 symbol, and keeps.And 1 symbol delay circuit 920 basis request of reading comes the complex gain amount after the output delay.Similarly, 2 symbol delay circuit 930 and 3 symbol delay circuit 940 also comprise RAM, 2 symbol delay circuit 930 make the time that postpones to be equivalent to 2 symbols from the complex gain amount of inverse discrete Fourier transformer inverse-discrete circuit 910 outputs, 3 symbol delay circuit 940 make from the complex gain amount of inverse discrete Fourier transformer inverse-discrete circuit 910 outputs and postpone to be equivalent to the time of 3 symbols, and keep.And each delay circuit basis is read the complex gain amount after the output delay of request difference.

Add circuit 950 has switching part and the addition portion 955 that is made of switch 951～954.Switch 951 connects inverse discrete Fourier transformer inverse-discrete circuit 910 and addition portion 955, switch 952 connects 1 symbol delay circuit 920 and addition portion 955, switch 953 connects 2 symbol delay circuit 930 and addition portion 955, and switch 954 connects 3 symbol delay circuit 940 and addition portion 955.Add circuit 950 carries out add operation by 951～954 pairs of complex gain amount and complex gain amounts after each delay of 930,3 symbol delay circuit of 920,2 symbol delay circuit of 1 symbol delay circuit, 940 outputs from 910 outputs of inverse discrete Fourier transformer inverse-discrete circuit of diverter switch.As the combination by the signal after the switch connection add operation, it is the ON state that consideration has only switch 952, have only switch 951,953 is that ON state and switch 951,952,953,954 all are three kinds of situations of ON state.Have only switch 952 identical with embodiment 1, only carry out transfer path and infer by the frequency pilot sign that comprises in 1 OFDM symbol for the ON state.Have only switch 951,953 identical with embodiment 5, only carry out transfer path and infer by the frequency pilot sign that comprises in 2 OFDM symbols for the ON state.Switch 951～954 all is that the ON state is identical with present embodiment, only carries out transfer path by the frequency pilot sign that comprises in 4 OFDM symbols and infers.Herein, when making switch 951～954 all be the ON state, because add circuit 950 uses 4 complex gain amounts to carry out add operation, so width time of delay of presumable in theory complex gain amount is 1/3rd of effective OFDM symbol lengths.Relative therewith, have only switch 951,953 identical with embodiment 5 for the ON state, be 1/6th of effective OFDM symbol lengths, have only switch 952 identical with embodiment 1 for the ON state, be 1/12nd of effective OFDM symbol lengths.Mate therewith, 203 threshold value comparison circuits and 204 adjunct circuits carry out the work corresponding with this length.

As mentioned above, according to equalizer and the equalization methods of embodiment 6, play the effect of equalizer and the equalization methods of embodiment 1.

And then, according to equalizer and the equalization methods of embodiment 6, infer owing to use 4 OFDM symbols to carry out transfer path, so, under the very little situation of the variation of the transfer function of transfer path, can carry out than inferring the more high-precision equilibrium of transfer path with 1 OFDM symbol.

And then, according to equalizer and the equalization methods of embodiment 6, infer, so the subcarrier configuration of scattered pilot symbol becomes identical with 3 subcarrier cycles owing to use 1 OFDM symbol to carry out transfer path.Therefore, the time width that can carry out the arrival path that transfer path infers becomes with 1 symbol and carries out transfer path 4 times when inferring.Therefore, the equalizer of embodiment 6 and equalization methods can carry out equilibrium to longer delay path of arrival time.

And then, according to equalizer and the equalization methods of embodiment 6, use the scattered pilot symbol that comprises in the 2nd the OFDM symbol of 1 OFDM symbol in OFDM symbol, front and back and front that carries out after transfer path is proofreaied and correct to carry out transfer path of equal valuely and infer.Therefore, the equalizer of embodiment 6 and equalization methods and SP with 4 OFDM symbols of the scattered pilot symbol that comprises in the 1st OFDM symbol in front of using the OFDM symbol after transfer path is proofreaied and correct, the 3rd OFDM symbol of the 2nd OFDM symbol in front and front carry out transfer path and infer and compare, even, error is diminished because of decay waits the transfer function change that makes transfer path.

Embodiment 7

Then, use accompanying drawing that equalizer and the equalization methods of embodiment 7 are described.Herein, when the notion of using Fig. 1 to the equalizer of embodiment 7 and equalization methods described, the equalizer of embodiment 7 and equalization methods used the frequency pilot sign of the OFDM symbol of current (for example t3) that the OFDM symbol of current (for example t3) is carried out demodulation.

Figure 10 is the block diagram of structure of the equalizer of expression embodiment 7.The equalizer of embodiment 7 comprises channel and infers portion 200, balancing operational portion 210, RAM1000 and switch 1010,1020, herein, omit to the explanation of previous embodiment same structure.

RAM1000 equally infers portion 200 with channel and is connected, makes the transfer path of inferring generation in the portion 200 at channel infer time that result's delay is equivalent to 1 symbol line output of going forward side by side.

Switch 1010 is inferred portion 200, RAM1000 and balancing operational portion 210 with channel and is connected.Switch 1010 is supplied with any one party that transfer path is inferred the result or the transfer path after the delay is inferred the result in RAM1000 of inferring generation in the portion 200 at channel based on indication intermittently used discontinuous operation control signal to balancing operational portion 210.

Switch 1020 is inferred portion 200 with channel and is connected, and stops to infer portion 200 to channel based on the discontinuous operation control signal and supplies with clock signal clk.That is, when discontinuous operation, do not infer portion 200 and supply with clock signal clk, work is stopped to channel.

As mentioned above, according to equalizer and the equalization methods of embodiment 7, play the effect of equalizer and the equalization methods of embodiment 1.

In addition, the transfer path characteristic does not have conversion or changes when very little, and is little because transfer path is inferred change in information, so, even generate not according to each OFDM symbol that transfer path is inferred information but generate by a plurality of OFDM symbols, receiving feature can not produce bigger poor yet.In this case,, generate transfer path not according to each OFDM symbol and infer information, and the transfer path information of inferring of the generation of being to use is over carried out equilibrium treatment according to equalizer and the equalization methods of embodiment 7.Therefore,, be used in and obtain transfer path and infer the channel portion of inferring of information and stop, can reducing making the required power consumption of the channel portion of inferring work according to equalizer and the equalization methods of embodiment 7.

Embodiment 8

Then, use accompanying drawing that equalizer and the equalization methods of embodiment 8 are described.Herein, when the notion of using Fig. 1 to the equalizer of embodiment 8 and equalization methods described, the equalizer of embodiment 8 and equalization methods used the frequency pilot sign of OFDM symbol of the 1st symbol in front (for example t2) of current (for example t3) that the OFDM symbol of the 1st symbol in front is carried out demodulation.

Figure 11 is the block diagram of structure of the equalizer of expression embodiment 8.The equalizer of embodiment 8 comprises that channel infers portion 1100,210,1 symbol delay circuit 600 of balancing operational portion, RAM1000 and switch 1010,1020.Herein, omit to the explanation of previous embodiment same structure.

Channel is inferred portion 1100 and is comprised that frequency pilot sign extracts circuit 201, inverse discrete Fourier transformer inverse- discrete circuit 202,1 symbol delay circuit 1101, threshold value comparison circuit 203, adjunct circuit 204 and fast Fourier transform circuit 205.

1 symbol delay circuit 1101 comprises RAM, makes the time that postpones to be equivalent to 1 symbol from the complex gain amount of inverse discrete Fourier transformer inverse-discrete circuit 202 outputs, the complex gain amount after the output delay.

As mentioned above, according to equalizer and the equalization methods of embodiment 8, play the equalizer of embodiment 1 and embodiment 7 and the effect of equalization methods.

Embodiment 9

Then, use accompanying drawing that equalizer and the equalization methods of embodiment 9 are described.Herein, when the notion of using Fig. 1 to the equalizer of embodiment 9 and equalization methods describes, identical with equalizer and the equalization methods of embodiment 5, the equalizer of embodiment 9 and equalization methods use the frequency pilot sign of the OFDM symbol of the frequency pilot sign of OFDM symbol of current (for example t3) and the 2nd symbol in front (for example t1), and the OFDM symbol of the 1st symbol in front (for example t2) is carried out demodulation.

Figure 12 is the block diagram of structure of the equalizer of expression embodiment 9.The equalizer of embodiment 9 comprises 1 symbol delay circuit 600, channel and infers portion 610, RAM1000, switch 1010,1020 and balancing operational portion 210.Herein, omit to the explanation of previous embodiment same structure.

Channel is inferred portion 1100 and is divided into first area 1200 and second area 1210.First area 1200 comprises: frequency pilot sign extracts circuit 201, inverse discrete Fourier transformer inverse-discrete circuit 202 and 2 symbol delay circuit 611, and second area 1210 comprises: add circuit 612, threshold value comparison circuit 203, adjunct circuit 204 and fast Fourier transform circuit 205.Any one zone all is provided clock signal clk, and still, the clock signal clk that offers second area 1210 provides by the switch 1020 by the control of discontinuous operation control signal.That is, second area 1210 is not provided clock signal clk when discontinuous operation.

As mentioned above, according to equalizer and the equalization methods of embodiment 9, play the equalizer of embodiment 1 and embodiment 4 and the effect of equalization methods.

And then, equalizer and equalization methods according to embodiment 9, the work of first area is stopped, the work of second area is stopped, thus, even after the work that makes second area has just restarted, also can generate the transfer path presumed value of using the frequency pilot sign that comprises in the 2nd OFDM symbol in front and the current OFDM symbol.

Embodiment 10

Then, use accompanying drawing that equalizer and the equalization methods of embodiment 10 are described.Herein, when the notion of using Fig. 1 to the equalizer of embodiment 10 and equalization methods describes, identical with equalizer and the equalization methods of embodiment 6, the equalizer of embodiment 10 and equalization methods use the frequency pilot sign of the OFDM symbol of the frequency pilot sign of OFDM symbol of current (for example t3) and the 2nd symbol in front (for example t1), and the OFDM symbol of 1 symbol of the front mat woven of fine bamboo strips (for example t2) is carried out demodulation.

Figure 13 is the block diagram of structure of the equalizer of expression embodiment 10.The equalizer of embodiment 10 comprises 1 symbol delay circuit 600, channel and infers portion 900, RAM1000, switch 1010,1020 and balancing operational portion 210.Herein, omit to the explanation of previous embodiment same structure.

Channel is inferred portion 900 and is divided into first area 1300 and second area 1310.First area 1300 comprises: frequency pilot sign extracts circuit 201,920,2 symbol delay circuit 930 of 910,1 symbol delay circuit of inverse discrete Fourier transformer inverse-discrete circuit and 3 symbol delay circuit 940, and second area 1310 comprises: add circuit 950, threshold value comparison circuit 203, adjunct circuit 204 and fast Fourier transform circuit 205.Any one zone all is provided clock signal clk, and still, the clock signal clk that offers second area 1310 provides by the switch 1020 by the control of discontinuous operation control signal.That is, second area 1310 is not provided clock signal clk when discontinuous operation.

As mentioned above, according to equalizer and the equalization methods of embodiment 10, play the equalizer of embodiment 1, embodiment 6 and embodiment 9 and the effect of equalization methods.

Embodiment 11

Then, use accompanying drawing that equalizer and the equalization methods of embodiment 11 are described.Herein, when the notion of using Fig. 1 to the equalizer of embodiment 11 and equalization methods describes, identical with equalizer and the equalization methods of embodiment 6, the equalizer of embodiment 11 and equalization methods use the frequency pilot sign of the OFDM symbol of the frequency pilot sign of OFDM symbol of current (for example t3) and the 2nd symbol in front (for example t1), and the OFDM symbol of the 1st symbol in front (for example t2) is carried out demodulation.

Figure 14 is the block diagram of structure of the equalizer of expression embodiment 11.The equalizer of embodiment 11 comprises that 1 symbol delay circuit 600, channel infers portion 1400 and balancing operational portion 210.Herein, omit to the explanation of previous embodiment same structure.

Channel is inferred portion 1400 and comprised: frequency pilot sign extracts circuit 201, frequency pilot sign memory circuit 1410, inverse discrete Fourier transformer inverse-discrete circuit 202, threshold value comparison circuit 203, adjunct circuit 204 and fast Fourier transform circuit 205.

Frequency pilot sign memory circuit 1410 comprises RAM, frequency pilot sign, the frequency pilot sign that extracts from the OFDM symbol of the 1st symbol in front, frequency pilot sign that extracts from the OFDM symbol of the 2nd symbol in front that storage is extracted from current OFDM symbol and the frequency pilot sign that extracts from the OFDM symbol of the 3rd symbol in front.And, the frequency pilot sign that frequency pilot sign memory circuit 1410 is stored by control signal (not shown) output.At this moment, the frequency pilot sign of frequency pilot sign memory circuit 1410 exportable 1 symbolic component still, also can make up a plurality of symbolic components and export.

As mentioned above, according to equalizer and the equalization methods of embodiment 11, play the equalizer of embodiment 1 and embodiment 6 and the effect of equalization methods.

Embodiment 12

Then, use accompanying drawing that equalizer and the equalization methods of embodiment 12 are described.Herein, when the notion of using Fig. 1 to the equalizer of embodiment 12 and equalization methods describes, identical with equalizer and the equalization methods of embodiment 11, the equalizer of embodiment 12 and equalization methods use the frequency pilot sign of the OFDM symbol of the frequency pilot sign of OFDM symbol of current (for example t3) and the 2nd symbol in front (for example t1), and the OFDM symbol of the 1st symbol in front (for example t2) is carried out demodulation.

Figure 15 is the block diagram of structure of the equalizer of expression embodiment 12.The equalizer of embodiment 12 comprises that 1 symbol delay circuit 600, channel infers portion 1400, RAM1000, switch 1010,1020 and balancing operational portion 210.Herein, omit to the explanation of previous embodiment same structure.

According to equalizer and the equalization methods of embodiment 12, play the equalizer of embodiment 1, embodiment 6, embodiment 7 and embodiment 11 and the effect of equalization methods.

Embodiment 13

Then, use accompanying drawing that equalizer and the equalization methods of embodiment 13 are described.Herein, when using Fig. 1 that the notion of the equalizer of embodiment 13 and equalization methods is described, identical with equalizer and the equalization methods of embodiment 11, the equalizer of embodiment 13 and equalization methods use the frequency pilot sign of the OFDM symbol of the frequency pilot sign of OFDM symbol of current (for example t3) and the 2nd symbol in front (for example t1), and the OFDM symbol of the 1st symbol in front (for example t2) is carried out demodulation.In addition, use the frequency pilot sign of the OFDM symbol of the frequency pilot sign of OFDM symbol of the 2nd symbol in frequency pilot sign, front (for example t3) of OFDM symbol of the 1st symbol in frequency pilot sign, front (for example t4) of the OFDM symbol of current (for example t5) and the 3rd symbol in front (for example t2), the OFDM symbol of the 1st symbol in front (for example t4) is carried out demodulation.

Figure 16 is the block diagram of structure of the equalizer of expression embodiment 13.The equalizer of embodiment 13 comprises that 1 symbol delay circuit 600, channel infers portion 1400, RAM1000, switch 1010,1020 and balancing operational portion 210.Herein, omit to the explanation of previous embodiment same structure.

Channel is inferred portion 1400 and is divided into first area 1600 and second area 1610.First area 1600 comprises: frequency pilot sign extracts circuit 201 and frequency pilot sign memory circuit 1410, and second area 1610 comprises: inverse discrete Fourier transformer inverse-discrete circuit 202, threshold value comparison circuit 203, adjunct circuit 204 and fast Fourier transform circuit 205.Any one zone all is provided clock signal clk, and still, the clock signal clk that offers second area 1610 provides by the switch 1020 by the control of discontinuous operation control signal.That is, second area 1610 is not provided clock signal clk when discontinuous operation.

As mentioned above, according to equalizer and the equalization methods of embodiment 13, play equalizer and the same effect of equalization methods with embodiment 12.

And then, according to equalizer and the equalization methods of embodiment 13, the arithmetic processing circuit (inverse discrete Fourier transformer inverse-discrete circuit 202 and fast Fourier transform circuit 205) that needs power consumption is concentrated in the zone of being controlled by identical clock signal.Therefore,, need the maximum circuit of power consumption to stop, can further reducing power consumption more by making according to equalizer and the equalization methods of embodiment 13.

In addition,, during making that second area 1610 stops, making first area 1600 work, can continue to extract and the storage frequency pilot sign according to equalizer and the equalization methods of embodiment 13.Therefore,, when discontinuous operation finishes, after the circuit of second area 1610 has just been started working, just can carry out operate as normal, can handle to received signal apace according to equalizer and the equalization methods of embodiment 13.

Claims (19)

1. equalizer is characterized in that possessing:

First extracts circuit, extracts a plurality of frequency pilot signs from input signal;

The inverse fourier transform circuit carries out inverse fourier transform to a plurality of frequency pilot signs of described extraction, calculates the complex gain amount in each path;

Second extracts circuit, uses described complex gain amount, extracts a plurality of paths;

Fourier transform circuit carries out Fourier transform to the path of described extraction; And

The balancing operational circuit extracts the phase component in the path behind the described Fourier transform, uses the phase component of described extraction that described input signal is carried out equilibrium.

2. as the equalizer of claim 1 record, it is characterized in that described inverse fourier transform circuit carries out inverse discrete Fourier transformer inverse-discrete or invert fast fourier transformation.

3. as the equalizer of claim 1 record, it is characterized in that described second extracts circuit comprises:

The threshold value comparison circuit is obtained quantity of power maximum in the quantity of power in described each path, and whether the quantity of power of judging described each path is in the predetermined power amount that begins from described maximum amount of power; And

Adjunct circuit, the zero laggard line output of the output of described threshold value comparison circuit being added predetermined number.

4. as the equalizer of claim 1 record, it is characterized in that described second extracts circuit comprises:

The threshold value comparison circuit is obtained the maximum in the value after absolute value to the real number of the complex gain amount in described each path and imaginary number carries out add operation, and whether the absolute value of judging described each path is in the preset range that begins from described maximum; And

Adjunct circuit, the zero laggard line output of the output of described threshold value comparison circuit being added predetermined number.

5. as the equalizer of claim 1 record, it is characterized in that the phase component and the amplitude in the path behind the described Fourier transform of described balancing operational circuit extraction use the phase component of described extraction and amplitude and described input signal to carry out multiplying.

6. as the equalizer of claim 1 record, it is characterized in that possessing:

1 symbol delay circuit makes described input signal postpone 1 symbol;

Memory circuit is temporarily stored the described path behind the described Fourier transform;

First switching circuit according to control signal, is exported any one party in the described path of described path behind the described Fourier transform or storage; And

The second switch circuit, according to described control signal, whether decision provides clock signal to described Fourier transform circuit.

7. equalizer is characterized in that possessing:

1 symbol delay circuit makes described input signal postpone 1 symbol;

First extracts circuit, extracts a plurality of frequency pilot signs from input signal;

The inverse fourier transform circuit carries out inverse fourier transform to a plurality of frequency pilot signs of described extraction, calculates the complex gain amount in each path;

2 symbol delay circuit make described complex gain amount postpone 2 symbols;

Add circuit carries out add operation to the complex gain amount behind described complex gain amount and 2 symbols of described delay;

Second extracts circuit, uses the described complex gain amount after the described add operation, extracts a plurality of paths;

Fourier transform circuit carries out Fourier transform to the path of described extraction; And

The balancing operational circuit extracts the phase component in the path behind the described Fourier transform, uses the phase component of described extraction, and the described input signal behind 1 symbol of described delay is carried out equilibrium.

8. as the equalizer of claim 7 record, it is characterized in that possessing:

Memory circuit is temporarily stored the described path behind the described Fourier transform;

First switching circuit according to control signal, is exported any one party in the described path of described path behind the described Fourier transform or storage; And

The second switch circuit, according to described control signal, whether decision provides clock signal to described Fourier transform circuit.

9. equalizer is characterized in that possessing:

1 symbol delay circuit makes described input signal postpone 1 symbol;

First extracts circuit, extracts a plurality of frequency pilot signs from input signal;

2 symbol delay circuit make the described frequency pilot sign of described extraction postpone 2 symbols;

Arrange circuit, the described frequency pilot sign of described extraction and the described frequency pilot sign after the described delay are synthesized, the frequency pilot sign after output is synthetic;

The inverse fourier transform circuit carries out inverse fourier transform to the described frequency pilot sign after described synthesizing, and calculates the complex gain amount in each path;

Second extracts circuit, uses described complex gain amount, extracts a plurality of paths;

Fourier transform circuit carries out Fourier transform to the path of described extraction; And

The balancing operational circuit extracts the phase component in the path behind the described Fourier transform, uses the phase component of described extraction, and the described input signal behind 1 symbol of described delay is carried out equilibrium.

10. equalizer is characterized in that possessing:

The one 1 symbol delay circuit makes described input signal postpone 1 symbol;

First extracts circuit, extracts a plurality of frequency pilot signs from input signal;

The inverse fourier transform circuit carries out inverse fourier transform to a plurality of frequency pilot signs of described extraction, calculates the complex gain amount in each path;

The 21 symbol delay circuit makes described complex gain amount postpone 1 symbol;

2 symbol delay circuit make described complex gain amount postpone 2 symbols;

3 symbol delay circuit make described complex gain amount postpone 3 symbols;

Add circuit carries out add operation to complex gain amount behind 2 symbols of complex gain amount, described delay behind described complex gain amount, 1 symbol of described delay and the complex gain amount behind 3 symbols of described delay;

Second extracts circuit, uses the described complex gain amount after the described add operation, extracts a plurality of paths;

Fourier transform circuit carries out Fourier transform to the path of described extraction; And

The balancing operational circuit extracts the phase component in the path behind the described Fourier transform, uses the phase component of described extraction, and the described input signal behind 1 symbol of described delay is carried out equilibrium.

11. the equalizer as claim 10 record is characterized in that possessing:

Memory circuit is temporarily stored the described path behind the described Fourier transform;

First switching circuit according to control signal, is exported any one party in the described path of described path behind the described Fourier transform or storage; And

The second switch circuit, according to described control signal, whether decision provides clock signal to described Fourier transform circuit.

12. an equalizer is characterized in that possessing:

The one 1 symbol delay circuit makes described input signal postpone 1 symbol;

First extracts circuit, extracts a plurality of frequency pilot signs from input signal;

The inverse fourier transform circuit carries out inverse fourier transform to a plurality of frequency pilot signs of described extraction, calculates the complex gain amount in each path;

The 21 symbol delay circuit makes described complex gain amount postpone 1 symbol;

Second extracts circuit, uses the described complex gain amount after the described delay to extract a plurality of paths;

Fourier transform circuit carries out Fourier transform to the path of described extraction;

Memory circuit is temporarily stored the described path behind the described Fourier transform;

First switching circuit according to control signal, is exported any one party in the described path of described path behind the described Fourier transform or storage;

The second switch circuit, according to described control signal, whether decision provides clock signal to described Fourier transform circuit; And

The balancing operational circuit extracts the phase component in the described path of described selection, uses the phase component of described extraction, and the described input signal behind 1 symbol of described delay is carried out equilibrium.

13. an equalizer is characterized in that possessing:

The one 1 symbol delay circuit makes described input signal postpone 1 symbol;

First extracts circuit, extracts a plurality of frequency pilot signs from input signal;

First memory circuit is a plurality of frequency pilot signs that unit stores described extraction with each symbol;

The inverse fourier transform circuit carries out inverse fourier transform to a plurality of frequency pilot signs of described storage, calculates the complex gain amount in each path;

The 21 symbol delay circuit makes described complex gain amount postpone 1 symbol;

Second extracts circuit, uses the described complex gain amount after the described delay, extracts a plurality of paths;

Fourier transform circuit carries out Fourier transform to the path of described extraction; And

The balancing operational circuit extracts the phase component in described path, uses the phase component of described extraction, and the described input signal behind 1 symbol of described delay is carried out equilibrium.

14. the equalizer as claim 13 record is characterized in that possessing:

Second memory circuit is temporarily stored the described path behind the described Fourier transform;

First switching circuit according to control signal, is exported any one party in the described path of described path behind the described Fourier transform or storage; And

The second switch circuit, according to described control signal, whether decision provides clock signal to described Fourier transform circuit.

15. an equalization methods is characterized in that,

From input signal, extract a plurality of frequency pilot signs,

A plurality of frequency pilot signs to described extraction carry out inverse fourier transform, calculate the complex gain amount in each path,

Use described complex gain amount, extract a plurality of paths,

Fourier transform is carried out in path to described extraction,

Extract the phase component in the path behind the described Fourier transform,

Use the phase component of described extraction that described input signal is carried out equilibrium.

16. the equalization methods as claim 15 record is characterized in that described inverse fourier transform is an inverse discrete Fourier transformer inverse-discrete.

17. equalization methods as claim 15 record, it is characterized in that, obtain quantity of power maximum in the quantity of power in described each path, select to have the predetermined power amount that begins from described maximum amount of power path with interior quantity of power, thus, extract described a plurality of path.

18. equalization methods as claim 15 record, it is characterized in that, obtain the maximum in the value after absolute value to the real number of the complex gain amount in described each path and imaginary number carries out add operation, select the path of absolute value in the preset range that begins from described maximum in described each path, thus, extract described a plurality of path.

19. the equalization methods as claim 15 record is characterized in that, extracts the amplitude in the path behind the described Fourier transform, uses described phase component and the described amplitude and the described input signal of described extraction, carries out described multiplying.

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