CN1937435A - Digital signal processing method for power line communication system - Google Patents

Abstract

This method transfers data at hi-speed on the power line. It is a wideband hi-speed power carrier comm. method base on the orthogonal frequency division multiplexing (OFDM) technique. It consists of an emitting terminal and a receiving terminal, and uses the power line to realize research and development of key technique of wideband hi-speed power carrier comm. system. Its comm. rate is or is greater then 50 Kbps, and the direct comm. distance is or is greater then 100 meter. The invention realizes to connect the system into Internet and prepares for designing a power line carrier comm. system with a comm. rate of 1 to 10 Mbps.

Description

The digital signal processing method of electric line communication system

Technical field

The present invention is a kind of method that is used at power line high speed transmission of data signals, and especially a kind of method of the broadband high-speed power line carrier, PLC based on OFDM (OFDM) belongs to the technical field of wire communication.

Background technology

Present communication mode has wireless channel communication to communicate by letter with wire message way, power line communication (Power LineCommunication) technology refers to and is based upon on the power delivery networks basis, realize between each node of power line communication network inside and with the system of other communication.Its history can be traced back to the twenties in 20th century, power line communication technology mainly utilizes the above high pressure of 11kV to carry out remote message transmission at that time, operating frequency is below the 150kHz, and this frequency range became the formal frequency range of European power technology standardization committee power line communication afterwards.Upward (9～490kHz) to transmit remote data or speech than low rate, be one of principal mode of power line communication technology application with low frequency by power line carrier at mesohigh power transmission network (more than the 35kV).In low pressure (220V) field, the PLC technology begins its transmission rate and is generally 1200b/s or lower, is called low speed PLC.The power line communication technology of low-voltage power line transmission rate more than 1Mb/s of carrying out both at home and abroad in recent years that utilize is referred to as high speed PLC.The PLC technology at first is used to load control, remote meter reading and household automation.

The PLC technology has its significant advantage with power line as local area network bus: cost is low, easy construction, a line are dual-purpose, cheap, and it is convenient to extend.Power line can reach in family, company and various place everywhere, and is more more extensive than cable and fixed telephone network.The greatest problem that exists is that power line network is to be designed to transmit electricity, but not is used for transmitting data.Therefore, power line is an insecure transmission channel, and very big noise and decay are arranged.Because the development of modern digital communication, the introducing of various advanced persons' modulation-demodulation technique (as OFDM) and Modern DSP technology make power line carrier communication become possibility.

In recent years, very active for the research of power line communication and Internet interconnection technique both at home and abroad.From the Norweb communication company of subsidiary of Britain United Power Company since nineteen ninety begins power line carrier communication studied, the research institution of many countries has carried out high speed power line Study on Technology and exploitation, Electric Power Research Institute as China, the Intellon of the U.S., Hispanic DS2 company etc., the transmission rate of product also develops into 45Mb/s from 1Mb/s, and high speed PLC has reached 200Mb/s at present.

Along with the develop rapidly of Internet technology, the number of logon is doubled and redoubled.Yet, adopt which kind of communication mode to make user terminal be connected to nearest broadband network connection device, becoming one of difficult point of long-term puzzlement people, also is one of universal bottleneck of Internet, is called " last l mile " problem that broadband network inserts by the insider.Utilization extend in all direction, spread all over town and country, through user 220V low-voltage power line transmitting high speed data the PLC technology with its need not wiring, wide coverage, distinguishing feature easy to connect, thought to provide one of the most competitive technology of " last 300m " solution by the insider.

High speed PLC can transmit the data up to 45Mb/s, and can transmit data, voice, video and electric power simultaneously, might bring the new trend of " four networks one platform ".

Different according to the configuring condition of local electrical network and various Internet access technology marketization degree, current high speed PLC technology mainly contains two kinds of development models:

One is for being the home networking pattern of representative with the U.S..The PLC of this pattern only provides family internal network, and other traditional communication mode is used in outdoor visit.This is because technology such as U.S. ADSL, HFC and product comparative maturity and popularizing on the one hand, the more important thing is because the low voltage distribution transformer of the U.S. is generally single-phase, average only for 5～6 users provide the power supply service, promote the too high cause of high speed PLC access technology cost.

Another kind of pattern is towards Europe and Asia-Pacific market.Because these regional low-voltage distribution web frame comparing class are seemingly, be generally 200～300 users the power supply service is provided, it is lower to promote high speed PLC access service average unit cost.This application model provides from distribution transformer or limit, building to comprehensive PLC solution of subscriber household.Because exterior product is with the environment for use difference of indoor product, the technical difficulty that implements is bigger, and therefore company's negligible amounts of this kind scheme can be provided, and mainly contains Spain DS2 company, Switzerland Ascom company, Israel Main.Net company etc.Experimental Network is had in countries and regions such as the Korea S in Spain, Germany, Austria, France and the Asia in Europe, Singapore, Hong Kong in these several companies.

The international organization of power line high-speed communication mainly contains the ECHONET of the HPA of plug-in alliance of family (HomePlug PowerlineAlliance), the PLC Forum of power line communication forum, PALAS (Powerline as an AlternativeLocal AccesS) and Japan.

The plug-in alliance of family that is made up of 13 companies such as Cisco, Intel, Hewlett-Packard, Panasonic and Sharp is found in April, 2000, is devoted to create common homeplug powerline network communications technology standard.HPA has developed into the enterprise group that is made up of 90 companies at present, and selects the prototype of the technology of American I ntellon company as uniform technical standards for use.In June calendar year 2001, HPA has issued the 1st version Home-PlugSpecfication 1.0 of its standard, and message transmission rate is decided to be 14Mb/s, adopts the OFDM modulation-demodulation technique, and mac-layer protocol is CSMA/CA.This standard setting inserts shorter mention in the household internal network application to outdoor high speed power line.

Be exactly under so domestic and international background, the staff of this seminar to OFDM the application in low voltage electric power carrier communication carried out studying experimentally, and under test and situation, determined the implementation method of the DSP in the ofdm system with reference to some power line channel data.The content of this patent is integrated the achievement in research that the personnel of seminar have now reached and applied for: based on the implementation method of the DSP of the electric line communication system of OFDM.

The application of OFDM technology in power line communication progressively obtained domestic and international colleague's approval, develops and released 10Mbps even higher communication module abroad.Because domestic its core technology of not grasping, therefore, the power line carrier, PLC Core Technology Research of actively developing China is very important.

This invention target is to promote the development of China's low-voltage powerline carrier communication core technology, and for the appointment of China's power line communication standard provides decision-making foundation, the electric line communication system that adapts to China's electrical network present situation for development provides key technology and product.

Summary of the invention

Technical problem: the purpose of this invention is to provide a kind of digital signal processing method of the electric line communication system based on OFDM, this method traffic rate 〉=50Kbps; 〉=100 meters of direct communication distances; And the access of the Internet of the system of realization; For the power-line carrier communication system that next step design of communications speed is 1-10Mbps is carried out basic work.

Technical scheme: method of the present invention adopts OFDM (OFDM) technology, utilizes power line to realize the research and development of the key technology of broadband high-speed power carrier communication system (based on the realization of the DSP of the electric line communication system of OFDM).

This digital signal processing method divides transmitting terminal and receiving terminal two parts, and the step of its processing method is: transmitting terminal:

1) host computer produces data flow, and the requirement according to data segment part in the frame format of system simultaneously sends.

2) DSP of long-pending sign indicating number realizes: convolution code is that the information sequence that will send passes through a linearity, the shift register of finite state and the coding that produces, usually the encoder of convolution code is by the K level, the shift register of every grade of k bit and n linear algebra function generator-modulo 2 adder formed, need encoded binary data serial input shift register, each k Bit data that moves into, the output sequence of the corresponding n bit of the list entries of each k bit, in channel coding schemes, select K=7 the most frequently used in engineering for use, k=1, and n=2R _c=1/2 convolution code, the Viterbi algorithm is adopted in decoding, gets δ=40＞5K, hard decision, the generator polynomial of (7,1,2) convolution code is expressed as with octal number: POLYA=133, POLYB=171.

Initial condition all was 0 state when 3) general convolution code had just begun to encode, and the afterbody of bit stream can be with filling out 0 " Flushing " when coding soon finishes, to allow encoding state revert to 0, so the information sequence afterbody must be artificially with the data 000000 that add 6bit, to force encoder to get back to 0 state, make to recall for the last time when deciphering to obtain correct decode results at the afterbody of frame data.

4) interweave: the mode that interweaves has two kinds of block interleaving and convolutional interleaves, select block interleaving in the system for use, the process of block interleaving is: the data after m rank interleaver will be encoded are lined up the array format that the capable n of m is listed as by the direction of row, by the direction that is listed as sense data successively, finish interweaving of data then.

5) 16QAM mapping: use the 16QAM modulation in the multi-system modulation, planisphere adopts the square planisphere, and relevant parameter is: minimum phase skew θ _Min=18 °, minimum Eustachian distance $d_{\min }=0.63\sqrt{E_0},$ Peak to average is γ=1.8, E ₀Be average power.

6) virtual carrier and conjugation expansion: being added among the DSP of virtual carrier finished by a carrier wave mapping graph, the data of carrier wave mapping graph include only 0 and 1, the frequency band of OFDM is divided into several subcarriers, several 0 and 1 data are just arranged in the carrier wave mapping graph, the corresponding subcarrier of 0 expression is not used for transmitting data, and the corresponding subcarrier of 1 expression is used for transmitting data; Used 256 subcarriers in ofdm system altogether, wherein 128 is virtual carrier, and 112 of front and 16 of back are virtual carriers, and 128 subcarriers in the middle of having only are used for transmitting data Carrier wave mapping graph rule, the utilization Fourier transform, result after the real signal Fourier transform is that amplitude spectrum is even symmetry, phase spectrum is odd symmetry, and OFDM realizes that with IFFT modulation just is converted to time-domain signal to frequency-region signal, is arranged to even symmetry with the amplitude spectrum of frequency-region signal, phase spectrum is arranged to odd symmetry, then the time-domain signal that comes out of conversion must be real signal, can just can lean on single channel D/A send data through carrier modulation, and can not change the frequency spectrum of signal; If OFDM adopts the mode on I, Q road, must add that then carrier modulation could send data, the conjugation expansion is exactly consciously frequency domain to be mended to meeting the frequency domain of real signal characteristics.

7) virtual carrier and conjugation are expanded coefficient result and be: ofdm system sends signal with single channel, is W if send the baseband frequency spectrum width of signal, and then the frequency spectrum that actual transmission signal takies under the effect of virtual carrier is The realization of virtual carrier and conjugation expansion is all made amendment or is resequenced and realize memory content among the DSP.

8) realization of IFFT in DSP: in IFFT, adopted the IFFT algorithm of TI, reduced the number of times of complex multiplication, in fixed-point DSP chip, used one the method for moving to right and finish the computing of 1/N, and prevent overflowing in the calculating process based on base 4 and base 2.

9) the D/A data are adjusted: before carrying out packing data, initial data is converted to the data that are fit to the D/A transmission.

Receiving terminal:

10) signal via channel be transmitted in receiving terminal at first by coupler, carry out carrier wave then and move, this be with transmitting terminal corresponding one with the signal downconversion process.

11) after signal is finished down-conversion, sampling becomes digital signal with analog signal through A/D.

12) synchronization module: be divided into for four steps synchronously, symbol is slightly synchronous, decimal Frequency Estimation and correction, integer frequency estimation and correction and fine synchronization; Whole this synchronizing process needs the better controlled clock, in the estimation of finishing the above laggard line phase of synchronizing process and correction and optimum sampling point differentiation; After finishing synchronously, the frame of signal is handled, abandoned Cyclic Prefix and synchronous head in the signal frame, directly give the processing unit of back the data segment in the Frame.

13) adopt the synchronous method of module, i.e. sampling come in after the data of some DSP just the triggering synchronous module carry out synchronously, per 128 point data trigger a synchronization module, have so just reduced and have preserved instruction on-the-spot and that the context switching is consumed, have improved the efficient of program running.

14) synchronously thick: at receiving terminal, when receiver finds that the output valve of M (n) keeps greater than certain thresholding in a period of time, think that then frame head is correctly caught, we selected DSP of the processing of precision aspect is a C54X series, is the fixed DSP of 16bit.

15) synchronously thin: because the frame head that the frame head acquisition algorithm obtains location only falls into the region of no relief of frame head correlation function, therefore there is certain ambiguity the frame head position, the meticulous timing of adopting is based on the thought of closing fine synchronization among the IEEE 802.11a with two-phase, promptly allow receiving sequence and local reference sequences make multiple correlation, just can obtain outstanding and sharp-pointed relevant peaks, detect the pseudo-frame head that whether has periodic noise to produce and catch, thereby improve synchronous accuracy.

16) memory space and precision are handled: the thin DSP memory module that when carrying out computing, needs 2 128 bytes synchronously, adding 1 A/D data writing module needs 3 memory modules altogether, aspect the precision processing and thick be the same synchronously.

17) the FFT module realizes: FFT is used in receiving terminal, because the data that receiving terminal receives all are real numbers, carries out computing so adopted certain method to make real number FFT become plural FFT, has saved the original closely amount of calculation of half, finishes in the lump and understands the conjugation expansion.

18) go expansion, the carrier wave inverse mapping is a baseband signal with the frequency spectrum down-frequency conversion.

19) data are counter adjusts, anti-16QAM mapping, and reciprocal cross is knitted, and at receiving terminal, the data of anti-interleaver after with demodulation are lined up the array format of the capable n row of m by the direction of row, by the direction of row sense data successively, finish the reciprocal cross of data and knit then.

20) realization of Viterbi decoding: butterfly type figure is the core that the Viterbi algorithm is realized, the processing of butterfly type figure has determined the efficient of Viterbi algorithm, realizes Viterbi in DSP, utilizes the method that produces fast table to improve the speed of Branch Computed tolerance; Utilize the function of C54X DSP cyclic addressing, make Metrix and Transition_matrix all be limited in the Circular Buffer the inside of 128 bytes, the saving of maximum possible and utilized memory, utilized the hardware supports of DSP, such as two 16 bit arithmetic abilities of accumulator to the Viterbi algorithm; Special is comparison, selection and the memory cell of Viterbi algorithm design, uses these special hardware supports to quicken the speed of decoding.

21) after decoding is finished, receive data with regard to the communication serial port that utilizes receiving terminal.

Beneficial effect: the present invention is based on the realization of DSP of the electric line communication system of OFDM, adopts OFDM (OFDM) technology, utilizes power line to realize the research and development of the key technology of broadband high-speed power carrier communication system.The application of OFDM technology in power line communication progressively obtained domestic and international colleague's approval, develops and released 10Mbps even higher communication module abroad.Because domestic its core technology of not grasping, therefore, the power line carrier, PLC Core Technology Research of actively developing China is very important.

This invention target is to promote the development of China's low-voltage powerline carrier communication core technology, and for the appointment of power line communication standard provides decision-making foundation, the electric line communication system that adapts to China's electrical network present situation for development provides key technology and product.

Designed the hardware circuit that DSP realizes;

On the DSP platform, realized ofdm communication system (comprising modules such as FFT/IFFT, QAM mapping, convolutional encoding, Viterbi decoding) with software algorithm;

Successfully realized the transfer of data of 50kbps;

Because the restriction of dsp chip disposal ability, the synchronized algorithm of employing be simple (later stage can be perfect) relatively.

The present invention has carried out work perfect to ofdm system and that realize on the basis of previous work personnel research.The hardware designs aspect has been finished the ofdm system based on DSP together, for the transmission and the receiving terminal of ofdm system provides stable DSP platform.The software design aspect, the accurate RTOS (DSP/BIOS) that has adopted TI just to release has in recent years used the design philosophy based on multithreading, has successfully designed the software of OFDM transmitting terminal and receiving terminal, has stepped the step with meaning for practicability.

Description of drawings

Fig. 1 is that system of the present invention realizes block diagram,

Fig. 2 is the schematic diagram that interweaves of the present invention,

Fig. 3 is synchronous realization flow figure of the present invention,

Fig. 4 is the flow chart of power communication system of the present invention,

Fig. 5 is a Viterbi decoding flow chart of the present invention,

Fig. 6 is K=7, k=1, and n=2 (R _c=1/2) convolution coding mode figure,

Fig. 7 is that decimal frequency bias is estimated and the flow chart of correcting,

Fig. 8 is that integer frequency bias is estimated and the flow chart of correcting,

Fig. 9 is meticulous frame synchronization process flow chart,

Figure 10 is that optimum sampling point is differentiated flow chart.

Embodiment

Scheme Design

OFDM basic parameter design: bandwidth B=200kHz

Use frequency range DSP implementation: 200～400kHz

Number of subchannels N=128

Cyclic prefix CP=32

The subchannel mapped mode is selected: the 16QAM:4bit/ subchannel

The DQPSK:2bit/ subchannel

Transmission means realizes: the DSP scheme: the expansion of base band conjugation

About communication distance 100m ~ 1000m

The error rate is controlled at about 10e-7 ~ 10e-9

Baud Length

T＝N×1/B＝640us

Guard time at interval

Δ＝160us

Subchannel at interval

Δf＝1/T＝1.5625kHz

Actual transmitted symbol length

T _s＝T+Δ＝800us

Actual symbol rate

f _s＝1/T _s＝1/800us＝1.25kbaud

Total bit rate: DSP:

1.25kbaud×128×4bit/symbol＝640kps

The required main devices of project: DSP:TMS320C5416

SRAM：IS61LV25616

FLASH：SST39VF400

CPLD：EPM7128

A/D：AD7492AR

D/A：AD9762AR

The theoretical research of system and emulation:

Under the Matlab platform, finish the emulation of systemic-function;

Under the SIMULINK platform, finish system dynamic simulation, verified the real time communication performance of system; Realize the algorithm of system with standard C; With OPNET Data Transport Protocol has been carried out emulation.

The present invention is based on the realization of DSP of the electric line communication system of OFDM, adopts OFDM (OFDM) technology, utilizes power line to realize the research and development of the key technology of broadband high-speed power carrier communication system.The application of OFDM technology in power line communication progressively obtained domestic and international colleague's approval, develops and released 10Mbps even higher communication module abroad.Because domestic its core technology of not grasping, therefore, the power line carrier, PLC Core Technology Research of actively developing China is very important.

This invention target is to promote the development of China's low-voltage powerline carrier communication core technology, and for the appointment of China's power line communication standard provides decision-making foundation, the electric line communication system that adapts to China's electrical network present situation for development provides key technology and product.

Designed the hardware circuit that DSP realizes;

On the DSP platform, realized ofdm communication system (comprising modules such as FFT/IFFT, QAM mapping, convolutional encoding, Viterbi decoding) with software algorithm;

Successfully realized the transfer of data of 50kbps;

Because the restriction of dsp chip disposal ability, the synchronized algorithm of employing be simple (later stage can be perfect) relatively.

The present invention has carried out work perfect to ofdm system and that realize on the basis of previous work personnel research.The hardware designs aspect has been finished the ofdm system based on DSP together, for the transmission and the receiving terminal of ofdm system provides stable DSP platform.The software design aspect, the accurate RTOS (DSP/BIOS) that has adopted TI just to release has in recent years used the design philosophy based on multithreading, has successfully designed the software of OFDM transmitting terminal and receiving terminal, has stepped the step with meaning for practicability.

1971, S.B.Weinstein and P.M.Ebert pointed out that the modulation of multichannel quadrature carrier can utilize DFT/IDFT to realize fast, and for the OFDM broad application has stepped solid step forward, the Cyclic Prefix among the OFDM has been eliminated ISI and ICI effectively.

The DSP platform:

After proposing with IFFT/FFT realization OFDM modulation, it is practical that the last realization of DSP OFDM just becomes.Selected the C5416 DSP in the TI C5000 series to realize in the system.

Dsp software design environment CCS:1999, TI have released dsp software Integrated Development Environment Code Composer Studio (being called for short CCS) revolutionaryly.

The DSP/BIOS:DSP/BIOS real-time kernel is the accurate RTOS that TI releases in recent years, and its purpose is to help the developer to set up the DSP application program and manage resource on the DSP sheet.

1. directly write, guaranteed the high efficiency of DSP/BIOS by assembler language;

2. support DSP programming, make the multitask embedded development become simple relatively based on thread;

3.DSP/BIOS have tailorability flexibly, on high efficiency basis, make its minimum occupy the space and only be the 1K byte;

4. the unified interface of DSP bottom hardware operation is provided for the developer, can have made the developer save a lot of problems that cause because of the difference of concrete chip model, energy has been concentrated in the realization of application.

The main realization flow of system has provided in Fig. 1, and following mask body is introduced the entire work process of system and the step of execution:

Produce data flow by host computer, send according to data segment requirement partly in the frame format of our system simultaneously.

The DSP of convolution code realizes, convolution code is the information sequence that will send by a linearity, the shift register of finite state and the coding that produces.Usually the encoder of convolution code is made up of the shift register and n the linear algebra function generator (being modulo 2 adder here) of K level (every grade of k bit), as Fig. 6.Need encoded binary data serial input shift register, move into the k Bit data at every turn.The output sequence of the corresponding n bit of the list entries of each k bit.Therefore the code efficiency of convolution code is defined as R _c=k/n.Parameter K is known as the constraint length of convolution code, and its expression has relation by current n bit output sequence and what k bit list entries, also is simultaneously the important parameter of a decision coding complexity.

In our channel coding schemes, selected K=7 the most frequently used in engineering for use, k=1, and n=2 (R _c=1/2) convolution code.The Viterbi algorithm is adopted in decoding, gets δ=40＞5K, hard decision.The generator polynomial of (7,1,2) convolution code is expressed as with octal number: POLYA=133, POLYB=171.

In fact we have carried out once interweaving with regard to being equivalent to the data behind the coding when carrying out convolutional encoding, and this problem is carried out a reciprocal cross and just knitted and can be resolved before decoding.What should be noted that a bit is: initial condition all was 0 state when general convolution code had just begun to encode, and the afterbody of bit stream can be with filling out 0 " Flushing ", to allow encoding state revert to 0 when coding soon finishes.So our information sequence afterbody must be got back to 0 state to force encoder at the afterbody of frame data artificially with the data 000000 that add 6bit, make to recall for the last time when deciphering to obtain correct decode results.

Interweave: the mode that interweaves has two kinds: block interleaving (Block Interleaving) and convolutional interleave (Convolutional Interleaving), we have selected block interleaving for use in the system.The process of block interleaving is: the data after m rank interleaver will be encoded are lined up the array format that the capable n of m is listed as by the direction of row, by the direction that is listed as sense data successively, finish interweaving of data then.(as Fig. 2 schematic diagram that interweaves), at receiving terminal, the data of deinterleaver after with demodulation are lined up the array format of the capable n row of m by the direction of row, by the direction of row sense data successively, finish the deinterleaving of data then.Interweaving in DSP just becomes the order of depositing of data once, realizes fairly simple.

The 16QAM mapping: in actual applications, we are usually with a kind of baseband signal that is called multi-system (as 4 systems, 8 systems, 16 systems etc.).Multi-system digitally modulated carrier parameter has the different value of M kind, and the multi-system digital modulation has two outstanding advantages than binary digit modulation: the one, and have and contain more information in the multi-system digital signal and make band efficiency higher; The 2nd, longer duration under identical information rate can improve the energy of code element, thereby reduces because the intersymbol interference that the characteristic of channel causes.We have used the 16QAM modulation in the multi-system modulation, and planisphere has adopted the square planisphere, and relevant parameter is: minimum phase skew θ _Min=18 °, minimum Eustachian distance $d_{\min }=0.63\sqrt{E_0},$ Peak to average is γ=1.8, E ₀Be average power.

Virtual carrier and conjugation expansion: being added among the DSP of virtual carrier finished by a carrier wave mapping graph, and the data of carrier wave mapping graph include only 0 and 1, and the frequency band of OFDM is divided into several subcarriers, and several 0 and 1 data are just arranged in the carrier wave mapping graph.The corresponding subcarrier of 0 expression is not used for transmitting data (just adding 0 handles), and the corresponding subcarrier of 1 expression is used for transmitting data.Used 256 subcarriers in our ofdm system altogether, wherein 128 is virtual carrier, and 112 of front and 16 of back are virtual carriers, and 128 subcarriers in the middle of having only are used for transmitting data.

Carrier wave mapping graph rule

The essence of conjugation expansion is the characteristic of having used Fourier transform.We know that the result after the real signal Fourier transform is that amplitude spectrum is even symmetry, and phase spectrum is odd symmetry, and this is that real signal has especially.OFDM realizes that with IFFT modulation just is converted to time-domain signal to frequency-region signal, if we are arranged to even symmetry with the amplitude spectrum of frequency-region signal wittingly, phase spectrum is arranged to odd symmetry, and then the time-domain signal that comes out of conversion must be real signal.We just can just can send data through carrier modulation by single channel D/A like this, and can not change the frequency spectrum of signal.If OFDM adopts the mode on I, Q road, must add that then carrier modulation could send data.So the conjugation expansion is exactly consciously frequency domain to be mended to meeting the frequency domain of real signal characteristics.

Virtual carrier and conjugation are expanded coefficient result: ofdm system sends signal with single channel, is W if send the baseband frequency spectrum width of signal, and then the frequency spectrum that actual transmission signal takies under the effect of virtual carrier is

The realization of virtual carrier and conjugation expansion is all made amendment or is resequenced and realize memory content among the DSP.

The realization of IFFT in DSP: in IFFT, adopted the IFFT algorithm of TI based on base 4 and base 2, the benefit of doing like this is the number of times that has reduced complex multiplication, also having good characteristics is exactly in fixed-point DSP chip, can very simply use one the method for moving to right and finish the computing of 1/N, and prevent overflowing in the calculating process.

The D/A data are adjusted: also having a job to do before carrying out packing data, is exactly that initial data is converted to the data that are fit to the D/A transmission.

Receiving terminal: signal is transmitted in receiving terminal at first by coupler via channel, carry out then carrier wave move this be with transmitting terminal corresponding one with the signal downconversion process.After signal was finished down-conversion, sampling became digital signal with analog signal through A/D.

Synchronization module: system mainly is divided into thick frame synchronization synchronously, and decimal frequency bias estimates and correct that integer frequency bias is estimated and corrected, meticulous frame synchronization, and optimum sampling point is differentiated, carrier phase estimation etc., concrete flow process is seen the Fig. 3 in the accompanying drawing.

Be very crucial technology synchronously in the ofdm system, but, the time reason has any problem owing to implementing with original synchronized algorithm that proposes, so we have only used the method for simple energy related synchronization in system, we also have a lot of needs of work to do synchronously with regard to OFDM.We were divided into for four steps synchronously, symbol is slightly synchronous, decimal Frequency Estimation and correction, integer frequency estimation and correction and fine synchronization, whole this synchronizing process needs the better controlled clock, we carry out estimation and the correction and the optimum sampling point differentiation of phase place after finishing above synchronizing process.We handle the frame of signal after finishing synchronously, and we abandon Cyclic Prefix and synchronous head in the signal frame, directly give the processing unit of back with the data segment in the Frame.

We have adopted the synchronous method of module, i.e. sampling come in after the data of some DSP just the triggering synchronous module carry out synchronously, as us is that per 128 point data trigger a synchronization module, so just reduced and preserved instruction on-the-spot and that the context switching is consumed, improved the efficient of program running.

Synchronously thick: as, when receiver finds that the output valve of M (n) keeps greater than certain thresholding in a period of time, to think that then frame head is correctly caught at receiving terminal.Though from certain angle, this frame head is caught function and had certain ambiguity, it realizes simple, can must catch frame head the soonest, and also have thin synchronization module to provide accurate timing position subsequently.We selected DSP of the processing of precision aspect is a C54X series, is the fixed DSP of 16bit.

Thick implementation method synchronously:

Thick frame synchronization realizes utilizing formula:

$M\left(n\right)=\frac{{\left|p\left(n\right)\right|}^2}{\left|R_0\left(n\right)\right|\•{|R}_N\left(N\right)|}$

Because:

$P\left(n\right)=\underset{i=0}{\overset{N-1}{\mathrm{\Σ}}}r(n+i)\·r^{*}(n+N+i)$

$P(n-1)=\underset{i=0}{\overset{N-1}{\mathrm{\Σ}}}r(n+i-1)\·r^{*}(n+N+i-1)$

Can obtain:

P (n)=P (n-1)+r (n+N-1) r ^*(n+2N-1)-r (n-1) r ^*(n+N-1) like this when new sampled data input is whenever arranged according to following formula can only need carry out 2 multiplyings can obtain corresponding P (n).Same R ₀(n) and R _N(n) also can carry out corresponding calculating fast, improve the arithmetic speed of thick frame synchronization.

$R_0\left(n\right)=\underset{i=0}{\overset{N-1}{\mathrm{\Σ}}}{\left|r(n+i)\right|}^2{R}_0(n-1)+{(n+N-1)|}^2{\left|r(n-1)\right|}^2$

$R_N\left(n\right)=\underset{i=0}{\overset{N-1}{\mathrm{\Σ}}}{\left|r(n+N+i)\right|}^2=R_N(n-1)+{\left|r(n+2N-1)\right|}^2-{\left|r(n+N-1)\right|}^2$

By on can get the flow process of synchronization module:

1) system power on or the situation of system reset under, give P (n), R ₀(n) and R _N(n) compose zero initial value.

2) do not detecting under the situation of thick frame, 8 the sampled point synchronization control module in every interval send to thick frame synchronization module solicited message and data, and thick frame synchronization receives information and corresponding data computation goes out P (n), R ₀(n) and R _N(n).

3) according to the thresholding of setting, need to consume ample resources because the divide operations that digital circuit realizes is comparatively complicated, thresholding is converted into fractional form

Judge M1=a|R ₀(n) || R _N(n) | with M2=b|P (n) | ²Size.As M2〉during M1, will be used to write down the counter that M (n) surpasses default thresholding number of times and add 1, otherwise, be the continuous default thresholding that surpasses to guarantee signal with this counter zero setting.

4) when counter values during, think to have detected thick frame this moment, send flag information to synchronization control module greater than a designated value.Synchronization control module is about to thick frame synchronization submodule and hangs up when receiving this information, simultaneously P (n) data latching is used for decimal frequency bias and estimates.

The implementation method that decimal frequency bias is estimated and corrected

Decimal frequency bias estimates that detecting signal at thick frame sends flag information and carry out later on, is undertaken by the control of synchronization module control end.Synchronization control module enables the decimal frequency bias estimation module after receiving that thick frame synchronization detects the flag bit of valid frame, simultaneously the data P (n) that obtains in the thick frame synchronization is issued the decimal frequency bias estimation module.Decimal frequency bias estimates to adopt the aforementioned estimation formula: $\widehat{\mathrm{\ϵ}}=-\frac{1}{2\mathrm{\π}}\∠P\left(n\right).$ Sampling divides 50 parts with circumference etc. when calculating decimal frequency bias, and the sine and cosine value of all angles and P (n) are relatively got near the phase place of person as P (n).

Decimal frequency bias needs the decimal frequency bias of data is corrected after estimating to finish.The process of correcting adopts open-loop method, by designing a DDS frequency source, in FPGA data and corresponding frequency is multiplied each other and reaches the purpose that compensates decimal frequency bias.

$r^{\′}\left(n\right)=s\left(n\right)e^{j2\mathrm{\πn\ϵ}/N}\·e^{-j2\mathrm{\π}(n+n_0)\mathrm{\ϵ}/N}=s\left(n\right)e^{-j2\mathrm{\π}{n}_0\mathrm{\ϵ}/N}$

Following formula shows by using built-in numerical frequency source can compensate decimal frequency bias, but because and do not know definite starting point, suppose that when data are corrected starting point is the original position that thick frame synchronization obtains, this just causes existing e ^{-j2 π n0 ε/N}Phase error.This phase error is equal to the phase difference of two places carrier wave to the influence of system.Can with the carrier phase error correction that combines.

Decimal frequency bias estimates and corrects the flow chart realized as shown in Figure 7, and we need try to achieve the angle of P (n) in the process of estimating, the implementation method that we have utilized look-up table and Cordic to examine to ask two kinds of method integer frequency bias of degree of chamfering to estimate and correct:

The estimation of integer frequency bias need be used the frequency domain information of sequence.64 data after the starting point that at first needs thick frame synchronization is determined are carried out the fft conversion, and this part circuit can call the module of the demodulation of ofdm signal, and what need finish mainly is interface problem.After obtaining the frequency domain sequence of data, data are sent into the integer frequency bias estimation unit estimate, the following estimation formulas that adopts:

$C\left(d\right)=\frac{|P\left(d\right){|}^2}{{E_0}^2\·{E_1}^2}$

$P\left(d\right)=\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}\left|R_k\right|\·\left(2\right|S_k\left(d\right)|-1)$

$E_0=\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}|R_k{|}^2$ $E_1=\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}{\left|S_k\right|}^2$

The flow chart that integer frequency bias is estimated and correction realizes as shown in Figure 8.

The integer frequency bias estimation module at first receives the frequency domain sequence of data, utilize local sequence and integer frequency bias estimation module to calculate correlation energy, then local sequence is done cyclic shift, ask correlation energy to arrive original local sequence with the data frequency domain sequence again up to cyclic shift.The maximum of points of the maximum correlation energy that obtains in this process is exactly pairing integer frequency deviation amount, and pairing side-play amount is negative normalization frequency deviation after the 32nd circulation

When data are corrected, use the numerical frequency source signal equally, principle is corrected identical with decimal frequency bias.

It is synchronously thin: because the frame head that the frame head acquisition algorithm obtains location only falls into the region of no relief of frame head correlation function, therefore there is certain ambiguity the frame head position, the meticulous timing that native system adopts is based on the thought of closing fine synchronization among the IEEE 802.11a with two-phase, promptly allow receiving sequence and local reference sequences make multiple correlation, just can obtain outstanding and sharp-pointed relevant peaks, another benefit of doing like this is to detect the pseudo-frame head that whether has periodic noise to produce to catch, thereby improves synchronous accuracy.Memory space and precision are handled: the thin DSP memory module that needs 2 128 bytes synchronously when carrying out computing, adding 1 A/D data writing module needs 3 memory modules altogether, so the memory space of 4 modules can satisfy thin synchronous requirement in slightly synchronous.Aspect the precision processing be the same synchronously slightly.The normalization correlation function that meticulous frame synchronization is used is as follows:

$M\left(n\right)=\frac{{\left|P\left(n\right)\right|}^2}{E\left(n\right).E_s}$

Wherein $P\left(n\right)=\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}r(n+k)\·s_k^{*},$ Be the correlation energy of received signal and local reference sequences, $E\left(n\right)=\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}{\left|r(n+k)\right|}^2,$ Be the energy of received signal in associated window, because the phase place of the just signal of correction of frequency deviation effects like this, E (n) can use the R that calculates in thick frame synchronizing process ₀(n) sequence replaces.To reduce system consumption. $E_s=\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}{\left|S_k\right|}^2,$ For the energy of reference sequences is a constant.So in main task of meticulous frame synchronization stage is to have two, the one, the calculating of P (n), the 2nd, the maximum of searching M (n).

The flow chart that meticulous frame synchronization process realizes as shown in Figure 9.

Meticulous frame synchronization process flow process is:

1) from the starting point of thick frame synchronization definition, synchronization control module is incited somebody to action 64 data subsequently, and the energy value E (n) that these 64 data are calculated by thick frame synchronizing process issues meticulous frame synchronization process module;

2) meticulous frame synchronization is set a lower thresholding initialized the time.64 data and the local reference sequences that will receive in meticulous frame synchronization are asked correlation energy.Calculate molecule and the denominator of M (n) respectively, utilize multiplication cross method (avoiding division arithmetic) to compare the size of M (n) and default thresholding then.As M (n) during greater than default threshold value, the molecule denominator of the default thresholding molecule denominator with M (n) is replaced, be used for follow-up comparison, store corresponding positional information simultaneously;

3) after one section 64 point data transmission finished, synchronization control module reservation regular hour surplus was used for meticulous frame synchronization module and carries out data processing.Then, move after the starting point with the definition of thick frame synchronization, carry out 1,2 liang of step again, up to moving to back 64 of thick frame synchronization starting point, to guarantee in information sequence, to include first section sync symbol of synchronous training sequence;

4) at this moment, the positional information of meticulous frame synchronization module output is the maximum position of being asked of M (n).

The implementation that optimum sampling point is differentiated:

In order to solve the optimum sampling point timing offset, ofdm system has adopted oversampling technique.In the content that discuss the front, sampled point is meant that under the situation of 8 sampling rates per 8 points are chosen the sampled point sequence that first point is wherein formed.When carrying out correcting frequency deviation, except that need are corrected use sampled point sequence, need that also remaining sampled point sequence is carried out same data and correct.

Obtain in meticulous frame synchronization using formula under the situation of comparatively accurate frame starting point:

$M\left(n\right)={|\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}r(n+k)\·s_k^{*}|}^2$

Wherein r (n+k) is the data of over-sampling, is divided into 8 groups in order, S _kBe local training sequence.In definite meticulous frame lock bit postpone.Is starting point to 8 groups of sampled datas with meticulous frame alignment position, and computing formula (3.24) is a starting point with the previous point in meticulous frame alignment position then respectively, respectively computing formula (3.24).The M that obtains after calculating is finished (n) maximum and corresponding sampled point can be similar to thinks optimum sampling point.

The FFT module realizes: FFT is used in receiving terminal, because the data that receiving terminal receives all are real numbers, carries out computing so adopted certain method to make real number FFT become plural FFT, has saved the original closely amount of calculation of half.In fact this method is also finished in the lump and is understood the conjugation expansion.Go expansion, the carrier wave inverse mapping.Data are counter to be adjusted, anti-16QAM mapping, and reciprocal cross is knitted.

The realization of Viterbi decoding: butterfly type figure is the core that the Viterbi algorithm is realized, the processing of butterfly type figure has determined the efficient of Viterbi algorithm.Realize Viterbi in DSP, we have used certain methods and means to improve the quality of program.

Utilize the method that produces fast table to improve the speed of Branch Computed tolerance.

Made full use of the function of C54X DSP cyclic addressing, made Metrix and Transition_matrix all be limited in the Circular Buffer the inside of 128 bytes, the saving of maximum possible and utilized memory.

Made full use of the hardware supports of DSP to the Viterbi algorithm.Two 16 bit arithmetic abilities (C16=1) such as accumulator; Special is comparison, selection and the memory cell (CSSU) etc. of Viterbi algorithm design, uses these special hardware supports to quicken the speed of decoding.

After decoding was finished, we just utilized the port (serial ports) of receiving terminal (PC etc.) to receive data.

Transmitting terminal:

1) produce data flow by host computer, the requirement according to data segment part in the frame format of system simultaneously sends.

2) DSP of convolution code realizes: convolution code is that the information sequence that will send passes through a linearity, the shift register of finite state and the coding that produces, usually the encoder of convolution code is made up of the shift register and n the linear algebra function generator (being modulo 2 adder here) of K level (every grade of k bit), need encoded binary data serial input shift register, move into the k Bit data at every turn.The output sequence of the corresponding n bit of the list entries of each k bit.Therefore the code efficiency of convolution code is defined as R _c=k/n.Parameter K is known as the constraint length of convolution code, and its expression has relation by current n bit output sequence and what k bit list entries, also is simultaneously the important parameter of a decision coding complexity.

3) in our channel coding schemes, selected K=7 the most frequently used in engineering for use, k=1, and n=2 (R _c=1/2) convolution code.The Viterbi algorithm is adopted in decoding, gets δ=40＞5K, hard decision.The generator polynomial of (7,1,2) convolution code is expressed as with octal number: POLYA=133, POLYB=171

4) in fact we have carried out once interweaving with regard to being equivalent to the data behind the coding when carrying out convolutional encoding, and this problem is carried out a reciprocal cross and just knitted and can be resolved before decoding.What should be noted that a bit is: initial condition all was 0 state when general convolution code had just begun to encode, and the afterbody of bit stream can be with filling out 0 " Flushing ", to allow encoding state revert to 0 when coding soon finishes.So our information sequence afterbody must be got back to 0 state to force encoder at the afterbody of frame data artificially with the data 000000 that add 6bit, make to recall for the last time when deciphering to obtain correct decode results.

5) interweave, the mode that interweaves has two kinds: block interleaving (Block Interleaving) and convolutional interleave (Convolutional Interleaving), we have selected block interleaving for use in the system.The process of block interleaving is: the data after m rank interleaver will be encoded are lined up the array format that the capable n of m is listed as by the direction of row, by the direction that is listed as sense data successively, finish interweaving of data then.As Fig. 2 schematic diagram that interweaves, at receiving terminal, the data of deinterleaver after with demodulation are lined up the array format of the capable n row of m by the direction of row, by the direction of row sense data successively, finish the deinterleaving of data then.Interweaving in DSP just becomes the order of depositing of data once, realizes fairly simple.

6) 16QAM mapping: in actual applications, we are usually with a kind of baseband signal that is called multi-system (as 4 systems, 8 systems, 16 systems etc.).Multi-system digitally modulated carrier parameter has the different value of M kind, and the multi-system digital modulation has two outstanding advantages than binary digit modulation: the one, and have and contain more information in the multi-system digital signal and make band efficiency higher; The 2nd, longer duration under identical information rate can improve the energy of code element, thereby reduces because the intersymbol interference that the characteristic of channel causes.We have used the 16QAM modulation in the multi-system modulation, and planisphere has adopted the square planisphere, and relevant parameter is: minimum phase skew θ _Min=18 °, minimum Eustachian distance $d_{\min }=0.63\sqrt{E_0}$ , peak to average is γ=1.8, E ₀Be average power.

7) virtual carrier and conjugation expansion: being added among the DSP of virtual carrier finished by a carrier wave mapping graph, and the data of carrier wave mapping graph include only 0 and 1, and the frequency band of OFDM is divided into several subcarriers, and several 0 and 1 data are just arranged in the carrier wave mapping graph.The corresponding subcarrier of 0 expression is not used for transmitting data (just adding 0 handles), and the corresponding subcarrier of 1 expression is used for transmitting data.Used 256 subcarriers in our ofdm system altogether, wherein 128 is virtual carrier, and 112 of front and 16 of back are virtual carriers, and 128 subcarriers in the middle of having only are used for transmitting data.

Carrier wave mapping graph rule

8) essence of conjugation expansion is the characteristic of having used Fourier transform.We know that the result after the real signal Fourier transform is that amplitude spectrum is even symmetry, and phase spectrum is odd symmetry, and this is that real signal has especially.OFDM realizes that with IFFT modulation just is converted to time-domain signal to frequency-region signal, if we are arranged to even symmetry with the amplitude spectrum of frequency-region signal wittingly, phase spectrum is arranged to odd symmetry, and then the time-domain signal that comes out of conversion must be real signal.We just can just can send data through carrier modulation by single channel D/A like this, and can not change the frequency spectrum of signal.If OFDM adopts the mode on I, Q road, must add that then carrier modulation could send data.So the conjugation expansion is exactly consciously frequency domain to be mended to meeting the frequency domain of real signal characteristics.

9) virtual carrier and conjugation are expanded coefficient result and be: ofdm system sends signal with single channel, is W if send the baseband frequency spectrum width of signal, and then the frequency spectrum that actual transmission signal takies under the effect of virtual carrier is

The realization of virtual carrier and conjugation expansion is all made amendment or is resequenced and realize memory content among the DSP.

10) realization of IFFT in DSP: in IFFT, adopted the IFFT algorithm of TI based on base 4 and base 2, the benefit of doing like this is the number of times that has reduced complex multiplication, also having good characteristics is exactly in fixed-point DSP chip, can very simply use one the method for moving to right and finish the computing of l/N, and prevent the possibility of overflowing in the calculating process.

11) the D/A data are adjusted: also having a job to do before carrying out packing data, is exactly that initial data is converted to the data that are fit to the D/A transmission.

Receiving terminal:

1). signal is transmitted in receiving terminal at first by coupler via channel, carry out then carrier wave move this be with transmitting terminal corresponding one with the signal downconversion process.

2). after signal was finished down-conversion, sampling became digital signal with analog signal through A/D.

3). synchronization module: be very crucial technology synchronously in the ofdm system, but, the time reason has any problem owing to implementing with original synchronized algorithm that proposes, so we have only used the method for simple energy related synchronization in system, we also have a lot of needs of work to do synchronously with regard to OFDM.We were divided into for four steps synchronously, symbol is slightly synchronous, decimal Frequency Estimation and correction, integer frequency estimation and correction and fine synchronization, whole this synchronizing process needs the better controlled clock, we carry out estimation and the correction and the optimum sampling point differentiation of phase place after finishing above synchronizing process.We handle the frame of signal after finishing synchronously, and we abandon Cyclic Prefix and synchronous head in the signal frame, directly give the processing unit of back with the data segment in the Frame.

4). we have adopted the synchronous method of module, i.e. sampling come in after the data of some DSP just the triggering synchronous module carry out synchronously, as us is that per 128 point data trigger a synchronization module, so just reduced and preserved instruction on-the-spot and that the context switching is consumed, improved the efficient of program running.

5). synchronously thick: as, when receiver finds that the output valve of M (n) keeps greater than certain thresholding in a period of time, to think that then frame head is correctly caught at receiving terminal.Though from certain angle, this frame head is caught function and had certain ambiguity, it realizes simple, can must catch frame head the soonest, and also have thin synchronization module to provide accurate timing position subsequently.

6). we selected DSP of the processing of precision aspect is a C54X series, is the fixed DSP of 16bit.

7). synchronously thin: because the frame head that the frame head acquisition algorithm obtains location only falls into the region of no relief of frame head correlation function, therefore there is certain ambiguity the frame head position, the meticulous timing that native system adopts is based on the thought of closing fine synchronization among the IEEE 802.11a with two-phase, promptly allow receiving sequence and local reference sequences make multiple correlation, just can obtain outstanding and sharp-pointed relevant peaks, another benefit of doing like this is to detect the pseudo-frame head that whether has periodic noise to produce to catch, thereby improves synchronous accuracy.

8). memory space and precision are handled: the thin DSP memory module that needs 2 128 bytes synchronously when carrying out computing, adding 1 A/D data writing module needs 3 memory modules altogether, so the memory space of 4 modules can satisfy thin synchronous requirement in slightly synchronous.Aspect the precision processing be the same synchronously slightly.

9) the .FFT module realizes: FFT is used in receiving terminal, because the data that receiving terminal receives all are real numbers, carries out computing so adopted certain method to make real number FFT become plural FFT, has saved the original closely amount of calculation of half.In fact this method is also finished in the lump and is understood the conjugation expansion.

10). go expansion, the carrier wave inverse mapping is a baseband signal with the frequency spectrum down-frequency conversion;

11). data are counter to be adjusted, anti-16QAM mapping, reciprocal cross is knitted.At receiving terminal, the data of anti-interleaver after with demodulation are lined up the array format of the capable n row of m by the direction of row, by the direction of row sense data successively, finish the reciprocal cross of data and knit then;

12) realization of .Viterbi decoding: butterfly type figure is the core that the Viterbi algorithm is realized, the processing of butterfly type figure has determined the efficient of Viterbi algorithm.Realize Viterbi in DSP, we have used certain methods and means to improve the quality of program.

Utilize the method that produces fast table to improve the speed of Branch Computed tolerance.

Made full use of the function of C54X DSP cyclic addressing, made Metrix and Transition_matrix all be limited in the Circular Buffer the inside of 128 bytes, the saving of maximum possible and utilized memory.Made full use of the hardware supports of DSP to the Viterbi algorithm.Two 16 bit arithmetic abilities (C16=1) such as accumulator; Special is comparison, selection and the memory cell (CSSU) etc. of Viterbi algorithm design, uses these special hardware supports to quicken the speed of decoding.

13). after decoding is finished, utilize the port (serial ports) of receiving terminal (PC etc.) to receive data.

Claims (2)

1. the digital signal processing method of an electric line communication system is characterized in that this digital signal processing method divides transmitting terminal and receiving terminal two parts, and the step of its processing method is:

Transmitting terminal:

1) host computer produces data flow, and the requirement according to data segment part in the frame format of system simultaneously sends;

2) DSP of long-pending sign indicating number realizes: convolution code is the information sequence that will send by a linearity, the shift register of finite state and the coding that produces, usually the encoder of convolution code by KLevel, every grade kThe shift register of bit and nIndividual linear algebra function generator-modulo 2 adder is formed, and needs encoded binary data serial input shift register, the each immigration kBit data, each kCorresponding one of the list entries of bit nThe output sequence of bit in channel coding schemes, is selected for use in engineering the most frequently used K=7, k=1 and n=2R _c=1/2 convolution code, the Viterbi algorithm is adopted in decoding, gets δ=40＞5 K, hard decision, the generator polynomial of (7,1,2) convolution code is expressed as with octal number: POLYA=133, POLYB=171;

Initial condition all was 0 state when 3) general convolution code had just begun to encode, and the afterbody of bit stream can be with filling out 0 " Flushing " when coding soon finishes, to allow encoding state revert to 0, so the information sequence afterbody must be artificially with the data 000000 that add 6bit, to force encoder to get back to 0 state, make to recall for the last time when deciphering to obtain correct decode results at the afterbody of frame data;

4) interweave: the mode that interweaves has two kinds of block interleaving and convolutional interleaves, select block interleaving in the system for use, the process of block interleaving is: the data after m rank interleaver will be encoded are lined up the array format that the capable n of m is listed as by the direction of row, by the direction that is listed as sense data successively, finish interweaving of data then;

5) 16QAM mapping: use the 16QAM modulation in the multi-system modulation, planisphere adopts the square planisphere, and relevant parameter is: the minimum phase skew θ _Min=18 °, minimum Eustachian distance $d_{\min }=0.63\sqrt{E_0}$ , peak to average is γ=1.8, E ₀Be average power;

6) virtual carrier and conjugation expansion: being added among the DSP of virtual carrier finished by a carrier wave mapping graph, the data of carrier wave mapping graph include only 0 and 1, the frequency band of OFDM is divided into several subcarriers, several 0 and 1 data are just arranged in the carrier wave mapping graph, the corresponding subcarrier of 0 expression is not used for transmitting data, and the corresponding subcarrier of 1 expression is used for transmitting data; Used 256 subcarriers in ofdm system altogether, wherein 128 is virtual carrier, and 112 of front and 16 of back are virtual carriers, and 128 subcarriers in the middle of having only are used for transmitting data

Carrier wave mapping graph rule, the utilization Fourier transform, result after the real signal Fourier transform is that amplitude spectrum is even symmetry, phase spectrum is odd symmetry, and OFDM realizes that with IFFT modulation just is converted to time-domain signal to frequency-region signal, is arranged to even symmetry with the amplitude spectrum of frequency-region signal, phase spectrum is arranged to odd symmetry, then the time-domain signal that comes out of conversion must be real signal, can just can lean on single channel D/A send data through carrier modulation, and can not change the frequency spectrum of signal; If OFDM adopts the mode on I, Q road, must add that then carrier modulation could send data, the conjugation expansion is exactly consciously frequency domain to be mended to meeting the frequency domain of real signal characteristics;

7) virtual carrier and conjugation are expanded coefficient result and be: ofdm system sends signal with single channel, is W if send the baseband frequency spectrum width of signal, and then the frequency spectrum that actual transmission signal takies under the effect of virtual carrier is $[\frac{112}{256}W,\frac{241}{256}W]$ , the realization of virtual carrier and conjugation expansion is all made amendment or is resequenced and realize memory content among the DSP;

8) realization of IFFT in DSP: in IFFT, adopted the IFFT algorithm of TI, reduced the number of times of complex multiplication, in fixed-point DSP chip, used one the method for moving to right and finish the computing of 1/N, and prevent overflowing in the calculating process based on base 4 and base 2;

9) the D/A data are adjusted: before carrying out packing data, initial data is converted to the data that are fit to the D/A transmission;

Receiving terminal:

10) signal via channel be transmitted in receiving terminal at first by coupler, carry out carrier wave then and move, this be with transmitting terminal corresponding one with the signal downconversion process;

11) after signal is finished down-conversion, sampling becomes digital signal with analog signal through A/D;

12) synchronization module: be divided into for four steps synchronously, symbol is slightly synchronous, decimal Frequency Estimation and correction, integer frequency estimation and correction and fine synchronization;

13) memory space and precision are handled: the thin DSP memory module that when carrying out computing, needs 2 128 bytes synchronously, adding 1 A/D data writing module needs 3 memory modules altogether, aspect the precision processing and thick be the same synchronously;

14) the FFT module realizes: FFT is used in receiving terminal, because the data that receiving terminal receives all are real numbers, carries out computing so adopted certain method to make real number FFT become plural FFT, has saved the original closely amount of calculation of half, finishes in the lump and understands the conjugation expansion;

15) go expansion, the carrier wave inverse mapping is a baseband signal with the frequency spectrum down-frequency conversion;

16) data are counter adjusts, anti-16QAM mapping, and reciprocal cross is knitted, and at receiving terminal, the data of anti-interleaver after with demodulation are lined up the array format of the capable n row of m by the direction of row, by the direction of row sense data successively, finish the reciprocal cross of data and knit then;

17) realization of Viterbi decoding: butterfly type figure is the core that the Viterbi algorithm is realized, the processing of butterfly type figure has determined the efficient of Viterbi algorithm, realizes Viterbi in DSP, utilizes the method that produces fast table to improve the speed of Branch Computed tolerance; Utilize the function of C54X DSP cyclic addressing, make Metrix and Transition_matrix all be limited in the Circular Buffer the inside of 128 bytes, the saving of maximum possible and utilized memory;

18) after decoding is finished, receive data with regard to the communication serial port that utilizes receiving terminal.

2. the digital signal processing method of electric line communication system according to claim 1 is characterized in that the step of its synchronization module processing method is:

1) be divided into for four steps synchronously, symbol is slightly synchronous, decimal Frequency Estimation and correction, integer frequency estimation and correction and fine synchronization; In estimation and the correction of finishing the above laggard line phase of synchronizing process, optimum sampling point is differentiated; After success synchronously, the frame of signal is handled, abandoned Cyclic Prefix and synchronous head part in the signal frame, directly obtain the data segment part in the Frame, and data segment is partly given the processing unit of back;

2) adopt the synchronous method of module, i.e. sampling come in after the data of some DSP just the triggering synchronous module carry out synchronously, per 128 point data trigger a synchronization module, have so just reduced and have preserved instruction on-the-spot and that the context switching is consumed, have improved the efficient of program running;

3) synchronously thick: at receiving terminal, when receiver finds that the output valve of M (n) keeps greater than certain thresholding in a period of time, think that then frame head is correctly caught, we selected DSP of the processing of precision aspect is a C54X series, is the fixed DSP of 16bit;

4) synchronously thin: the frame head that the frame head acquisition algorithm obtains is located in the region of no relief that only falls into the frame head correlation function just passable, the meticulous timing of adopting is based on the implementation method of closing fine synchronization among the IEEE 802.11a with two-phase, promptly allow receiving sequence and local reference sequences make multiple correlation, obtain outstanding and sharp-pointed relevant peaks, detect the pseudo-frame head that whether has periodic noise to produce and catch, improved synchronous accuracy.