CN1937435A - Digital signal processing method for power line communication system - Google Patents

Abstract

The digital signal processing method of the power line communication system is a method for high-speed transmission of data signals in the power line, especially a method for broadband high-speed power carrier communication based on Orthogonal Frequency Division Multiplexing (OFDM). The method is divided into two parts: the transmitting end and the receiving end. Using Orthogonal Frequency Division Multiplexing (OFDM) technology, the research and development of the key technology of broadband high-speed power carrier communication system is realized by using the power line. The communication rate of this method is ≥50Kbps; the direct communication distance is ≥ 100 meters; and realize the Internet access of the system; do the basic work for the next step of designing a power line carrier communication system with a communication rate of 1-10Mbps.

Description

Digital Signal Processing Method for Power Line Communication System

technical field

The invention is a method for high-speed transmission of data signals in power lines, in particular a method for broadband high-speed power carrier communication based on Orthogonal Frequency Division Multiplexing (OFDM), which belongs to the technical field of wired communication.

Background technique

The current communication methods include wireless channel communication and wired channel communication. Power Line Communication (Power Line Communication) technology refers to a system based on the power transmission network that realizes communication between nodes within the power line communication network and with other communication networks. . Its history can be traced back to the 1920s. At that time, the power line communication technology mainly used high voltage above 11kV for long-distance information transmission, and the working frequency was below 150kHz. Later, this frequency band became the official frequency band of power line communication of the European Technical Standardization Committee. It is one of the main forms of power line communication technology to transmit long-distance data or voice at a low frequency (9-490kHz) at a low rate through a power line carrier on a medium and high voltage transmission network (above 35kV). In the field of low voltage (220V), the transmission rate of PLC technology is generally 1200b/s or lower, which is called low-speed PLC. In recent years, the power line communication technology using low-voltage power line transmission rate above 1Mb/s developed at home and abroad is called high-speed PLC. PLC technology was first used in load control, remote meter reading and home automation.

The use of power lines as the LAN bus in PLC technology has its significant advantages: low cost, convenient construction, dual-purpose one-line, low price, and convenient extension. Powerlines are ubiquitous in homes, businesses and places, and are more extensive than cable and landline telephone networks. The biggest problem is that powerline networks are designed to carry electricity, not data. Therefore, the power line is an unreliable transmission channel and has a lot of noise and attenuation. Due to the development of modern digital communication technology, the introduction of various advanced modulation and demodulation technologies (such as OFDM) and modern DSP technology, power line carrier communication has become possible.

In recent years, the research on power line communication and Internet interconnection technology at home and abroad is very active. Since Norweb Communications, a subsidiary of United Power Corporation of the United Kingdom, began research on power line carrier communication in 1990, research institutions in many countries have carried out research and development of high-speed power line technology, such as China's Electric Power Research Institute, the United States' Intellon, Spain's DS2 company, etc., the transmission rate of the product has also developed from 1Mb/s to 45Mb/s, and the current high-speed PLC has reached 200Mb/s.

With the rapid development of Internet technology, the number of people logging on to the Internet has doubled. However, what communication method to use to connect the user terminal to the nearest broadband network connection device has become one of the difficulties that have plagued people for a long time, and it is also one of the bottlenecks for Internet popularization. It is called "the last mile" of broadband network access by industry insiders. "question. Using the 220V low-voltage power line extending in all directions, all over urban and rural areas, and direct to users to transmit high-speed data, the PLC technology is considered by the industry to be the most competitive solution for the "last 300m" because of its remarkable characteristics of no wiring, wide coverage, and convenient connection. One of the techniques.

High-speed PLC can already transmit data up to 45Mb/s, and can transmit data, voice, video and power at the same time, which may bring a new trend of "four networks in one".

According to the configuration of the local power grid and the degree of marketization of various Internet access technologies, the current high-speed PLC technology mainly has two development modes:

One is the home networking model represented by the United States. This mode of PLC only provides home networking, and other traditional communication methods are used for outdoor access. On the one hand, this is due to the relatively mature and popular technologies and products such as ADSL and HFC in the United States. More importantly, because the low-voltage distribution transformers in the United States are generally single-phase, they only provide power supply services for 5 to 6 users on average, and promote high-speed PLC. Due to the high cost of access technology.

Another model is for the European and Asia-Pacific markets. Because the structure of the low-voltage distribution network in these areas is relatively similar, it generally provides power supply services for 200 to 300 users, and the average cost of promoting high-speed PLC access services is low. This application mode provides a comprehensive PLC solution from the distribution transformer or building to the user's home. Since outdoor products are used in different environments from indoor products, it is difficult to implement technically. Therefore, the number of companies that can provide this solution is relatively small, mainly including DS2 in Spain, Ascom in Switzerland, and Main.Net in Israel. These companies have established experimental networks in Spain, Germany, Austria, France in Europe and South Korea, Singapore, Hong Kong and other countries and regions in Asia.

International organizations for high-speed power line communication mainly include the HomePlug Powerline Alliance (HPA), PLC Forum, PALAS (Powerline as an Alternative Local AccessS), and ECHONET in Japan.

The Home Plug Alliance, formed by 13 companies including Cisco, Intel, Hewlett-Packard, Panasonic and Sharp, was established in April 2000 and is committed to creating a common technical standard for home power line network communication. At present, HPA has developed into an enterprise group composed of 90 companies, and the technology of Intellon Company of the United States is selected as the prototype of the unified technical standard. In June 2001, HPA released the first version of its standard, Home-PlugSpecfication 1.0, setting the data transmission rate at 14Mb/s, using OFDM modulation and demodulation technology, and the MAC layer protocol as CSMA/CA. This standard is oriented towards home internal network applications, and is less involved in outdoor high-speed power line access.

It is under such a background at home and abroad that the staff of this research group have conducted experimental research on the application of OFDM in low-voltage power carrier communication, and after testing and referring to some power line channel data, they have determined the The realization method of the DSP. The content of this patent is mainly to integrate and apply the research results that the research team has achieved: the realization method of DSP of the power line communication system based on Orthogonal Frequency Division Multiplexing.

The application of OFDM technology in power line communication has gradually been recognized by counterparts at home and abroad, and foreign countries have developed and launched communication modules with 10Mbps or even higher. Since the core technology has not been mastered in China, it is very necessary to actively carry out research on the core technology of power carrier communication in our country.

The goal of this invention is to promote the development of the core technology of low-voltage power line carrier communication in my country, provide decision-making basis for the designation of power line communication standards in my country, and provide key technologies and products for the development of power line communication systems that adapt to the current situation of my country's power grid.

Contents of the invention

Technical problem: The purpose of this invention is to provide a digital signal processing method based on OFDM power line communication system, the communication rate of this method is ≥50Kbps; the direct communication distance is ≥100 meters; and the Internet access of the system is realized ; Do a good job of basic work for the next step of designing a power line carrier communication system with a communication rate of 1-10Mbps.

Technical scheme: the method of the present invention adopts Orthogonal Frequency Division Multiplexing (OFDM) technology, utilizes power line to realize the research and development of the key technology of broadband high-speed power carrier communication system (based on the DSP of the power line communication system of Orthogonal Frequency Division Multiplexing accomplish).

The digital signal processing method is divided into two parts, the transmitting end and the receiving end, and the steps of the processing method are: the transmitting end:

1) The upper computer generates a data stream and sends it according to the requirements of the data segment in the system frame format.

2) DSP implementation of product codes: Convolutional codes are codes generated by passing the transmitted information sequence through a linear, finite-state shift register. Usually, the encoders of convolutional codes are composed of K-level, k-bit shift registers per level. Bit register and n linear algebraic function generators-modulo 2 adders, the binary data that needs to be encoded is serially input to the shift register, and k-bit data is shifted in each time, and each k-bit input sequence corresponds to an n-bit output sequence , in the channel coding scheme, the most commonly used convolutional code of K=7, k=1, and n=2R _c =1/2 in engineering is selected, and the decoding adopts the Viterbi algorithm, taking δ=40>5K, hard Judgment, the generator polynomial of the (7,1,2) convolutional code is represented by octal numbers: POLYA=133, POLYB=171.

3) Generally, the initial state of the convolutional code is 0 at the beginning of encoding, and when the encoding is about to end, the tail of the bit stream will be followed by "Flushing" filled with 0, so that the encoding state returns to 0, so the information sequence The tail must be artificially followed by 6-bit data 000000 to force the encoder to return to the 0 state at the end of a frame of data, so that the last backtracking during decoding can obtain the correct decoding result.

4) Interleaving: There are two types of interleaving: block interleaving and convolutional interleaving. In the system, block interleaving is selected. The process of block interleaving is: the m-order interleaver arranges the encoded data into an array of m rows and n columns in the row direction form, and then read the data sequentially in the direction of the column to complete the interleaving of the data.

5) 16QAM mapping: use 16QAM modulation in multi-ary modulation, the constellation diagram adopts a square constellation diagram, and the relevant parameters are: minimum phase offset θ _min = 18°, minimum Euclidean distance $d_{\min }=0.63\sqrt{{\mathrm{E.}}_0},$ The peak-average value is γ = 1.8, and E ₀ is the average power.

6) Virtual carrier and conjugate extension: The addition of virtual carrier is done through a carrier map in DSP. The data in the carrier map only includes 0 and 1. The frequency band of OFDM is divided into several subcarriers. The carrier map There are several 0 and 1 data, 0 means that the corresponding subcarrier is not used to transmit data, 1 means that the corresponding subcarrier is used to transmit data; in the OFDM system, a total of 256 subcarriers are used, of which 128 are virtual carriers , the first 112 subcarriers and the last 16 are virtual carriers, and only the middle 128 subcarriers are used to transmit data Carrier map rules, using Fourier transform, the result of Fourier transform of the real signal is that the amplitude spectrum is evenly symmetrical, and the phase spectrum is oddly symmetrical. OFDM uses IFFT to realize modulation, which is to convert the frequency domain signal into a time domain signal. , the amplitude spectrum of the frequency domain signal is arranged as even symmetry, and the phase spectrum is arranged as odd symmetry, then the transformed time domain signal must be a real signal, and the data can be sent out by a single D/A without carrier modulation. And it will not change the spectrum of the signal; if OFDM adopts I and Q channels, carrier modulation must be added to send the data. Conjugate expansion is to consciously supplement the frequency domain to the frequency domain that conforms to the characteristics of real signals.

7) The result of the joint action of the virtual carrier and conjugate extension is that the OFDM system transmits signals in a single channel. If the baseband spectrum width of the transmitted signal is W, the spectrum occupied by the actual transmitted signal under the action of the virtual carrier is The implementation of virtual carrier and conjugate expansion in DSP is realized by modifying or reordering the contents of memory.

8) Implementation of IFFT in DSP: In IFFT, TI’s IFFT algorithm based on radix 4 and radix 2 is used to reduce the number of complex multiplications. In the fixed-point DSP chip, the method of shifting one bit to the right is used to complete 1/ N operations, and prevent overflow during operations.

9) D/A data adjustment: Before data packaging, convert the original data into data suitable for D/A transmission.

Receiving end:

10) The transmission of the signal through the channel first passes through the coupler at the receiving end, and then performs carrier shifting. This is a process of down-converting the signal corresponding to the sending end.

11) After the signal is down-converted, the analog signal is converted into a digital signal through A/D sampling.

12) Synchronization module: Synchronization is divided into four steps, symbol coarse synchronization, decimal frequency estimation and correction, integer frequency estimation and correction, and fine synchronization; the entire synchronization process requires a good control of the clock, and the phase is performed after completing the above synchronization process Estimation and correction, and discrimination of the best sampling point; after the synchronization is completed, the signal frame is processed, the cyclic prefix and synchronization header in the signal frame are discarded, and the data segment in the data frame is directly handed over to the subsequent processing unit.

13) The method of module synchronization is adopted, that is, the DSP triggers the synchronization module to synchronize after a certain amount of data is sampled, and the synchronization module is triggered once every 128 points of data, which reduces the consumption of instructions for saving the scene and context switching, and improves the program. operating efficiency.

14) Coarse synchronization: at the receiving end, when the receiver finds that the output value of M(n) remains greater than a certain threshold for a period of time, the frame header is considered to be captured correctly, and the DSP we choose for precision processing is C54X Series, 16bit fixed-point DSP.

15) Fine synchronization: because the frame header positioning obtained by the frame header capture algorithm only falls into the plain area of the frame header correlation function, the frame header position has a certain ambiguity, and the fine timing adopted is based on the double correlation in IEEE 802.11a The idea of fine synchronization is to let the received sequence and the local reference sequence be complexly correlated to obtain a prominent and sharp correlation peak, and to detect whether there is a pseudo-frame header capture caused by periodic noise, thereby improving the accuracy of synchronization.

16) Storage capacity and precision processing: fine synchronization requires two 128-byte DSP memory modules when performing calculations, plus 1 A/D data writing module requires a total of 3 storage modules, in terms of precision processing and coarse synchronization it's the same.

17) FFT module implementation: FFT is used at the receiving end, because the data received at the receiving end are all real numbers, so a certain method is adopted to make real number FFT into complex number FFT for operation, which saves nearly half of the original calculation amount. Complete Understanding Conjugate Extensions.

18) Despreading, carrier inverse mapping, down-converting the frequency spectrum into a baseband signal.

19) Data anti-adjustment, anti-16QAM mapping, anti-interleaving, at the receiving end, the anti-interleaver arranges the demodulated data into an array form of m rows and n columns according to the column direction, and then reads the data sequentially according to the row direction, Complete data deinterleaving.

20) The realization of Viterbi decoding: butterfly diagram is the core that Viterbi algorithm realizes, and the processing of butterfly diagram has determined the efficiency of Viterbi algorithm, realizes Viterbi in DSP, utilizes the method for producing fast list to improve the speed of calculation branch measure; Utilize The circular addressing function of C54X DSP limits both Metrix and Transition_matrix to 128-byte Circular Buffer, saves and utilizes the memory as much as possible, and utilizes the hardware support of DSP for Viterbi algorithm, such as the double 16-bit operation of the accumulator Ability; comparison, selection, and storage units specially designed for Viterbi algorithms, using these specialized hardware to support accelerated decoding speed.

21) After the decoding is completed, use the communication serial port of the receiving terminal to receive the data.

Beneficial effects: the present invention is based on the realization of the DSP of the power line communication system of orthogonal frequency division multiplexing, adopts orthogonal frequency division multiplexing (OFDM) technology, utilizes the power line to realize the research and development of the key technology of broadband high-speed power carrier communication system . The application of OFDM technology in power line communication has gradually been recognized by counterparts at home and abroad, and foreign countries have developed and launched communication modules with 10Mbps or even higher. Since the core technology has not been mastered in China, it is very necessary to actively carry out research on the core technology of power carrier communication in our country.

The goal of this invention is to promote the development of the core technology of low-voltage power line carrier communication in my country, provide decision-making basis for the designation of power line communication standards, and provide key technologies and products for the development of power line communication systems that adapt to the current situation of my country's power grid.

Design the hardware circuit realized by DSP;

Realized the OFDM communication system (including FFT/IFFT, QAM mapping, convolutional coding, Viterbi decoding and other modules) on the DSP platform with software algorithms;

Successfully achieved 50kbps data transmission;

Due to the limitation of DSP chip processing capability, the synchronization algorithm adopted is relatively simple (it can be perfected later).

The present invention completes and realizes the OFDM system on the basis of the research of previous staff members. In terms of hardware design, the DSP-based OFDM system has been completed together, providing a stable DSP platform for the sending and receiving ends of the OFDM system. In terms of software design, the quasi-RTOS (DSP/BIOS) introduced by TI in recent years has been adopted, and the design idea based on multi-threading has been used to successfully design the software of OFDM sending end and receiving end, which has taken a meaningful step for practical application .

Description of drawings

Fig. 1 is a system realization block diagram of the present invention,

Fig. 2 is the principle diagram of interleaving of the present invention,

Fig. 3 is the realization flowchart of the synchronization of the present invention,

Fig. 4 is a flowchart of the power communication system of the present invention,

Fig. 5 is the Viterbi decoding flowchart of the present invention,

Fig. 6 is K=7, k=1, and n=2 (R _c =1/2) convolutional code encoding scheme figure,

Fig. 7 is a flow chart of fractional frequency offset estimation and correction,

Fig. 8 is a flowchart of integer frequency offset estimation and correction,

Fig. 9 is a flow chart of fine frame synchronization processing,

Fig. 10 is a flow chart for judging the optimal sampling point.

Detailed ways

System Design

OFDM basic parameter design: bandwidth B＝200kHz

                                  DSP implementation scheme: 200 ~ 400 kHz

The number of sub-channels N＝128

                                                                           

Sub-channel mapping mode selection: 16QAM: 4bit/sub-channel

DQPSK: 2bit/subchannel

Transmission method implementation: DSP solution: baseband conjugate extension

The communication distance is about 100m~1000m

The bit error rate is controlled at around 10e-7~10e-9

symbol length

T=N×1/B=640us

guard interval

Δ=160us

subchannel spacing

Δf=1/T=1.5625kHz

Actual transmission symbol length

T _s ＝T+Δ＝800us

actual symbol rate

f _s ＝1/T _s ＝1/800us＝1.25kbaud

Total bit rate: DSP:

1.25kbaud×128×4bit/symbol＝640kps

Main components required for the project: DSP: TMS320C5416

SRAM: IS61LV25616

FLASH: SST39VF400

              CPLD: EPM7128

A/D: AD7492AR

D/A: AD9762AR

Theoretical research and simulation of the system:

The simulation of the system function is completed under the Matlab platform;

The system dynamic simulation is completed under the SIMULINK platform, and the real-time communication performance of the system is verified; the algorithm of the system is implemented with standard C; the data transmission protocol is simulated with OPNET.

The present invention is based on the realization of the DSP of the power line communication system of orthogonal frequency division multiplexing, adopts orthogonal frequency division multiplexing (OFDM) technology, and utilizes the power line to realize the research and development of the key technology of broadband high-speed power carrier communication system. The application of OFDM technology in power line communication has gradually been recognized by counterparts at home and abroad, and foreign countries have developed and launched communication modules with 10Mbps or even higher. Since the core technology has not been mastered in China, it is very necessary to actively carry out research on the core technology of power carrier communication in our country.

The goal of this invention is to promote the development of the core technology of low-voltage power line carrier communication in my country, provide decision-making basis for the designation of power line communication standards in my country, and provide key technologies and products for the development of power line communication systems that adapt to the current situation of my country's power grid.

Design the hardware circuit realized by DSP;

Realized the OFDM communication system (including FFT/IFFT, QAM mapping, convolutional coding, Viterbi decoding and other modules) on the DSP platform with software algorithms;

Successfully achieved 50kbps data transmission;

Due to the limitation of DSP chip processing capability, the synchronization algorithm adopted is relatively simple (it can be perfected later).

The present invention completes and realizes the OFDM system on the basis of the research of previous staff members. In terms of hardware design, the DSP-based OFDM system has been completed together, providing a stable DSP platform for the sending and receiving ends of the OFDM system. In terms of software design, the quasi-RTOS (DSP/BIOS) introduced by TI in recent years has been adopted, and the design idea based on multi-threading has been used to successfully design the software of OFDM sending end and receiving end, which has taken a meaningful step for practical application .

In 1971, S.B.Weinstein and P.M.Ebert pointed out that the modulation and demodulation of multi-channel orthogonal carriers can be quickly realized by using DFT/IDFT, which is a solid step for the wide application of OFDM technology. The cyclic prefix in OFDM effectively eliminates ISI and ICI.

DSP platform:

After proposing to use IFFT/FFT to realize OFDM modulation and demodulation, it becomes feasible to realize OFDM on DSP. In the system, the C5416 DSP in the TI C5000 series is selected to realize it.

DSP software design environment CCS: In 1999, TI revolutionaryly launched the DSP software integrated development environment Code Composer Studio (CCS for short).

DSP/BIOS: The DSP/BIOS real-time kernel is a quasi-RTOS launched by TI in recent years. Its purpose is to help developers build DSP applications and manage DSP on-chip resources.

1. Directly written in assembly language, ensuring the high efficiency of DSP/BIOS;

2. Support thread-based DSP program design, making multi-task embedded development relatively simple;

3. DSP/BIOS is flexible and scalable, and the minimum occupied space is only 1K bytes on the basis of high efficiency;

4. Provide developers with a unified interface for DSP underlying hardware operations, which can save developers a lot of problems caused by different chip models, and focus on the implementation of applications.

The main implementation process of the system is given in Figure 1. The following describes the entire working process and execution steps of the system in detail:

The data stream is generated by the host computer and sent according to the requirements of the data segment in the frame format of our system.

The DSP implementation of the convolutional code, the convolutional code is the code generated by passing the transmitted information sequence through a linear, finite-state shift register. Usually, the encoder of the convolutional code is composed of K-level (k-bit per level) shift registers and n linear algebraic function generators (here, modulo 2 adders), as shown in Figure 6. The binary data to be coded is serially input into the shift register, and k-bit data is shifted in each time. Each input sequence of k bits corresponds to an output sequence of n bits. Therefore, the coding efficiency of a convolutional code is defined as R _c =k/n. The parameter K is called the constraint length of the convolutional code, which indicates how many k-bit input sequences the current n-bit output sequence is related to, and is also an important parameter that determines the complexity of the encoding.

In our channel coding scheme, the convolutional code with K=7, k=1, and n=2 (R _c =1/2), which is most commonly used in engineering, is selected. Decoding adopts Viterbi algorithm, taking δ=40>5K, hard decision. The generator polynomial of the (7, 1, 2) convolutional code is represented by octal numbers: POLYA=133, POLYB=171.

In fact, when we perform convolutional encoding, it is equivalent to interleaving the encoded data. This problem can be solved by deinterleaving before decoding. One thing to note is that the initial state of the general convolutional code is 0 at the beginning of encoding, and when the encoding is about to end, the tail of the bit stream will be followed by "Flushing" filled with 0, so that the encoding state returns to 0 . Therefore, the end of our information sequence must be artificially followed by 6-bit data 000000 to force the encoder to return to the 0 state at the end of a frame of data, so that the last backtracking during decoding can obtain the correct decoding result.

Interleaving: There are two ways of interleaving: Block Interleaving and Convolutional Interleaving. In the system, we choose block interleaving. The process of block interleaving is as follows: the m-order interleaver arranges the coded data into an array of m rows and n columns according to the row direction, and then reads out the data sequentially according to the column direction to complete the data interleaving. (As shown in Figure 2 Interleaving Schematic), at the receiving end, the deinterleaver arranges the demodulated data into an array of m rows and n columns in the direction of the column, and then reads the data in sequence according to the direction of the row to complete the deinterleaver of the data intertwined. Interleaving in DSP just changes the storage order of data, which is relatively simple to realize.

16QAM mapping: In practical applications, we often use a baseband signal called multi-ary (such as 4-ary, 8-ary, 16-ary, etc.). The multi-ary digital modulation carrier parameter has M different values. The multi-ary digital modulation has two outstanding advantages over the binary digital modulation: one is that the multi-ary digital signal contains more information, which makes the frequency band utilization more efficient. High; second, it lasts for a long time at the same information rate, which can increase the energy of the symbol, thereby reducing the intersymbol interference caused by the channel characteristics. We use 16QAM modulation in multi-ary modulation, and the constellation diagram adopts a square constellation diagram. The relevant parameters are: minimum phase offset θ _min = 18°, minimum Euclidean distance $d_{\min }=0.63\sqrt{{\mathrm{E.}}_0},$ The peak-average value is γ = 1.8, and E ₀ is the average power.

Virtual carrier and conjugate extension: The addition of virtual carrier is done through a carrier map in DSP. The data in the carrier map only includes 0 and 1. The frequency band of OFDM is divided into several subcarriers. In the carrier map, there is There are several 0's and 1's of data. 0 indicates that the corresponding subcarrier is not used to transmit data (that is, add 0), and 1 indicates that the corresponding subcarrier is used to transmit data. A total of 256 subcarriers are used in our OFDM system, 128 of which are virtual carriers, the front 112 and the latter 16 are virtual carriers, and only the middle 128 subcarriers are used to transmit data.

载波映射图规则

Carrier Map Rules

The essence of conjugate extension is to use the characteristics of Fourier transform. We know that the result of the Fourier transform of the real signal is that the amplitude spectrum is evenly symmetric, and the phase spectrum is oddly symmetric, which is special for real signals. OFDM uses IFFT to achieve modulation, which is to convert the frequency domain signal into a time domain signal. If we intentionally arrange the amplitude spectrum of the frequency domain signal as even symmetry and the phase spectrum as odd symmetry, the transformed time domain signal must be real signal. In this way, we can send the data by a single D/A without carrier modulation, and the frequency spectrum of the signal will not be changed. If OFDM adopts the way of I and Q channels, carrier modulation must be added to send the data. So the conjugate extension is to consciously complement the frequency domain to the frequency domain that conforms to the characteristics of the real signal.

The result of the joint action of the virtual carrier and conjugate extension is that the OFDM system transmits signals in a single channel. If the baseband spectrum width of the transmitted signal is W, the spectrum occupied by the actual transmitted signal under the action of the virtual carrier is

DSP中虚载波和共轭扩展的实现都是对存储器内容进行修改或者重新排序来实现的。

The implementation of virtual carrier and conjugate expansion in DSP is realized by modifying or reordering the contents of memory.

Implementation of IFFT in DSP: In IFFT, TI’s IFFT algorithm based on radix 4 and radix 2 is used. The advantage of this is that the number of complex multiplications is reduced. Another good feature is that in fixed-point DSP chips, It is very simple to apply the method of shifting one bit to the right to complete the 1/N operation, and prevent overflow during the operation.

D/A data adjustment: Before data packaging, there is another work that must be done, which is to convert the original data into data suitable for D/A transmission.

Receiving end: The transmission of the signal through the channel first passes through the coupler at the receiving end, and then carries out carrier shifting. This is a process of down-converting the signal corresponding to the sending end. After the signal is down-converted, the analog signal is converted into a digital signal through A/D sampling.

Synchronization module: The synchronization of the system is mainly divided into coarse frame synchronization, decimal frequency offset estimation and correction, integer frequency offset estimation and correction, fine frame synchronization, optimal sampling point discrimination, carrier phase estimation, etc. The specific process is shown in the attached figure image 3.

Synchronization in the OFDM system is a very critical technology, but due to time reasons and the difficulty in implementing the original synchronization algorithm, we only use a simple energy-related synchronization method in the system. As far as OFDM synchronization is concerned, we still have a lot Work needs to be done. Our synchronization is divided into four steps, symbol coarse synchronization, fractional frequency estimation and correction, integer frequency estimation and correction, and fine synchronization. The entire synchronization process requires a good control of the clock. After completing the above synchronization process, we estimate the phase And correction, and best sampling point discrimination. After the synchronization is completed, we process the signal frame. We discard the cyclic prefix and synchronization header in the signal frame, and directly hand over the data segment in the data frame to the subsequent processing unit.

We adopt the method of module synchronization, that is, after a certain amount of data is sampled, the DSP triggers the synchronization module for synchronization. For example, we trigger the synchronization module every 128 points of data, which reduces the consumption of instructions for saving the scene and context switching. Improve the efficiency of program operation.

Coarse synchronization: At the receiving end, when the receiver finds that the output value of M(n) remains greater than a certain threshold for a period of time, it considers that the frame header is correctly captured. Although from a certain point of view, this frame header capture function has a certain degree of ambiguity, but it is simple to implement, and can capture the frame header as quickly as possible, and then there is a fine synchronization module to give precise timing positions. The DSP we choose for precision processing is the C54X series, which is a 16-bit fixed-point DSP.

Coarse synchronization implementation method:

Coarse frame synchronization is implemented using the formula:

$\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; p</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{<span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span><span\; class="notranslate">\; \&bull;</span>{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span>}$

because:

$\mathrm{<span\; class="notranslate">\; P</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; r</span>}}^{<span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span>$

$\mathrm{<span\; class="notranslate">\; P</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; r</span>}}^{<span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

can get:

P(n)=P(n-1)+r(n+N-1) r ^* (n+2N-1)-r(n-1) r ^* (n+N-1) When there is new sampling data input, the corresponding P(n) can be obtained only by performing two multiplication operations according to the above formula. Similarly, R ₀ (n) and R _N (n) can also perform corresponding fast calculations to improve the calculation speed of coarse frame synchronization.

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

The flow of the synchronization module can be obtained from the above:

1) When the system is powered on or the system is reset, assign zero initial values to P(n), R ₀ (n) and R _N (n).

2) In the case that the coarse frame is not detected, the synchronization control module sends the request information and data to the coarse frame synchronization module at intervals of 8 sampling points, and the coarse frame synchronously receives the information and the corresponding data to calculate P(n), R ₀ (n) and R _N (n).

判断M1=a·|R₀(n)|·|R_N(n)|与M2=b·|P(n)|²的大小。当M2>M1时，将用于记录M(n)超过预设门限次数的计数器加1，否则将此计数器置零，以保证信号是连续的超过预设的门限。3) According to the set threshold, because the division operation implemented by the digital circuit is more complicated and consumes a lot of resources, the threshold is converted into a fractional form

Judge the size of M1=a·|R ₀ (n)|·|R _N (n)| and M2=b·|P(n)| ² . When M2>M1, add 1 to the counter used to record the number of times M(n) exceeds the preset threshold, otherwise, set the counter to zero to ensure that the signal continues to exceed the preset threshold.

4) When the counter value is greater than a specified value, it is considered that a coarse frame has been detected at this time, and the flag information is sent to the synchronization control module. When the synchronization control module receives this information, it will suspend the coarse frame synchronization submodule, and at the same time latch the P(n) data for fractional frequency offset estimation.

Realization Method of Fractional Frequency Offset Estimation and Correction

Fractional frequency offset estimation is performed after the coarse frame detects the signal sending flag information, and is controlled by the control terminal of the synchronization module. The synchronization control module enables the fractional frequency offset estimation module after receiving the flag bit indicating that the coarse frame synchronization detects a valid frame, and at the same time sends the data P(n) obtained in the coarse frame synchronization to the fractional frequency offset estimation module. The decimal frequency offset estimation uses the aforementioned estimation formula: $\widehat{\mathrm{\&epsiv;}}=-\frac{1}{2\mathrm{\&pi;}}\&angle;P\left(\mathrm{no}\right).$ When calculating the fractional frequency offset, the sampling divides the circle into 50 equal parts, compares the sine and cosine values of each angle with P(n), and takes the closest one as the phase of P(n).

After the fractional frequency offset estimation is completed, the fractional frequency offset of the data needs to be corrected. The correction process adopts an open-loop method. By designing a DDS frequency source, the data is multiplied by the corresponding frequency in the FPGA to achieve the purpose of compensating the fractional frequency offset.

${\mathrm{<span\; class="notranslate">\; r</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; e</span>}}^{\mathrm{<span\; class="notranslate">\; j</span>}\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;n\&epsiv;</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; e</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; j</span>}\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; no</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; \&epsiv;</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; e</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; j</span>}\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}{\mathrm{<span\; class="notranslate">\; no</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}\mathrm{<span\; class="notranslate">\; \&epsiv;</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; N</span>}}$

The above formula shows that the fractional frequency offset can be compensated by using the built-in digital frequency source, but because the exact starting point is not known, it is assumed that the starting point is the starting position obtained by coarse frame synchronization during data correction, which leads to the existence of e ^{-j2πn0ε /N} phase error. The impact of this phase error on the system is equal to the phase difference between the two carriers. It can be corrected together with the carrier phase error.

The flow chart of decimal frequency offset estimation and correction is shown in Figure 7. In the estimation process, we need to obtain the angle of P(n). We use the look-up table method and the Cordic kernel to obtain the two methods of removing the angle. The implementation method of frequency offset estimation and correction:

The estimation of integer frequency offset needs to use the frequency domain information of the sequence. Firstly, it is necessary to perform FFT transformation on 64 data after the starting point determined by coarse frame synchronization. This part of the circuit can call the OFDM signal demodulation module, and the main thing that needs to be completed is the interface problem. After the frequency domain sequence of the data is obtained, the data is sent to the integer frequency offset estimation unit for estimation, and the following estimation formula is used:

$\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; P</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; )</span>{<span\; class="notranslate">\; |</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}$

$\mathrm{<span\; class="notranslate">\; P</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}<span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}<span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}{<span\; class="notranslate">\; |</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$ ${\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{<span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; |</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

The flow chart of the implementation of integer frequency offset estimation and correction is shown in Figure 8.

在数据纠正时，同样使用数字频率源信号，原理与小数频偏纠正相同。The integer frequency offset estimation module first receives the frequency domain sequence of the data, uses the local sequence and the integer frequency offset estimation module to calculate the correlation energy, then performs a cyclic shift on the local sequence, and then calculates the correlation energy with the data frequency domain sequence until the cyclic shift reaches the original local sequence. The maximum point of the maximum correlation energy obtained in this process is the corresponding integer frequency offset, and the corresponding offset after the 32nd cycle is the negative normalized frequency offset

In the data correction, the digital frequency source signal is also used, and the principle is the same as that of the decimal frequency offset correction.

Fine synchronization: because the frame header positioning obtained by the frame header capture algorithm only falls into the plain area of the frame header correlation function, the frame header position has certain ambiguity. The idea of fine synchronization is to make the received sequence complexly correlated with the local reference sequence to obtain a prominent and sharp correlation peak. Another advantage of this is to detect whether there is a pseudo-frame header capture generated by periodic noise, thereby improving synchronization. accuracy. Storage capacity and precision processing: fine synchronization requires two 128-byte DSP memory modules, plus an A/D data writing module requires a total of 3 storage modules, so the storage of 4 modules in coarse synchronization Space has been able to meet the requirements of fine synchronization. In terms of precision processing, it is the same as coarse synchronization. The normalized correlation function used by fine frame synchronization is as follows:

$\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; P</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; E.</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; .</span>{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}}$

in $P\left(\mathrm{no}\right)=\underset{k=0}{\overset{N-1}{\mathrm{\&Sigma;}}}r(\mathrm{no}+k)\&Center\; Dot;{\mathrm{the\; s}}_k^{*},$ is the correlation energy of the received signal and the local reference sequence, $\mathrm{E.}\left(\mathrm{no}\right)=\underset{k=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{\left|r(\mathrm{no}+k)\right|}^2,$ In order to receive the energy of the signal in the correlation window, because correcting the frequency deviation affects only the phase of the signal, E(n) can be replaced by the R ₀ (n) sequence calculated during the coarse frame synchronization. to reduce system consumption. ${\mathrm{E.}}_{\mathrm{the\; s}}=\underset{k=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{\left|S_k\right|}^2,$ The energy for the reference sequence is a constant. Therefore, there are two main tasks in the fine frame synchronization stage, one is the calculation of P(n), and the other is to find the maximum value of M(n).

The flow chart of the implementation of the fine frame synchronization processing is shown in Fig. 9 .

The processing flow of fine frame synchronization is as follows:

1) Starting from the starting point defined by the coarse frame synchronization, the synchronization control module sends the subsequent 64 data and the energy value E(n) calculated by the coarse frame synchronization process of these 64 data to the fine frame synchronization processing module;

2) Fine frame synchronization sets a lower threshold during initialization. In the fine frame synchronization, the 64 received data are correlated with the local reference sequence for energy. Calculate the numerator and denominator of M(n) respectively, and then use the cross-multiplication method (avoiding the division operation) to compare the size of M(n) with the preset threshold. When M(n) is greater than the preset threshold value, replace the numerator and denominator of the preset threshold with the numerator and denominator of M(n) for subsequent comparison, and store corresponding position information at the same time;

3) After a period of 64 points of data transmission ends, the synchronization control module reserves a certain time margin for the fine frame synchronization module to process data. Then, the starting point defined by the coarse frame synchronization is moved back, and the two steps 1 and 2 are performed again until the last 64 bits of the starting point of the coarse frame synchronization are moved to ensure that the information sequence contains the first sync of the synchronization training sequence symbol;

4) At this time, the position information output by the fine frame synchronization module is the position where the sought M(n) is the largest.

The way to realize the best sampling point discrimination:

In order to solve the timing deviation of the best sampling point, the OFDM system adopts over-sampling technology. In the content discussed above, the sampling point refers to the sampling point sequence composed of the first point selected from every 8 points in the case of 8 times the sampling rate. When performing frequency offset correction, in addition to correcting the used sampling point sequence, it is also necessary to perform the same data correction on the remaining sampling point sequences.

In the case of fine frame synchronization to obtain a more accurate frame start point, use the formula:

$\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{<span\; class="notranslate">\; |</span>\underset{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}^{<span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; |</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

Among them, r(n+k) is the oversampled data, which is divided into 8 groups in sequence, and S _k is the local training sequence. After determining the fine frame sync position. For the 8 groups of sampling data, calculate the formula (3.24) with the fine frame positioning position as the starting point, and then calculate the formula (3.24) with the point before the fine frame positioning position as the starting point. After the calculation is completed, the maximum value of M(n) and the corresponding sampling points can be approximately considered as the best sampling points.

FFT module implementation: FFT is used at the receiving end, because the data received at the receiving end are all real numbers, so a certain method is used to convert real FFT into complex FFT for operation, saving nearly half of the original calculation. In fact, this method also completes the understanding of conjugate expansion. De-spreading, Carrier Inverse Mapping. Data anti-adjustment, anti-16QAM mapping, anti-interleaving.

Implementation of Viterbi decoding: Butterfly diagram is the core of Viterbi algorithm implementation, and the processing of butterfly diagram determines the efficiency of Viterbi algorithm. To implement Viterbi in DSP, we have used some methods and means to improve the quality of the program.

The method of generating fast table improves the speed of calculating branch metrics.

Make full use of the circular addressing function of C54X DSP, so that both Metrix and Transition_matrix are limited to 128 bytes of Circular Buffer, which saves and utilizes the memory as much as possible.

Make full use of DSP's hardware support for Viterbi algorithm. For example, the dual 16-bit computing capability of the accumulator (C16=1); the comparison, selection and storage unit (CSSU) specially designed for the Viterbi algorithm, etc., using these special hardware supports to accelerate the speed of decoding.

After the decoding is completed, we use the communication port (serial port) of the receiving terminal (PC, etc.) to receive the data.

The transmitting end:

1) The data stream is generated by the host computer and sent according to the requirements of the data segment in the frame format of the system.

2) DSP implementation of convolutional codes: convolutional codes are codes generated by passing the transmitted information sequence through a linear, finite-state shift register. Usually, the encoders of convolutional codes are composed of K levels (k bits per level) The shift register and n linear algebraic function generators (here is a modulo 2 adder), the binary data that needs to be encoded are serially input to the shift register, and k-bit data is shifted in each time. Each input sequence of k bits corresponds to an output sequence of n bits. Therefore, the coding efficiency of a convolutional code is defined as R _c =k/n. The parameter K is called the constraint length of the convolutional code, which indicates how many k-bit input sequences the current n-bit output sequence is related to, and is also an important parameter that determines the complexity of the encoding.

3) In our channel coding scheme, the convolutional codes of K=7, k=1, and n=2 (R _c =1/2), which are most commonly used in engineering, are selected. Decoding adopts Viterbi algorithm, taking δ=40>5K, hard decision. (7,1,2) the generator polynomial of convolution code is expressed as: POLYA=133, POLYB=171 with octal number

4) In fact, when we perform convolutional encoding, it is equivalent to interleaving the encoded data once. This problem can be solved by deinterleaving once before decoding. One thing to note is that the initial state of the general convolutional code is 0 at the beginning of encoding, and when the encoding is about to end, the tail of the bit stream will be followed by "Flushing" filled with 0, so that the encoding state returns to 0 . Therefore, the end of our information sequence must be artificially followed by 6-bit data 000000 to force the encoder to return to the 0 state at the end of a frame of data, so that the last backtracking during decoding can obtain the correct decoding result.

5) Interleaving. There are two ways of interleaving: Block Interleaving and Convolutional Interleaving. In the system, we choose block interleaving. The process of block interleaving is as follows: the m-order interleaver arranges the coded data into an array of m rows and n columns according to the row direction, and then reads out the data sequentially according to the column direction to complete the data interleaving. As shown in the interleaving schematic diagram in Figure 2, at the receiving end, the deinterleaver arranges the demodulated data into an array of m rows and n columns according to the column direction, and then reads the data sequentially according to the row direction to complete the deinterleaving of the data. Interleaving in DSP just changes the storage order of data, which is relatively simple to realize.

6) 16QAM mapping: In practical applications, we often use a baseband signal called multi-ary (such as 4-ary, 8-ary, 16-ary, etc.). The multi-ary digital modulation carrier parameter has M different values. The multi-ary digital modulation has two outstanding advantages over the binary digital modulation: one is that the multi-ary digital signal contains more information, which makes the frequency band utilization more efficient. High; second, it lasts for a long time at the same information rate, which can increase the energy of the symbol, thereby reducing the intersymbol interference caused by the channel characteristics. We use 16QAM modulation in multi-ary modulation, and the constellation diagram adopts a square constellation diagram. The relevant parameters are: minimum phase offset θ _min = 18°, minimum Euclidean distance $d_{\min }=0.63\sqrt{{\mathrm{E.}}_0}$ , the peak-average value is γ=1.8, and E ₀ is the average power.

7) Virtual carrier and conjugate extension: The addition of virtual carrier is done through a carrier map in DSP. The data in the carrier map only includes 0 and 1. The frequency band of OFDM is divided into several subcarriers. The carrier map There are several 0 and 1 data in it. 0 indicates that the corresponding subcarrier is not used to transmit data (that is, add 0), and 1 indicates that the corresponding subcarrier is used to transmit data. A total of 256 subcarriers are used in our OFDM system, 128 of which are virtual carriers, the front 112 and the latter 16 are virtual carriers, and only the middle 128 subcarriers are used to transmit data.

Carrier Map Rules

8) The essence of conjugate extension is to use the characteristics of Fourier transform. We know that the result of the Fourier transform of the real signal is that the amplitude spectrum is evenly symmetric, and the phase spectrum is oddly symmetric, which is special for real signals. OFDM uses IFFT to achieve modulation, which is to convert the frequency domain signal into a time domain signal. If we intentionally arrange the amplitude spectrum of the frequency domain signal as even symmetry and the phase spectrum as odd symmetry, the transformed time domain signal must be real signal. In this way, we can send the data by a single D/A without carrier modulation, and the frequency spectrum of the signal will not be changed. If OFDM adopts the way of I and Q channels, carrier modulation must be added to send the data. So the conjugate extension is to consciously complement the frequency domain to the frequency domain that conforms to the characteristics of the real signal.

。DSP中虚载波和共轭扩展的实现都是对存储器内容进行修改或者重新排序来实现的。9) The result of the joint action of the virtual carrier and conjugate extension is that the OFDM system transmits signals in a single channel. If the baseband spectrum width of the transmitted signal is W, the spectrum occupied by the actual transmitted signal under the action of the virtual carrier is

. The implementation of virtual carrier and conjugate expansion in DSP is realized by modifying or reordering the contents of memory.

10) Implementation of IFFT in DSP: In IFFT, TI’s IFFT algorithm based on radix 4 and radix 2 is used. The advantage of this is that the number of complex multiplications is reduced. Another good feature is that it can be used in fixed-point DSP chips. In , it is very simple to apply the method of shifting one bit to the right to complete the l/N operation, and prevent the possibility of overflow during the operation.

11) D/A data adjustment: Before data packaging, there is another work that must be done, which is to convert the original data into data suitable for D/A transmission.

Receiving end:

1). The transmission of the signal through the channel first passes through the coupler at the receiving end, and then carries out carrier shifting. This is a process of down-converting the signal corresponding to the sending end.

2). After the signal is down-converted, the analog signal is converted into a digital signal through A/D sampling.

3). Synchronization module: Synchronization is a very critical technology in OFDM system, but it is difficult to implement due to time reasons and the original synchronization algorithm, so we only use a simple energy-related synchronization method in the system to synchronize OFDM Speaking of which, we still have a lot of work to do. Our synchronization is divided into four steps, symbol coarse synchronization, fractional frequency estimation and correction, integer frequency estimation and correction, and fine synchronization. The entire synchronization process requires a good control of the clock. After completing the above synchronization process, we estimate the phase And correction, and best sampling point discrimination. After the synchronization is completed, we process the signal frame. We discard the cyclic prefix and synchronization header in the signal frame, and directly hand over the data segment in the data frame to the subsequent processing unit.

4). We adopt the method of module synchronization, that is, the DSP triggers the synchronization module to synchronize after a certain amount of data is sampled. For example, we trigger the synchronization module every 128 points of data, which reduces the consumption of saving the scene and context switching The instruction improves the efficiency of program operation.

5). Coarse synchronization: at the receiving end, when the receiver finds that the output value of M(n) remains greater than a certain threshold for a period of time, it considers that the frame header is correctly captured. Although from a certain point of view, this frame header capture function has a certain degree of ambiguity, but it is simple to implement, and can capture the frame header as quickly as possible, and then there is a fine synchronization module to give precise timing positions.

6). The processing of precision. The DSP we choose is C54X series, which is a 16-bit fixed-point DSP.

7).Fine synchronization: because the frame header positioning obtained by the frame header capture algorithm only falls into the plain area of the frame header correlation function, the frame header position has certain ambiguity. The fine timing adopted by this system is based on IEEE 802.11a The idea of double correlation to fine synchronization, that is, to make the received sequence complexly correlated with the local reference sequence, can obtain a prominent and sharp correlation peak. Another advantage of this is to detect whether there is a pseudo-frame header capture generated by periodic noise. Thereby improving the accuracy of synchronization.

8). Storage capacity and precision processing: fine synchronization requires two 128-byte DSP memory modules, plus an A/D data writing module requires a total of 3 storage modules, so 4 in coarse synchronization The storage space of the module has been able to meet the requirements of fine synchronization. In terms of precision processing, it is the same as coarse synchronization.

9). Realization of FFT module: FFT is used at the receiving end, because the data received at the receiving end are all real numbers, so a certain method is adopted to convert real number FFT into complex number FFT for operation, which saves nearly half of the original calculation amount. In fact, this method also completes the understanding of conjugate expansion.

10). Despreading, carrier inverse mapping, down-converting the frequency spectrum into a baseband signal;

11). Data anti-adjustment, anti-16QAM mapping, anti-interleaving. At the receiving end, the deinterleaver arranges the demodulated data into an array of m rows and n columns according to the column direction, and then reads the data sequentially according to the row direction to complete the deinterleaving of the data;

12). Implementation of Viterbi decoding: Butterfly diagram is the core of Viterbi algorithm implementation, and the processing of butterfly diagram determines the efficiency of Viterbi algorithm. To implement Viterbi in DSP, we have used some methods and means to improve the quality of the program.

The method of generating fast table improves the speed of calculating branch metrics.

Make full use of the circular addressing function of C54X DSP, so that both Metrix and Transition_matrix are limited to 128 bytes of Circular Buffer, which saves and utilizes the memory as much as possible. Make full use of DSP's hardware support for Viterbi algorithm. For example, the dual 16-bit computing capability of the accumulator (C16=1); the comparison, selection and storage unit (CSSU) specially designed for the Viterbi algorithm, etc., using these special hardware supports to accelerate the speed of decoding.

13). After the decoding is completed, use the communication port (serial port) of the receiving terminal (PC, etc.) to receive the data.

Claims (2)

1. A digital signal processing method of a power line communication system, characterized in that the digital signal processing method is divided into two parts, a transmitting end and a receiving end, and the steps of its processing method are: The transmitting end: 1) The upper computer generates a data stream and sends it according to the requirements of the data segment in the frame format of the system; 2) DSP implementation of product codes: Convolutional codes are codes generated by passing the transmitted information sequence through a linear, finite-state shift register. Usually, the encoders of convolutional codes are composed of K- level, k-bit shift registers per level. Bit register and n linear algebraic function generators-modulo 2 adders, the binary data that needs to be encoded is serially input to the shift register, and k- bit data is shifted in each time, and each k -bit input sequence corresponds to an n- bit output sequence , in the channel coding scheme, choose the most commonly used convolutional code in engineering with K = 7, k = 1, and n = 2R _c = 1/2, use the Viterbi algorithm for decoding, take δ = 40 > 5 K , Hard decision, the generator polynomial of (7,1,2) convolutional code is expressed as: POLYA =133, POLYB =171 with octal number; 3) Generally, the initial state of the convolutional code is 0 at the beginning of encoding, and when the encoding is about to end, the tail of the bit stream will be followed by "Flushing" filled with 0, so that the encoding state returns to 0, so the information sequence The tail must be artificially followed by 6-bit data 000000 to force the encoder to return to the 0 state at the end of a frame of data, so that the last backtracking during decoding can obtain the correct decoding result; 4) Interleaving: There are two types of interleaving: block interleaving and convolutional interleaving. In the system, block interleaving is selected. The process of block interleaving is: the m-order interleaver arranges the encoded data into an array of m rows and n columns in the row direction form, and then read the data sequentially in the direction of the column to complete the interleaving of the data; 5) 16QAM mapping: use 16QAM modulation in multi-ary modulation, the constellation diagram adopts a square constellation diagram, and the relevant parameters are: minimum phase offset θ _min = 18°, minimum Euclidean distance $d_{\min }=0.63\sqrt{{\mathrm{E.}}_0}$ , the peak-average value is γ = 1.8, E ₀ is the average power; 6) Virtual carrier and conjugate extension: The addition of virtual carrier is done through a carrier map in DSP. The data in the carrier map only includes 0 and 1. The frequency band of OFDM is divided into several subcarriers. The carrier map There are several 0 and 1 data, 0 means that the corresponding subcarrier is not used to transmit data, 1 means that the corresponding subcarrier is used to transmit data; in the OFDM system, a total of 256 subcarriers are used, of which 128 are virtual carriers , the first 112 subcarriers and the last 16 are virtual carriers, and only the middle 128 subcarriers are used to transmit data

Carrier map rules, using Fourier transform, the result of Fourier transform of the real signal is that the amplitude spectrum is evenly symmetrical, and the phase spectrum is oddly symmetrical. OFDM uses IFFT to realize modulation, which is to convert the frequency domain signal into a time domain signal. , the amplitude spectrum of the frequency domain signal is arranged as even symmetry, and the phase spectrum is arranged as odd symmetry, then the transformed time domain signal must be a real signal, and the data can be sent out by a single D/A without carrier modulation. And it will not change the spectrum of the signal; if OFDM adopts I and Q channels, it must be modulated by the carrier to send the data. Conjugate expansion is to consciously supplement the frequency domain to the frequency domain that conforms to the characteristics of the real signal; 7) The result of the joint action of the virtual carrier and conjugate extension is that the OFDM system transmits signals in a single channel. If the baseband spectrum width of the transmitted signal is W, the spectrum occupied by the actual transmitted signal under the action of the virtual carrier is $[\frac{112}{256}W,\frac{241}{256}W]$ , the implementation of virtual carrier and conjugate extension in DSP is realized by modifying or reordering the memory content; 8) Implementation of IFFT in DSP: In IFFT, TI’s IFFT algorithm based on radix 4 and radix 2 is used to reduce the number of complex multiplications. In the fixed-point DSP chip, the method of shifting one bit to the right is used to complete 1/ The operation of N, and prevent overflow during the operation; 9) D/A data adjustment: Before data packaging, convert the original data into data suitable for D/A transmission; Receiving end: 10) The transmission of the signal through the channel first passes through the coupler at the receiving end, and then the carrier is moved. This is a process of down-converting the signal corresponding to the sending end; 11) After the signal is down-converted, the analog signal is converted into a digital signal through A/D sampling; 12) Synchronization module: synchronization is divided into four steps, symbol coarse synchronization, decimal frequency estimation and correction, integer frequency estimation and correction, and fine synchronization; 13) Storage capacity and precision processing: fine synchronization needs two 128-byte DSP memory modules when performing calculations, plus an A/D data writing module requires a total of 3 storage modules, in terms of precision processing and coarse synchronization it's the same; 14) Implementation of FFT module: FFT is used at the receiving end, because the data received at the receiving end are all real numbers, so a certain method is adopted to make the real number FFT into complex number FFT for operation, which saves nearly half of the original calculation amount. Complete Understanding Conjugate Expansion; 15) Despreading, carrier inverse mapping, down-converting the frequency spectrum into a baseband signal; 16) Data anti-adjustment, anti-16QAM mapping, anti-interleaving, at the receiving end, the anti-interleaver arranges the demodulated data into an array form of m rows and n columns according to the column direction, and then reads the data sequentially according to the row direction, Complete data deinterleaving; 17) The realization of Viterbi decoding: butterfly graph is the core that Viterbi algorithm realizes, and the processing of butterfly graph has determined the efficiency of Viterbi algorithm, implements Viterbi in DSP, utilizes the method for producing fast table to improve the speed of calculation branch measure; Utilize The circular addressing function of C54X DSP limits both Metrix and Transition_matrix to 128-byte Circular Buffer, saving and utilizing memory to the greatest extent possible; 18) After the decoding is completed, use the communication serial port of the receiving terminal to receive the data. 2. the digital signal processing method of power line communication system according to claim 1, is characterized in that the step of its synchronization module processing method is: 1) Synchronization is divided into four steps, symbol coarse synchronization, decimal frequency estimation and correction, integer frequency estimation and correction, and fine synchronization; after completing the above synchronization process, perform phase estimation and correction, and determine the best sampling point; after successful synchronization Afterwards, the frame of the signal is processed, the cyclic prefix and the synchronization header part in the signal frame are discarded, the data segment part in the data frame is obtained directly, and the data segment part is handed over to the subsequent processing unit; 2) The method of module synchronization is adopted, that is, the DSP triggers the synchronization module to synchronize after a certain amount of data is sampled, and the synchronization module is triggered once every 128 points of data, which reduces the consumption of instructions for saving the scene and context switching, and improves the program. operating efficiency; 3) Coarse synchronization: at the receiving end, when the receiver finds that the output value of M(n) remains greater than a certain threshold for a period of time, the frame header is considered to be captured correctly, and the DSP we choose for precision processing is C54X series, 16bit fixed-point DSP; 4) Fine synchronization: The frame header positioning obtained by the frame header capture algorithm can only fall within the plain area of the frame header correlation function. The fine timing adopted is based on the implementation method of fine synchronization using double correlation in IEEE 802.11a, that is, let The receiving sequence is re-correlated with the local reference sequence to obtain a prominent and sharp correlation peak, and detect whether there is a pseudo-frame header capture caused by periodic noise, which improves the accuracy of synchronization.