CN116719005A

CN116719005A - Fixed-point data processing method and device based on FPGA and storage medium

Info

Publication number: CN116719005A
Application number: CN202311004223.0A
Authority: CN
Inventors: 施雪松; 周振超; 冯友怀; 陈涛
Original assignee: Nanjing Hawkeye Electronic Technology Co Ltd
Current assignee: Nanjing Hawkeye Electronic Technology Co Ltd
Priority date: 2023-08-10
Filing date: 2023-08-10
Publication date: 2023-09-08
Anticipated expiration: 2043-08-10
Also published as: CN116719005B

Abstract

The invention provides a fixed-point data processing method, a device and a storage medium based on an FPGA (field programmable gate array), which aim to combine two real sequences acquired based on two channels into a first complex signal, send the first complex signal into an FFT (fast Fourier transform) calculation module for corresponding Fourier transform processing after fixed-point processing, then determine the cascade number of butterfly factors, process target fixed-point data by adopting a butterfly processing method to obtain a second complex signal, adjust the bit width of the second complex signal under the condition of keeping the bit width of a decimal part unchanged, and finally carry out frequency domain recovery processing on the received second complex signal so as to recover the frequency domain results corresponding to the original two real sequences.

Description

Fixed-point data processing method and device based on FPGA and storage medium

Technical Field

The invention relates to the technical field of radar signal processing, in particular to a fixed-point data processing method and device based on an FPGA and a storage medium.

Background

FPGA (Field Programmable Gate Array ) has higher integration, greater logic implementation capability and better design flexibility than PAL, GAL, CPLD and other programmable devices. And with the rapid development of integrated circuit technology, the integration level of the FPGA is rapidly increased to tens of millions, and the FPGA provides rich on-chip resources, so that the design cost is reduced, and the design period is shortened. The design and development of complex digital signal processing systems have become a necessary trend by adopting FPGA chips with higher parallelism, higher speed and higher flexibility. The FFT operation is realized in the FPGA, so that the operation speed is required to be high, and the waste of resources is reduced as much as possible.

The actual application of the civil radar mainly uses a frequency modulation continuous wave mode to detect targets in the millimeter wave field, wherein an FMCW (Frequency Modulated Continuous Wave frequency modulation continuous wave) radar signal consists of innumerable frames, each frame consists of Nc chirp signals, and each chirp signal has Nr effective data points. In the radar signal processing process, each chirp signal is sampled by an ADC (Analog-to-Digital Converter) chip, and Nr valid data points are obtained. The Nr valid data points are fed into a distance dimension FFT computation module as a real sequence of Nr points to assist in subsequent resolution of the distance information of the target and to generate an input signal for doppler processing.

In radar receiving systems, multichannel data is typically collected simultaneously. On one hand, MIMO radar antenna array, obtain the phase difference among the channels and use for the space spectrum estimation; on the other hand, the signal to noise ratio of the subsequent signal processing can be improved by accumulating after collecting the data of a plurality of channels. However, the radar signal processing of the multichannel data needs to consume a large amount of resources, so that the application of the MIMO radar is restricted. Accordingly, there is a need to address the problems of the prior art.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention aims to provide a fixed-point data processing method, a fixed-point data processing device and a storage medium based on an FPGA, so as to solve the technical problems in the prior art.

The invention adopts the following technical scheme:

according to an aspect of the present invention, there is provided a fixed-point data processing method based on FPGA, the method comprising:

acquiring a first complex signal to be processed, and carrying out fixed-point processing on the first complex signal based on a preset rule to obtain fixed-point processed target fixed-point data; the first complex signal is a time domain signal, and the first complex signal is obtained based on two real sequences acquired by two channels;

Receiving the target fixed point data, determining the cascade number of butterfly factors, adopting a butterfly processing method to process the target fixed point data to obtain a second complex signal, and determining the overflow bit width of the integer part of the output sequence after the butterfly processing according to the cascade number of the butterfly factors under the condition that the bit width of the decimal part is kept unchanged so as to adjust the bit width of the output second complex signal;

and receiving the second complex signals, respectively performing positive-order operation and negative-order operation on the effective data point data in the second complex signals, acquiring a pair of effective data point data at corresponding positions from the effective data point data of the positive-order operation and the effective data point data of the negative-order operation, and performing corresponding operation processing to recover frequency domain results corresponding to two real sequences of the two channels.

Further, the first complex signal comprises a real part and an imaginary part, wherein the real part is derived from one of the two channels and the imaginary part is derived from the other of the two channels.

Further, the method for obtaining the first complex signal to be processed and performing fixed-point processing on the first complex signal based on a preset rule includes:

And designing the bit width of the target fixed-point data according to the maximum quantized bit width of the ADC chip so as to perform fixed-point processing on the first complex signal.

Further, the method of determining the number of cascades of butterfly factors includes:

judging whether the number of the effective data points in the single group of the first complex signals is the integral power of 2, if so, determining the cascade number of the butterfly factors according to the magnitude that the number of the input effective data points is the power of the integral power of 2;

otherwise, the number of the input effective data points is expanded to the nearest integer power of 2 by means of zero filling, and the size of the power in the expanded integer power of 2 is used for determining the cascade number of the butterfly factors.

Further, the method further comprises: and adding 1-bit significant digits as IP core internal protection to adjust the bit width of the output second complex signals.

Further, the receiving the second complex signal, and performing a positive-order operation and a negative-order operation on the valid data point data in the second complex signal, respectively, and obtaining a pair of valid data point data in a corresponding position from the valid data point data in the positive-order operation and the valid data point data in the negative-order operation, where the corresponding operation includes:

And storing the valid data point data of the positive bit sequence operation and the valid data point data of the negative bit sequence operation into a first storage unit and a second storage unit respectively, and simultaneously reading a pair of valid data point data from the first storage unit and the second storage unit one by one in a parallel mode to perform corresponding operation processing.

Further, when the valid data point data of the positive-order operation and the valid data point data of the negative-order operation are stored in the first storage unit and the second storage unit, respectively, the method further includes:

and splicing the real part and the imaginary part of the second complex signal to jointly adjust the bit width of the output buffer data.

Further, before the frequency domain result output, the method further comprises:

and adjusting the bit width of the output frequency domain result corresponding to each of the two real sequences of the two channels to be consistent with the bit width of the target fixed-point data by a truncation or shift method.

According to a further aspect of the present invention there is provided an FPGA-based fixed point data processing apparatus, the apparatus comprising:

the fixed-point processing module is used for acquiring a first complex signal to be processed, and carrying out fixed-point processing on the first complex signal based on a preset rule to obtain fixed-point processed target fixed-point data; the first complex signal is a time domain signal, and the first complex signal is obtained based on two real sequences acquired by two channels;

The FFT calculation module is used for receiving the target fixed point data, determining the cascade number of butterfly factors, adopting a butterfly processing method to process the target fixed point data to obtain a second complex signal, and determining the overflow bit width of the integer part of the output sequence after the butterfly processing according to the cascade number of the butterfly factors under the condition that the bit width of the decimal part is kept unchanged so as to adjust the bit width of the output second complex signal;

the frequency domain recovery module is used for receiving the second complex signal, respectively carrying out positive sequence operation and inverse sequence operation on the effective data point data in the second complex signal, acquiring a pair of effective data point data in corresponding positions from the effective data point data in the positive sequence operation and the effective data point data in the inverse sequence operation, and carrying out corresponding operation processing so as to recover the frequency domain results corresponding to the two real sequences of the two channels.

Further, the fixed-point processing module is further configured to design a bit width of the target fixed-point data according to a maximum quantization bit width of the ADC chip, so as to perform fixed-point processing on the first complex signal.

Further, the FFT computation module is further configured to determine whether the number of valid data points in the single set of first complex signals is an integer power of 2, and if so, determine the number of cascade butterfly factors according to the magnitude of the power in which the number of valid data points input is the integer power of 2;

Further, the frequency domain recovery module is further configured to store the valid data point data in the second complex signal into a first storage unit and a second storage unit in a positive order operation mode and a negative order operation mode, and simultaneously read a pair of valid data point data from the first storage unit and the second storage unit one by one in a parallel mode to perform corresponding operation processing.

Further, before the frequency domain result is output, the frequency domain recovery module is further configured to adjust, by a truncation or shift method, a bit width of the output frequency domain result corresponding to each of the two real sequences of the two channels to be consistent with a bit width of the target fixed point data.

According to another aspect of the present invention there is provided a computer readable storage medium storing a computer program loadable by a processor to perform any of the aforementioned FPGA-based fixed point data processing methods.

The invention has the advantages that: the method aims at combining two real sequences acquired based on two channels into a first complex signal, sending the first complex signal to an FFT (fast Fourier transform) calculation module for corresponding Fourier transform processing after the first complex signal is subjected to fixed-point processing, then determining the cascade number of butterfly factors, processing target fixed-point data by adopting a butterfly processing method to obtain a second complex signal, adjusting the bit width of the second complex signal under the condition that the bit width of a decimal part is kept unchanged, and finally carrying out frequency domain recovery processing on the received second complex signal to recover the frequency domain results corresponding to the original two real sequences.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a radar receiving system according to an embodiment of the present application.

Fig. 2 is a schematic diagram of a logic structure of a radar signal processing device according to the conventional technology.

Fig. 3 is a schematic logic structure diagram of a fixed-point data processing device based on FPGA according to an embodiment of the present application.

Fig. 4 shows a schematic logic structure of the frequency domain recovery module in fig. 3.

Fig. 5 is a schematic diagram of bit width variation of a specific exemplary data stream corresponding to fig. 3 and 4.

Fig. 6 is a flow chart of a fixed-point data processing method based on FPGA according to an embodiment of the present application.

Fig. 7A shows a schematic diagram of frequency domain result comparison of Sig1 for radar signal processing based on Matlab computation and FPGA-based fixed-point data processing, respectively.

Fig. 7B shows a schematic diagram of frequency domain result comparison of Sig2 for radar signal processing based on Matlab computation and FPGA-based fixed-point data processing, respectively.

Fig. 8A shows a quantization error case schematic diagram between the FPGA-based fixed-point data processing and the Sig1 frequency domain result calculated based on Matlab in fig. 7A.

Fig. 8B shows a quantization error case schematic diagram between the FPGA-based fixed-point data processing and the Sig2 frequency domain result calculated based on Matlab in fig. 7B.

Detailed Description

The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention, as well as the preferred embodiments thereof, together with the following detailed description of the invention, given by way of illustration only, together with the accompanying drawings.

In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

The invention will be further described in detail with reference to the drawings and detailed description below in order to make the objects, features and advantages of the invention more comprehensible.

Fig. 1 is a schematic diagram of a radar receiving system according to an embodiment of the present invention.

As shown in fig. 1, an embodiment of the present invention provides a radar receiving system, the radar receiving system 1000 includes: a plurality of receiving antennas, ADC chips, and radar signal processing means 300; the plurality of receiving antennas are used for receiving echo signals scattered by radar detection targets; the ADC chip is configured to collect the echo signal and perform corresponding digital-to-analog conversion processing, and input the signal subjected to the digital-to-analog conversion processing to the radar signal processing device 300 for processing.

In some embodiments, radar receiving system 1000 also includes a power module to provide the electrical power required by the various electronics.

The FPGA-based fixed-point data processing apparatus and the FPGA-based fixed-point data processing method in the embodiment of the present invention will be further described below with reference to the radar receiving system architecture shown in fig. 1.

As shown in fig. 2, taking the case of two-channel ADC acquisition as an example, the signal processing method of the conventional radar signal processing apparatus 300' currently is: and (3) for each channel ADC chip to acquire an input real sequence, directly calling 1 distance dimension complex FFT calculation module, wherein the real part is Nr effective data acquired by acquisition, and the imaginary part is set to zero to obtain a distance dimension FFT calculation result. And 2 distance dimension FFT calculation modules are called by the two channels, the real part of each distance dimension FFT calculation module is respectively sent into different channels for collecting data, the imaginary part is set to zero, and the like.

However, in reality, all the time domain signals received and acquired are real signals, and the ADC chip sampling is a process of discretizing the signals acquired by the corresponding channels. The conventional fourier transform method based on FPGA (Field Programmable Gate Array, field programmable logic array) is to send the acquired N-point real signal to the real part of the FFT computation module, and the imaginary part is set to zero. This approach, while capable of accurately computing the acquired signal spectrum information, uses only about half of the computing power of the FFT computation module because the imaginary part is zeroed out.

For the real sequence acquired by the multi-channel ADC chip, different channels are connected with respective FFT calculation modules, so that the resource waste is further caused. Meanwhile, as the number of channels increases, the waste of resources is multiplied. When the number of channels is relatively large, the resource waste is very large, and because the resources in the FPGA are relatively tense, the part uses more resources, which means that other functions need to be correspondingly cut, and finally the overall performance of the system is affected.

In view of the above, the present invention aims to reduce the resources required for radar signal processing and fully utilize the computing power of the FFT computation module, so as to avoid the waste of the computing power of the FFT computation module and the waste of resources.

Fig. 3 is a schematic logic structure diagram of a fixed-point data processing device based on FPGA according to an embodiment of the present invention, fig. 4 is a schematic logic structure diagram of a frequency domain recovery module in fig. 3, and fig. 5 is a schematic bit width variation diagram of a specific exemplary data stream corresponding to fig. 3 and 4.

As shown in fig. 3-5, an embodiment of the present invention provides an FPGA-based fixed-point data processing apparatus 400, which is applicable to the radar signal processing apparatus 300 in fig. 1, and includes:

the fixed-point processing module 410 is configured to obtain a first complex signal to be processed, and perform fixed-point processing on the first complex signal based on a preset rule, so as to obtain fixed-point processed target fixed-point data; the first complex signal is a time domain signal, and the first complex signal is obtained based on two real sequences acquired by two channels;

the FFT calculation module 420 is configured to receive the target fixed-point data, determine the number of cascade connections of butterfly factors, and process the target fixed-point data by using a butterfly processing method to obtain a second complex signal, and determine, according to the number of cascade connections of the butterfly factors, an overflow bit width of an integer part of the output sequence after the butterfly processing, so as to adjust a bit width of the output second complex signal, where the bit width of the fraction part remains unchanged;

The frequency domain recovery module 430 is configured to receive the second complex signal, perform a positive-order operation and a negative-order operation on valid data point data in the second complex signal, and obtain a pair of valid data point data in corresponding positions from the valid data point data in the positive-order operation and the valid data point data in the negative-order operation, and perform corresponding operation processing to recover frequency domain results corresponding to two real sequences of the two channels.

The technical scheme provided by the embodiment of the invention aims to combine two real sequences acquired based on two channels into a first complex signal, send the first complex signal into an FFT calculation module for corresponding Fourier transform processing after the first complex signal is subjected to fixed-point processing, then determine the cascade number of butterfly factors, process the target fixed-point data by adopting a butterfly processing method to obtain a second complex signal, adjust the bit width of the second complex signal under the condition that the bit width of a decimal part is kept unchanged, and finally carry out frequency domain recovery processing on the received second complex signal so as to recover the frequency domain results corresponding to the original two real sequences. Therefore, compared with the common technology, the method can fully utilize the computing capability of the FFT computing module, save resources and realize no extra operation resource waste under the condition of no data overflow.

For the sake of clear and concise explanation of the technical solution of the embodiment of the present invention, the case of two channel ADC acquisition is discussed at present, and in the radar signal processing system, two channel ADC acquisition acquires two sets of real signals Sig1 and Sig2, which may be mutually independent real sequences. Specifically, the two sets of real signals Sig1 and Sig2 are combined into a first complex signalz(n) Input to FFT computation module 420 for processing; in particular, the first complex signalz(n) Comprising a real part and an imaginary part, the real part originating from one of the two channels and the imaginary part originating from the other of the two channels. For example, zn_re (the real part of the first complex signal) is derived from sig1_time_re and zn_im (the imaginary part of the first complex signal) is derived from sig2_time_re.

Wherein the first complex signal is represented by:

i.e. two real sequences acquired based on two channels are respectively the real part and the imaginary part of the first complex signal. First complex signalz(n) Obtaining a second complex signal in a corresponding complex form after being subjected to fourier transform processing by the FFT computation block 420Z(k). In the frequency domain recovery module 430, the real part conjugate symmetry of the real signal fourier transform result in the frequency domain is utilized, the real part information and the imaginary part information of the Sig1 and Sig2 signals collected by the original two channels in the frequency domain are reversely deduced by utilizing the characteristic of the imaginary part conjugate antisymmetry, and the analysis antisymmetric algorithm can be realized on the basis of the FPGA platform and finally is applied to the product.

Since the echo signal sampled by the ADC chip is a discrete period sequencex(n) Thus, toThe frequency domain analysis is performed by performing discrete fourier transform (Discrete Fourier Transformation, DFT), the formula of the DFT algorithm is shown in formula 1 (note: formula 1 is a general expression, wherein,x(n) Representing the time-domain signal,X(K) Representing the frequency domain signal, so herex(n) Can be used to represent xn, yn, or zn in fig. 3).

Formula 1.

Discrete periodic sequences can be obtained by DFT conversion of 1x(n) Corresponding frequency domain dataX(k). The fourier transform is a linear transform, and the frequency domain data may be obtained by an Inverse Discrete Fourier Transform (IDFT) represented by equation 2X(k) Recovering to obtain time domain datax(n)。

Formula 2.

Twiddle factor shown in figure 1W _N Is divided into a plurality of circles by the physical meaning ofNAnd (3) rotating the parts, wherein the phase factor obtained by rotation has symmetry and periodicity as shown in a formula 3.

Formula 3.

By utilizing symmetry and periodicity of the phase factors, the DFT algorithm is optimized, a fast Fourier transform (Fast Fourier Transform, FFT) algorithm can be formed, the FFT is an optimization algorithm of DFT, and physical meanings of the FFT and the DFT are consistent. If the sequence before FFT conversionx(n) Only the real part and the imaginary part are zero, the phase factor is substituted, as shown in equation 2, and the kth component after FFT conversion can be expressed as:

Formula 4.

Because ofx(n) The imaginary part is zero, soSo the first in the frequency domainN-kThe individual components can be expressed as:

formula 5.

Thus, the frequency domain data relationship can be written as:

or (b)

Formula 6.

From the above, in the result of Fourier transform of real signal, the real part is relative to [ ]N-1)/2 is symmetrical, and the imaginary part is relative to #N-1)/2 is antisymmetric. So that the complex sequence of the first complex signalWherein, the method comprises the steps of, wherein,x(n) The acquired real signal is acquired for ADC _ Sig1 shown in figure 3,y(n) The acquired real signal is acquired for adc_sig2 shown in fig. 3. Alonex(n) The result of the fourier transform of the real sequence isX(k) Alone, aloney(n) The result of the fourier transform of the real sequence isY(k) Based on the homogeneity and additivity of the fourier transform, then:

formula 7.

Formula 7 can also be written as:

formula 8.

Using the frequency domain data relationship in equation 6kThe first half of the component represents the second half, i.e., the result is:

formula 9.

Combining formula 8 and formula 9, the final result is:

formula 10.

Thus, the first complex signalz(n) After being processed by the FFT calculation module, the corresponding second complex signal is obtainedZ(k)。

It should be appreciated that in embodiments of the present invention, the second complex signal includes a real part and an imaginary part, and the number of all valid data points in the second complex signal is equal to the number of all valid data points in the first complex signal.

The independent solution can be obtained by the back-pushing of 10x(n) Frequency domain result corresponding to real sequenceX(k) And aloney(n) Frequency domain result corresponding to real sequenceY(k)。

And the analysis and back-pushing algorithm can be realized on the basis of an FPGA platform, and finally, the application is formed in the product.

In the embodiment of the invention, in order to realize no extra operation resource waste under the condition of no data overflow, the embodiment of the invention also carries out the fixed-point processing on the real sequences acquired based on the two channels when the real sequences are combined into the first complex signals.

Illustratively, when Matlab software generates test data, floating point data is typically required to be pinned to ensure that the FPGA is able to read normally, where the fixed point data occupies less memory space than the floating point data and the fixed point data occupies less computing resources than the floating point data.

In addition, since various algorithms based on FPGA are built by hardware circuits, in order to ensure the usability of the subsequent frequency domain recovery module 430, and in order to improve the suitability of the subsequent various ADC chips, for example, an ADC chip with valid data bits of 10 bits or an ADC chip with valid data bits of 12 bits are adapted. In the embodiment of the invention, the bit width of the target fixed-point data is designed according to the maximum quantized bit width of the ADC chip so as to perform fixed-point processing on the first complex signal. Illustratively, the maximum quantization bit width of current ADC chips is 16 bits, which 16 bits are typically the most significant bits seen on the market. If it is less than 16 bits, it can also be adapted to 16 bits by complementing "0" or expanding.

Illustratively, the original is input via two channelsxn、ynThe time domain data is fixed-point data of a target fixed-point data of 16-bit effective symbol number, and the total bit width is 16 bits, wherein, the symbol bit is 1 bit, the decimal bit is 15 bits, and the symbol bit is recorded as 16Q15. I.e. using 1/2 ¹⁵ To represent the quantization accuracy of the decimal places in the first complex signal, so as to reduce the waste of computing resources as much as possible while guaranteeing the quantization accuracy.

[ butterfly factor ]: if the input is two numbers, A and B, then the corresponding two outputs areAnd->Wherein->. Here A, B andk ₁ all complex numbers and all multiplications or additions and subtractions are based on complex numbers. When (when)k ₁ At maximum 1, the two outputs representing the current most extreme case are A+B and A-B. When (when)k ₁ Taking the minimum value-1, the two outputs representing the current most extreme case are A-B and A+B.

Illustratively, assume that the original time domain input data is 16Q15 for the fixed-point case, and assume here that x is considered to be combined into the first complex signaln)、y(n) The signals are 1024 effective data points, the number of effective data points after the localization is 1024, when 1024 (2 ¹⁰ ) When FFT calculation is carried out on each effective data point in the FFT calculation module, 10 stages of butterflies need to be called inside the effective data point Form factor, and when 8 effective data points are input to carry out FFT calculation in FFT calculation module, 3-level butterfly factor is required to be called inside; when 16 valid data points are input to perform FFT calculation in the FFT calculation module, a 4-level butterfly factor is required to be called inside the FFT calculation module. That is, in the embodiment of the present invention, it is determined whether the number of valid data points in the first complex signal is an integer power of 2, and if so, the number of levels of the butterfly factors to be called is determined directly according to the magnitude of the power in the integer power of 2 (or the sequence length of the corresponding binary number) of the number of valid data points to be input. In addition, if 1000 valid data points are input, the number of the valid data points is greater than 2 ⁹ And less than 2 ¹⁰ So that only FFT calculations corresponding to 1024 valid data points can be performed (10-level butterfly factor operations are required), and the 24 valid data points that are not sufficient must be padded by zero padding (e.g., an additional zero padding module is provided). Therefore, the number of effective data points entering the FFT computation module for the fixed-point butterfly processing must be the number of powers of 2.

Specifically, in the case of reserving the bit width of the fractional part, determining the overflow bit width of the integer part of the output sequence after the butterfly processing according to the cascade number of the butterfly factors, so as to adjust the bit width of the output second complex signal.

Illustratively, in the embodiment of the present invention, the bit width of the target fixed-point data is set to 16Q15, based on the characteristics of the 10-level butterfly factor, after the 10-level butterfly factor operation is performed, the bit width of the integer part thereof is increased by 10 bits, and all the 10 bits which are increased by the integer bits, and the bit width precision of the fractional part is reserved, so that the final effective output data (second complex signal) localization case is 26Q15.

For example, binary "11" and binary "10" are added to obtain a binary result of "101", at which time the corresponding bit width is increased by 1 bit. If, in the most extreme case, the binary "11" and the binary "11" are added, the binary result is "110", at which point the corresponding bit width is increased by 1 bit. Thus, when two binary decimal places are input for addition, in the most extreme case, the bit width is expanded by one bit at most, which can correctly represent the calculation result after addition, and no data overflow occurs. Since the butterfly operation of each stage corresponds to an addition (e.g., a+b) and a subtraction (e.g., a-B), if each stage corresponds to that extreme case, the bit width of the integer corresponding to the calculated result is increased by 10 bits after the final 10-stage butterfly operation. Therefore, in the case where the bit width (quantization accuracy) based on decimal places remains unchanged, it is generally calculated for the addition of a and B, both of which are decimal places, whose carry bits must be carried toward integer digits, so that the carry bits after invoking the 10-level butterfly operation in this embodiment are all in integer digits, the bit width of which is increased by 10 bits accordingly.

In addition, in order to ensure the stability of the IP core, in the embodiment of the present invention, 1 significant digit is further added as an IP core internal protection, so as to adjust the bit width of the output second complex signal, thereby ensuring that the whole significant data bit will not overflow. Thus, a pinpointed form of 27Q15 is finally formed.

Since the final recovery calculation shown in equation 10 requires the frequency domain recovery module 430 to perform corresponding addition and subtraction processing on the valid data point data of the positive bit sequence operation and the valid data point data of the negative bit sequence operation, the valid data point data of the second complex signal (including the real part zk_re and the imaginary part zk_im) obtained after processing by the FFT calculation module 420 needs to be separately stored after performing the positive bit sequence operation and the negative bit sequence operation, so as to obtain a pair of valid data point data of the corresponding position and perform corresponding operation processing.

In order to be able to recover the frequency domain results corresponding to the real sequences of the two channels to be recovered one by one continuously under the condition of no blockage. The frequency domain recovery module 430 is further configured to store the valid data point data in the second complex signal into a first storage unit (buf 1) and a second storage unit (buf 2) in a positive order operation and a negative order operation respectively, and simultaneously read a pair of valid data point data from the first storage unit (buf 1) and the second storage unit (buf 2) one by one in a parallel manner to perform corresponding operation processing. Compared with the method that the data of the corresponding position is firstly stored and then is called to carry out corresponding addition and subtraction operation, the time is more efficient.

Specifically, as shown in fig. 4, the frequency domain recovery module 430 includes a first storage unit (buf 1), a second storage unit (buf 2), a control unit, and an operation unit; the control unit is used for controlling the effective data point data of the positive order operation and the effective data point data of the negative order operation to be respectively stored into the first storage unit (buf 1) and the second storage unit (buf 2); the operation unit is used for simultaneously reading a pair of valid data point data from the first storage unit (buf 1) and the second storage unit (buf 2) one by one in a parallel mode to perform corresponding operation processing.

In order to accelerate the data reading speed of each storage unit and to relieve the pressure of the server of the radar signal processing device, in the embodiment of the invention, the first storage unit (buf 1) and the second storage unit (buf 2) are both cache units.

The control unit is used for controlling the sequence of a first write address (waddr 1) of the first storage unit (buf 1) and a second write address (waddr 2) of the second storage unit (buf 2), and sequentially caching effective data points in the second complex signals to the first storage unit (buf 1) according to the sequence of forward increment of the write addresses; and sequentially caching the valid data points in the second complex signals to the second storage unit (buf 2) according to the reverse descending order of the write addresses. After the buffer is completed, the buffer can be read out sequentially, so that the two read signals zk_re1, zk_im1, zk_re2 and zk_im2 respectively perform corresponding addition and subtraction operations in a mode shown in a formula 10, and the recovered output results can be formed one by one.

Because the data in the FPGA is faced with the problem of the data bit width becoming large during the multiplication and addition process, however, the hardware resources are limited, so the final bit width of the data needs to be designed, which faces the problems of the selection of the bit width and how to truncate the bits.

Further, before the frequency domain result is output, the frequency domain recovery module 430 is further configured to adjust, by a truncation or shifting method, a bit width of the output frequency domain result corresponding to each of the two real sequences of the two channels to be consistent with a bit width of the target fixed point data, so that a truncation error caused by a reduction of quantization bits is not caused.

According to yet another aspect of the present invention, there is provided a fixed-point data processing method based on an FPGA.

Fig. 6 is a flow chart of a fixed-point data processing method based on FPGA according to an embodiment of the present invention.

As shown in fig. 6, the fixed-point data processing method based on FPGA is applicable to the radar signal processing device 300 in fig. 1, and the method includes the following steps:

step S10, a first complex signal to be processed is obtained, and fixed-point processing is carried out on the first complex signal based on a preset rule, so that fixed-point processed target fixed-point data is obtained; the first complex signal is a time domain signal, and the first complex signal is obtained based on two real sequences acquired by two channels;

Step S20, receiving the target fixed point data, determining the cascade number of butterfly factors, adopting a butterfly processing method to process the target fixed point data to obtain a second complex signal, and determining the overflow bit width of the integer part of the output sequence after the butterfly processing according to the cascade number of the butterfly factors under the condition that the bit width of the decimal part is kept unchanged so as to adjust the bit width of the output second complex signal;

step S30, receiving the second complex signals, performing positive sequence operation and negative sequence operation on the effective data point data in the second complex signals respectively, acquiring a pair of effective data point data in corresponding positions from the effective data point data in the positive sequence operation and the effective data point data in the negative sequence operation, and performing corresponding operation processing to recover frequency domain results corresponding to two real sequences of the two channels respectively.

The steps S10 to S30 will be specifically described below with reference to fig. 3 to 5.

In step S10, the radar signal processing device 300 acquires a first complex signal to be processed, and performs a fixed-point processing on the first complex signal based on a preset rule, so as to obtain target fixed-point data after the fixed-point processing. The received acquired time domain signals in the radar signal receiving system are real signals, and two real sequences acquired based on two channels are input into the radar signal processing device 300, wherein the first complex signal comprises a real part and an imaginary part, wherein the real part is derived from one of the two channels, and the imaginary part is derived from the other of the two channels. The real part and the imaginary part are real signals acquired and converted by the ADC chip.

Furthermore, since the various algorithms based on the FPGA are all built by hardware circuits, in order to ensure the availability of the migration of the frequency domain recovery module 430 in the subsequent radar signal processing device 300, in this embodiment, the original input is via two channelsxn、ynThe time domain data is fixed-point data of a target fixed-point data of 16-bit effective symbol number, and the total bit width is 16 bits, wherein, the symbol bit is 1 bit, the decimal bit is 15 bits, and the symbol bit is recorded as 16Q15. I.e. using 1/2 ¹⁵ Representing the quantization accuracy of the decimal places in the first complex signal to minimize the waste of computing resources while guaranteeing quantization accuracy.

In step S20, the target fixed-point data is received, the cascade number of butterfly factors is determined based on the sequence length of the valid data points of the first complex signal, the target fixed-point data is processed by adopting a butterfly processing method to obtain a second complex signal, and under the condition that the bit width of the fractional part is kept unchanged, the overflow bit width of the integer part of the output sequence after the butterfly processing is determined according to the cascade number of the butterfly factors, so as to adjust the bit width of the output second complex signal.

[ butterfly factor ]: if the input is two numbers, A and B, then the corresponding two outputs areAndwherein->. Here A, B andk ₁ all complex numbers and all multiplications or additions and subtractions are based on complex numbers. When (when)k ₁ At maximum 1, the two outputs representing the current most extreme case are A+B and A-B. When (when)k ₁ Taking the minimum value-1, the two outputs representing the current most extreme case are A-B and A+B.

Illustratively, assume that the original time domain input data is 16Q15 for the fixed-point case, and assume here that x is considered to be combined into the first complex signaln)、y(n) The signals are 1024 effective data points, the number of effective data points after the localization is 1024, when 1024 (2 ¹⁰ ) When the FFT calculation is carried out on the effective data points, 10-level butterfly factors are required to be called in the effective data points, and when the FFT calculation is carried out on the effective data points which are input into the FFT calculation module, 3-level butterfly factors are required to be called in the effective data points; when 16 valid data points are input to perform FFT calculation in the FFT calculation module, a 4-level butterfly factor is required to be called inside the FFT calculation module. That is, in the embodiment of the present invention, it is determined whether the number of valid data points in the first complex signal is an integer power of 2, if so, the number of levels of the butterfly factors to be called is determined directly according to the magnitude of the power in the integer power of 2 (or the sequence length of the corresponding binary number) of the number of the valid data points to be input. In addition, if 1000 valid data points are input, the number of the valid data points is greater than 2 ⁹ Less than 2 ¹⁰ So that only FFT calculations corresponding to 1024 valid data points can be performed (10-level butterfly factor operations are required), and the 24 valid data points that are not sufficient must be padded by zero padding (e.g., an additional zero padding module is provided). Therefore, the number of valid data points for performing FFT computation must be the number of integer powers of 2.

Illustratively, in the embodiment of the present invention, the bit width of the target bit-mapped data is set to be 16Q15, based on the characteristics of the 10-level butterfly factor, after the 10-level butterfly factor operation is performed, the bit width of the integer part of the target bit-mapped data is increased by 10 bits, and all the 10 bits increased by the integer bit are increased, and the bit width precision of the fractional part is reserved, so that the final effective output data (the second complex signal) is positioned to be 26Q15.

For example, binary "11" and binary "10" are added to obtain a binary result of "101", at which time the corresponding bit width is increased by 1 bit. If, in the most extreme case, the binary "11" and the binary "11" are added, the binary result is "110", at which point the corresponding bit width is increased by 1 bit. Thus, when two decimal places of binary are added, in the most extreme case, the bit width is expanded by one bit at most, which correctly represents the calculation result after addition, and no data overflow occurs. Since the butterfly factor operation of each stage corresponds to an addition (e.g., a+b) and a subtraction (e.g., a-B), if each stage corresponds to that extreme case, after the final use of the butterfly operation of 10 stages, the bit width of the integer corresponding to the obtained calculation result is increased by 10 bits. Therefore, in the case where the bit width (quantization accuracy) based on decimal places remains unchanged, it is generally calculated for the addition of a and B, both of which are decimal places, whose carry bits must be carried toward integer digits, so that the carry bits after invoking the 10-level butterfly operation in this embodiment are all in integer digits, the bit width of which is increased by 10 bits accordingly.

In step S30, in order to recover the frequency domain results corresponding to the two real sequences of the two channels, the frequency domain recovery module receives the second complex signal, and performs a positive-order operation and an inverse-order operation on the valid data point data in the second complex signal, so as to obtain a pair of valid data point data at corresponding positions from the valid data point data operated by the positive-order operation and the valid data point data operated by the inverse-order operation, and perform corresponding operation processing, which uses the fourier transform result of the real signal to be conjugate symmetric in the real part of the frequency domain, and the imaginary part conjugate antisymmetry characteristic to reversely solve the real part and imaginary part information corresponding to the Sig1 and Sig2 signals acquired by the original two channels in the frequency domain.

The fixed point data processing method based on the FPGA provided by the embodiment of the invention aims at combining two real sequences acquired based on two channels into a first complex signal, performing fixed point processing, then sending the first complex signal into an FFT computing module for corresponding Fourier transform processing, and then utilizing the real part conjugate symmetry of the Fourier transform result of the real signal in a frequency domain and the imaginary part conjugate antisymmetry characteristic to reversely deduce the real part information and the imaginary part information of the Sig1 and Sig2 signals acquired by the original two channels in the frequency domain so as to recover the frequency domain results corresponding to the two real sequences respectively. Therefore, compared with the common technology, the method can fully utilize the computing capability of the FFT computing module, and can realize no extra computing resource waste under the condition of no data overflow.

Since the final recovery calculation shown in equation 10 requires the frequency domain recovery module to perform corresponding addition and subtraction processing on the valid data point data of the positive bit sequence operation and the valid data point data of the negative bit sequence operation, the valid data point data of the second complex signal (including the real part zk_re and the imaginary part zk_im) obtained after the FFT calculation processing needs to be separately stored after the positive bit sequence operation and the negative bit sequence operation, so as to obtain a pair of valid data point data of the corresponding position to perform corresponding operation processing. The method therefore further comprises: and storing the valid data point data of the positive bit sequence operation and the valid data point data of the negative bit sequence operation into a first storage unit and a second storage unit respectively, and simultaneously reading a pair of valid data point data from the first storage unit and the second storage unit one by one in a parallel mode to perform corresponding operation processing. Compared with the method that the data of the corresponding position is firstly stored and then is called to carry out corresponding addition and subtraction operation, the time is more efficient.

In order to accelerate the data reading speed of each storage unit and to relieve the pressure of the radar signal processing server, in the embodiment of the invention, the first storage unit and the second storage unit are both cache units. Hereinafter referred to as buf1 and buf2, respectively.

Further, the method for obtaining the first complex signal to be processed and performing fixed-point processing on the first complex signal based on a preset rule includes: and designing the bit width of the target fixed-point data according to the maximum quantized bit width of the ADC chip so as to perform fixed-point processing on the first complex signal. Wherein the fixed point data occupies less memory space than the floating point data and the fixed point data occupies less computing resources than the floating point data.

In addition, since various algorithms based on FPGA are built by hardware circuits, in order to ensure the usability of the subsequent frequency domain recovery module 430, and in order to improve the suitability of the subsequent various ADC chips, for example, an ADC chip with valid data bits of 10 bits or an ADC chip with valid data bits of 12 bits are adapted. In the embodiment of the invention, the bit width of the target fixed-point data is designed according to the maximum quantized bit width of the ADC chip so as to perform fixed-point processing on the first complex signal. If it is less than 16 bits, it can also be adapted to the ADC chip currently having the largest quantization bit width by complementing "0" or expanding.

Illustratively, the original is input via two channels xn、ynThe time domain data is fixed-point data of a target fixed-point data of 16-bit effective symbol number, and the total bit width is 16 bits, wherein, the symbol bit is 1 bit, the decimal bit is 15 bits, and the symbol bit is recorded as 16Q15. I.e. using 1/2 ¹⁵ To represent the quantization accuracy of the decimal places in the first complex signal, so as to reduce the waste of computing resources as much as possible while guaranteeing the quantization accuracy.

To ensure the stability of the IP core, the method further comprises: 1-bit valid digit is added as IP core internal protection, so that the whole valid data bit is further ensured not to overflow. Thus, a pinpointed form of 27Q15 is finally formed.

In order to be able to recover the frequency domain results corresponding to the real sequences of the two channels to be recovered one by one continuously under the condition of no blockage. The receiving the second complex signal, and performing a positive-order operation and a negative-order operation on the valid data point data in the second complex signal, respectively, and obtaining a pair of valid data point data at corresponding positions from the valid data point data of the positive-order operation and the valid data point data of the negative-order operation, and performing corresponding operation processing includes:

Further, when the valid data point data of the positive-order operation and the valid data point data of the negative-order operation are stored in the first storage unit and the second storage unit, respectively, the method further includes: and receiving the second complex signal, and splicing the real part and the imaginary part of the second complex signal to jointly adjust the bit width of the buffer output data.

The data in the FPGA is faced with the problem of the data bit width becoming large during the multiplication and addition process, however, the hardware resources are limited, so the final bit width of the data needs to be designed, which faces the problems of the selection of the bit width and how to truncate the bits.

Further, before the frequency domain result output, the method further comprises: and adjusting the bit width of the output frequency domain result corresponding to each of the two real sequences of the two channels to be consistent with the bit width of the target fixed point data by a truncation or shift method, so that bit truncation errors caused by reduction of quantization bits are avoided.

In summary, by adopting the technical scheme provided by the embodiment of the invention, a new N-point sequence is constructed by respectively putting the real part and the imaginary part of a new N-point complex sequence into two paths of N-point real sequences x (N) and y (N) . After the N-point complex sequence passes through a complex FFT calculation module, the frequency domain result obtained after FFT processing is processed to recover and obtain FFT results X (k) and Y (k) corresponding to the original two paths of N-point real sequences X (N) and Y (N).

Fig. 7A shows a schematic diagram of comparing frequency domain results of Sig1 based on Matlab calculation and FPGA-based fixed point data processing, respectively, fig. 7B shows a schematic diagram of comparing frequency domain results of Sig2 based on Matlab calculation and FPGA-based fixed point data processing, respectively, fig. 8A shows a schematic diagram of quantization error between frequency domain results of Sig1 based on FPGA-based fixed point data processing and Matlab calculation in fig. 7A, and fig. 8B shows a schematic diagram of quantization error between frequency domain results of Sig2 based on FPGA-based fixed point data processing and Matlab calculation in fig. 7B.

7A-7B, the same data are operated on the Matlab software to keep the precision of each effective point data, and an output result is obtained; and then, reading a result calculated by fixed-point data processing based on the FPGA by using Matlab software, converting the fixed-point data into floating-point data after reading, comparing an output result calculated by the Matlab software with an output result obtained by fixed-point data processing based on the FPGA, and solving an error between the output result and the output result, wherein the result shows that the quantization error after the fixed-point data processing based on the FPGA is basically about +/-0.03 as shown in fig. 8A-8B.

Compared with the conventional technical scheme and the technical scheme evaluation of the application, the two methods are comprehensively realized on the FPGA under the condition of the same x (n) and y (n) data input, and compared with the method of directly calling an FFT calculation module to carry out FFT conversion by one channel of the conventional technical scheme, the optimized FFT conversion method of the technical scheme of the application has the advantages that the calculation capacity of complex FFT cores is fully utilized, in addition, in the completion of FFT calculation of the same effective data points, the Slice resources and the Bram resources are saved by nearly half, and the system performance is integrally improved.

Table 1 two methods different dimension assessment

According to another aspect of the present application, the embodiments further provide a computer readable storage medium having a computer program stored therein, which when executed by a processor, implements the FPGA-based fixed-point data processing method of any of the above-described embodiments.

The specific limitation and implementation of the above steps may refer to the steps and methods of the embodiments of the fixed point data processing method based on FPGA, and are not described herein. Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.

The method, the device and the storage medium for processing fixed-point data based on the FPGA provided by the embodiment of the invention are described in detail, and specific examples are applied to the description of the principle and the implementation mode of the invention, and the description of the above embodiments is only used for helping to understand the technical scheme and the core idea of the invention; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A fixed point data processing method based on an FPGA, the method comprising:

2. The method for FPGA-based fixed-point data processing as claimed in claim 1,

the first complex signal includes a real part and an imaginary part, wherein the real part is derived from one of the two channels and the imaginary part is derived from the other of the two channels.

3. The FPGA-based fixed-point data processing method as claimed in claim 1, wherein the acquiring a first complex signal to be processed and performing the fixed-point processing on the first complex signal based on a preset rule includes:

4. The FPGA-based fixed point data processing method of claim 1, wherein the method of determining the number of cascades of butterfly factors comprises:

5. The FPGA-based fixed point data processing method of claim 4, further comprising:

and adding 1-bit significant digits as IP core internal protection to adjust the bit width of the output second complex signals.

6. The FPGA-based fixed-point data processing method of claim 1, wherein the receiving the second complex signal and performing a positive-order operation and a negative-order operation on valid data point data in the second complex signal, respectively, and obtaining a pair of valid data point data at a corresponding position from the valid data point data of the positive-order operation and from the valid data point data of the negative-order operation, performing a corresponding operation process includes:

7. The FPGA-based fixed point data processing method of claim 6, wherein when storing valid data point data for a positive bit order operation and valid data point data for a negative bit order operation into the first memory cell and the second memory cell, respectively, the method further comprises:

8. The FPGA-based fixed point data processing method of claim 7, wherein prior to the frequency domain result output, the method further comprises:

9. A fixed point data processing apparatus based on an FPGA, the apparatus comprising:

10. The FPGA-based fixed point data processing apparatus of claim 9,

11. The FPGA-based fixed point data processing apparatus of claim 9,

the fixed-point processing module is also used for designing the bit width of the target fixed-point data according to the maximum quantized bit width of the ADC chip so as to perform fixed-point processing on the first complex signal.

12. The FPGA-based fixed point data processing apparatus of claim 9,

the FFT calculation module is further used for judging whether the number of the effective data points in the single group of the first complex signals is the whole power of 2, if so, determining the cascade number of the butterfly factors according to the magnitude that the number of the input effective data points is the power of the whole power of 2;

13. The FPGA-based fixed point data processing apparatus of claim 9,

the frequency domain recovery module is further configured to store the valid data point data in the second complex signal into a first storage unit and a second storage unit according to a positive bit sequence operation and a negative bit sequence operation, and simultaneously read a pair of valid data point data from the first storage unit and the second storage unit one by one in a parallel manner to perform corresponding operation processing.

14. The FPGA-based fixed point data processing apparatus of claim 13,

before the frequency domain result is output, the frequency domain recovery module is further configured to adjust, by a truncation or shift method, a bit width of the output frequency domain result corresponding to each of the two real sequences of the two channels to be consistent with a bit width of the target fixed point data.

15. A computer readable storage medium, characterized in that it stores a computer program that can be loaded by a processor to perform the FPGA-based fixed point data processing method according to any of claims 1 to 8.