CN1934705A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN1934705A
CN1934705A CN 200580008875 CN200580008875A CN1934705A CN 1934705 A CN1934705 A CN 1934705A CN 200580008875 CN200580008875 CN 200580008875 CN 200580008875 A CN200580008875 A CN 200580008875A CN 1934705 A CN1934705 A CN 1934705A
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China
Prior art keywords
transistor
peripheral circuit
gate oxidation
grid
oxidation films
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CN 200580008875
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Chinese (zh)
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CN100576545C (en
Inventor
吉田雅昭
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Ricoh Microelectronics Co Ltd
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Ricoh Co Ltd
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Abstract

A semiconductor device is disclosed that includes a nonvolatile memory cell having a memory transistor and a selection transistor, and a peripheral circuit transistor. The memory transistor includes a memory gate oxide film that is arranged on a semiconductor substrate, and a floating gate made of polysilicon that is arranged on the memory gate oxide film. The selection transistor is serially connected to the memory transistor and includes a selection gate oxide film that is arranged on the semiconductor substrate, and a selection gate made of polysilicon that is arranged on the selection gate oxide film. The peripheral circuit transistor includes a peripheral circuit gate oxide film that is arranged on the semiconductor substrate, and a peripheral circuit gate made of polysilicon that is arranged on the peripheral circuit gate oxide film. The memory gate oxide film is arranged to be thinner than the peripheral circuit gate oxide film.

Description

Semiconductor device
Technical field
The present invention relates to comprise non-volatile memory cells and such as the semiconductor device of the peripheral circuit of logical circuit with floating grid.For example, this semiconductor device can be as the semiconductor device that comprises distributor (divider) resistance circuit, voltage detection circuit or constant voltage generative circuit.
Background technology
Electrically Erasable Read Only Memory (EEPROM) is corresponding to a kind of form of nonvolatile memory, and can be divided into two classes usually according to the quantity of using grid.Be that EEPROM can be divided into individual layer grid type nonvolatile memory and double-deck grid type nonvolatile memory.For example, disclosed the technology that relates to list-floor grid type nonvolatile memory international patent application 8-506693 number of Japan Patent open 6-85275 number and translator of Japanese, and the technology that has disclosed about double-deck grid type nonvolatile memory for Japanese patent laid-open publication gazette 4-80544 number.
Fig. 1 is the plane graph of individual layer grid type nonvolatile memory.Nonvolatile memory as shown in Figure 1 comprises p-N-type semiconductor N substrate (p-substrate) 101, n-type diffusion layer 103,105,107 and control gate 109.Should note between n- type diffusion layer 103 and 105, being provided with at interval, and between n- type diffusion layer 105 and 107, be provided with at interval.
The zone that the selection grid of being made by polysilicon membrane 111 are arranged in p-substrate 101 by the grid oxidation film (not shown) go up with the part crossover of n- type diffusion layer 103 and 105, this zone comprises the zone between n-type diffusion layer 103 and 105.The floating grid of being made by the polysilicon oxidation film 113 arranges by the silicon oxide film (not shown), and with extension above zone of p-substrate 101 and control gate 109, this zone is included in the zone between n-type diffusion layer 105 and 107.Should note floating grid 113 be arranged to by the storage gate oxidation films partly with the part crossover of n- type diffusion layer 105 and 107.
When on this individual layer grid type nonvolatile memory, carrying out write operation, when promptly injecting electronics to floating grid 113, n-type diffusion layer 103 is set to 0V, and n-type diffusion layer 107 is set to predetermined potential Vpp, and this predetermined potential Vpp is applied on control gate 109 and the selection grid 111.Like this, can connect by transistor and selection grid 111 that n-type diffusion layer 103,105 is realized, and electronics can be injected into the floating grid 113 by the storage gate oxidation films from n-type diffusion layer 105.
When write operation is wiped in execution on this individual layer grid type nonvolatile memory, promptly from floating grid 113 during ejected electron, control gate 109 is set to 0V, and n-type diffusion layer 107 opens wide, and predetermined electromotive force Vpp is applied on n-type diffusion layer 103 and the selection grid 111.Like this, can connect, and the electronics that is infused in the floating grid 113 can extract in the n-type diffusion layer 105 via the storage gate oxidation films by tunnel effect by transistor and selection grid 111 that n-type diffusion layer 103,105 is realized.
Fig. 2 is the profile of double-deck grid type nonvolatile memory.Nonvolatile memory as shown in Figure 2 comprises the p-substrate 101 and the n- type diffusion layer 117 and 119 of each interval.The zone that the floating grid of being made by polysilicon membrane 123 is arranged in p-substrate 101 by storage gate oxidation films 121 go up with partly with the part crossover of n- type diffusion layer 117 and 119, this zone is included in the zone between n-type diffusion layer 117 and 119.The control gate of being made by polysilicon membrane 127 is arranged on the floating grid 123 by silica membrane 125.
When on this double-deck grid type nonvolatile memory, carrying out write operation, when promptly injecting electronics to floating grid 123, n-type diffusion layer 119 is set to 0V, and n-type diffusion layer 117 is set to predetermined potential Vpp, and applies predetermined electromotive force Vpp for control gate 127.Like this, electronics can be injected into the floating grid 123 by the storage gate oxidation films from n-type diffusion layer 119.
When carrying out erase operation on this double-deck grid type nonvolatile memory, promptly from floating grid 123 during ejected electron, this control gate 127 is set to 0V, and n-type diffusion layer 117 opens wide, and predetermined electromotive force Vpp is applied on the n-type diffusion layer 119.Like this, the electronics that is infused in the floating grid 113 can extract in the n-type diffusion layer 119 by storage gate oxidation films 121.
The technology that Japan Patent has openly openly disclosed about the non-volatile memory cells that does not comprise control gate for 2004-31920 number with Japan Patent for 2003-168747 number.
Fig. 3 A and 3B be the diagram nonvolatile memory that do not comprise control gate schematic diagram, Fig. 3 A is the plane graph of this nonvolatile memory, and Fig. 3 B is its profile.It should be noted that in these accompanying drawings, the element that those shown in Fig. 1 and 2 have said function provides identical reference number.
Nonvolatile memory shown in Fig. 3 A and the 3B comprises p-substrate 101 and n-type diffusion layer 103,105 and 107.Should note being provided with between n- type diffusion layer 103 and 105 at interval and between n- type diffusion layer 105 and 107, being provided with at interval.
The zone that the selection grid of being made by polysilicon membrane 111 are arranged in p-substrate 101 by grid oxidation film 129 go up with partly with the part crossover of n- type diffusion layer 103 and 105, this zone is included in the zone between n-type diffusion layer 103 and 105.The floating grid of being made by polysilicon membrane 123 is arranged on the zone of p-substrate 101 by storage gate oxidation films 121, and this zone is included in the zone between n- type diffusion layer 105 and 107, to realize memory transistor.The transistor 123 of floating be arranged to by storage gate oxidation films 121 partly with the part crossover of n- type diffusion layer 105 and 107.
When on this nonvolatile memory, carrying out erase operation, promptly from floating grid 123 during ejected electron, for example, can be on the transistor 123 of floating irradiation ultraviolet radiation so that the transistor 123 of floating can be initialised to the zero charge state.
In this case, for example n-type diffusion layer 103 is set to 0V, and n-type diffusion layer 107 and selection grid 111 are set to predetermined electromotive force Vpp such as 7V.Like this, can be connected by the selection transistor that n-type diffusion layer 103,105 and selection grid 111 are realized, the electronics that is infused in the floating grid 123 can extract in the n-type diffusion layer 105 via storage grid oxide film 121 by tunnel effect.In this example, n-type diffusion layer 103 and floating grid 123 must be each other crossover fully.Therefore, embedding n-type diffusion layer is in n-type diffusion layer 105 1 sides that are arranged under the floating grid 123, as described in the open 2003-168747 of Japan Patent.
When on this nonvolatile memory, carrying out write operation, when promptly being injected into electronics in the floating grid 123, n-type diffusion layer 107 is set to 0V, and predetermined electromotive force Vpp such as 4.5V are applied on the n-type diffusion layer 103, and selects grid 111 to be set to predetermined voltage Von such as 2V.Like this, can connect, and electronics can be injected into the floating grid 123 by the storage gate oxidation films from n-type diffusion layer 105 by the selection transistor that n-type diffusion layer 103,105 and selection grid 111 are realized.In this case, embedded type n-type diffusion layer must be rendered as the situation when carrying out erase operation.
Equally, it should be noted, the open 2004-31920 number announcement of Japan Patent is provided with the transistorized grid oxidation film of MOS (metallic silicon oxide) of the peripheral circuit of realization such as logical circuit, to have identical thickness with the grid oxidation film of selecting transistorized grid oxidation film and memory transistor.
When be arranged to as the grid oxidation film of the memory transistor that does not comprise control gate, selection transistor and the peripheral circuit transistor of in open 2004-31920 number of Japan Patent, being instructed have same thickness the time, when grid oxidation film was arranged to have half grade of (sub half level) thickness of branch of 7.5nm, the storage gate oxidation films of memory transistor also had the thickness of 7.5mm.Like this, the present inventor found through experiments needs about 6-7V or higher predetermined potential Vpp so that obtain the good feature of writing.
Yet in this case, for example 6-7V or higher voltage must be applied on the peripheral circuit transistor, when this peripheral circuit transistor structure carries out write operation on memory transistor predetermined electromotive force Vpp are applied to memory.This means that the electric field that will reach about 10MV/cm applies on the thick peripheral circuit transistor grid oxidation film of 7.5nm (hereinafter referred to as ' peripheral circuit grid oxidation film '), and therefore, the peripheral circuit transistor grid oxidation film may be easy to damage and may reduce the productive rate and the reliability of corresponding semiconductor device.Equally, discovery according to the inventor, snapback (snapback) voltage of nmos pass transistor (N channel transistor) with the thick grid oxidation film of 7.5nm is about 6-7V, it equals predetermined potential Vpp substantially, and therefore, when memory transistor was carried out write operation, peripheral circuit was easy to damage, and says the productive rate and the reliability that also may reduce the corresponding semiconductor device from this respect.
In order to prevent this problem, the thickness of the gate oxidation films of memory transistor, selection transistor and peripheral circuit transistor for example can be set to half grade of about 13.5nm.Yet when grid oxidation film thickness increased, writing voltage Vpp also must increase, and makes it can't resolve at grid oxidation film thickness and is set to the problem that occurs under half grade of situation of attached branch.When the thickness of grid oxidation film is set to about 13.5nm and writes voltage Vpp when being set to about 6-7V, although can prevent infringement to the peripheral circuit grid oxidation film, but the storage gate oxidation films of memory transistor also is set to 13.5nm, thereby can not obtain good write attribute.
Equally, the present inventor has tested and has estimated the semiconductor device that is disclosed in open 2004-31920 number of the Japan Patent, it comprises the memory transistor of not being with control gate and selects transistor and peripheral circuit transistor, and find in this semiconductor device, can not obtain enough charge-retention property mainly due to impurity concentration high in the polysilicon of floating grid.
Summary of the invention
According to one or more problems described above; conceived the present invention and the semiconductor device that comprises non-volatile memory cells and peripheral circuit transistor is provided; this non-volatile memory cells comprises the memory transistor of selecting transistor not have control gate with having floating grid; wherein semiconductor device can be carried out write operation fully on memory transistor, and the grid oxidation film of protection peripheral circuit is without prejudice.
The present invention also provides semiconductor device, it comprises non-volatile memory cells and the peripheral circuit transistor of selecting transistor not have the memory transistor of control gate with having floating grid, wherein can improve the semiconductor device charge-retention property of memory transistor.
According to one embodiment of present invention, the semiconductor device that is provided comprises:
Semiconductor substrate;
Non-volatile memory cells, it comprises
Memory transistor is realized by MOS transistor, comprise the storage gate oxidation films that is arranged on the semiconductor substrate and make the floating grid that is arranged on the storage grid oxide film by polysilicon, this floating grid be in electric floating state and
Select transistor, realized by MOS transistor, be connected in series on the memory transistor, this selections transistor comprises the selection grid oxidation film that is arranged on the semiconductor substrate and is made on the selection grid that are arranged on the selection grid oxidation film by polysilicon; With
Peripheral circuit transistor is realized by MOS transistor, comprises the peripheral circuit grid oxidation film that is arranged on the semiconductor substrate and is arranged on peripheral circuit grid on the peripheral circuit grid oxidation film by what polysilicon was made;
Wherein storing gate oxidation films is arranged to thinner than peripheral circuit gate oxidation films.
In a preferred embodiment of the invention, memory transistor and selection transistor are the PMOS transistors.
In another preferred embodiment of the present invention, select grid oxidation film to be arranged to have identical thickness with the storage gate oxidation films.
In another preferred embodiment of the present invention, select grid oxidation film to be arranged to have identical thickness with the peripheral circuit grid oxidation film.
In another preferred embodiment of the present invention, semiconductor device of the present invention also comprises:
Capacitor comprises by the polysilicon manufacturing and by insulation film being arranged on bottom electrode on the semiconductor substrate, and comprises by the polysilicon manufacturing and by capacitor insulation film and be arranged on top electrode on this bottom electrode;
Wherein floating grid is created by identical polysilicon layer with bottom electrode, and capacitor insulating film is arranged on the upper surface and side surface of floating grid.
In another preferred embodiment of the present invention, the peripheral circuit grid are created by identical polysilicon layer with top electrode.
In another preferred embodiment of the present invention, select grid, floating grid and bottom electrode to create by identical polysilicon layer.
In another preferred embodiment of the present invention, select grid, peripheral circuit grid and top electrode to create by identical polysilicon layer.
According to another embodiment of the invention, the semiconductor device that is provided comprises the distributor resistance circuit, and it is configured to obtain voltage output and pass through to cut off one or more fuse element regulation voltages outputs by the voltage dividing potential drop.Distributor resistance circuit according to an embodiment comprises: a plurality of resistances are regulated resistive element, are connected in series; A plurality of fuse MOS transistor as fuse element, are regulated resistive element with resistance and are connected in parallel; Non-volatile memory cells according to an embodiment of the invention; And reading circuit, be used for store status ON/OFF fuse MOS transistor according to non-volatile memory cells, wherein at least one in fuse MOS transistor and the reading circuit is configured to the peripheral circuit transistor according to the embodiment of the invention.
According to another embodiment of the invention, the semiconductor device that is provided comprises: voltage detection circuit, comprise distributor resistance circuit according to an embodiment of the invention, and distribute the voltage of input voltage and this distribution of output; Generating circuit from reference voltage produces reference voltage; And comparison circuit, the distribution voltage from the distributor resistance circuit is compared with the reference voltage from generating circuit from reference voltage.
According to another embodiment of the invention, the semiconductor device that is provided comprises: the constant voltage generative circuit comprises output driver, the output of control input voltage; The distributor resistance circuit distributes output voltage and exports the voltage of this distribution according to an embodiment of the invention, and generating circuit from reference voltage produces reference voltage; And comparison circuit, the distribution voltage from the distributor resistance circuit is compared with the reference voltage from generating circuit from reference voltage, and control the operation of output driver according to comparative result.
According to another embodiment of the invention, the semiconductor device that is provided comprises:
Semiconductor substrate;
Non-volatile memory cells comprises
Memory transistor is realized by MOS transistor, comprise the storage gate oxidation films that is arranged on the semiconductor substrate and be arranged on floating grid on the storage gate oxidation films by what polysilicon was made, this floating grid be in electric floating state and
Select transistor, realized by MOS transistor, be connected in series on the memory transistor, this selections transistor comprises the selection grid oxidation film that is arranged on the semiconductor substrate and is arranged on selection grid on the selection grid oxidation film by what polysilicon was made; With
Peripheral circuit transistor is realized by MOS transistor, comprises the peripheral circuit grid oxidation film that is arranged on the semiconductor substrate and is arranged on peripheral circuit grid on the peripheral circuit grid oxidation film by what polysilicon was made;
Wherein the impurity concentration in the polysilicon of floating grid is arranged to be lower than the interior impurity concentration of polysilicon of peripheral circuit grid.
In a preferred embodiment of the invention, the impurity concentration in the polysilicon of selection grid equals the interior impurity concentration of polysilicon of floating grid.
In another preferred embodiment of the present invention, the impurity concentration in the polysilicon of selection grid equals the interior impurity concentration of polysilicon of peripheral circuit grid.
In another preferred embodiment of the present invention, storage gate oxidation films, selection grid oxidation film are arranged to have identical thickness with the peripheral circuit grid oxidation film.
In another preferred embodiment of the present invention, the storage gate oxidation films is arranged to thinner than peripheral circuit grid oxidation film.
In another preferred embodiment of the present invention, select grid oxidation film to be arranged to have identical thickness with the storage gate oxidation films.
In another preferred embodiment of the present invention, select grid oxidation film to be arranged to have identical thickness with the peripheral circuit grid oxidation film.
In another preferred embodiment of the present invention, memory transistor and selection transistor are the PMOS transistors.
According to another embodiment of the present invention, the semiconductor device that is provided comprises the distributor resistance circuit, is configured to obtain output voltage and reconcile output voltage by cutting off one or more fuse elements by voltage divider.Distributor resistance circuit according to an embodiment comprises a plurality of resistances adjusting resistive elements that are connected in series, a plurality of fuse MOS transistor are parallel-connected to resistance as fuse element and regulate on the resistive element, according to an embodiment of the invention non-volatile memory cells, be used for reading circuit according to the store status ON/OFF fuse MOS transistor of non-volatile memory cells, wherein at least one fuse MOS transistor and reading circuit are configured to the peripheral circuit transistor according to the embodiment of the invention.
According to another embodiment of the invention, the semiconductor device that is provided comprises: voltage detection circuit, comprise distributor resistance circuit according to an embodiment of the invention, and distribute input voltage and export the voltage of this distribution; Generating circuit from reference voltage produces reference voltage; Comparison circuit is compared the component voltage from the distributor resistance circuit with the reference voltage from generating circuit from reference voltage.
According to another embodiment of the invention, the semiconductor device that is provided comprises: constant voltage produces circuit, comprises output driver, the output of control input voltage; The distributor resistance circuit distributes output voltage and exports the voltage of this distribution according to an embodiment of the invention; Generating circuit from reference voltage produces reference voltage; And comparison circuit, the distribution voltage from the distributor resistance circuit is compared with the reference voltage from generating circuit from reference voltage, and control the operation of output driver according to comparative result.
Description of drawings
Read following detailed by the reference accompanying drawing, other target of the present invention, feature and advantage will become more clear.
Fig. 1 is the plane graph of individual layer grid type nonvolatile memory;
Fig. 2 is the profile of double-deck grid type nonvolatile memory;
Fig. 3 A and Fig. 3 B are the schematic diagrames that diagram does not comprise the nonvolatile memory of control gate, and Fig. 3 A is the plane graph of nonvolatile memory, cut open the profile of getting and Fig. 3 B is an E-E line along Fig. 3 A;
Fig. 4 A-4D is the schematic diagram of diagram first embodiment of the invention, Fig. 4 A is the plane graph of memory cell, Fig. 4 B is the plane graph of peripheral circuit transistor, Fig. 4 C is the profile that cuts open the memory cell of Fig. 4 A that gets along the A-A line, and Fig. 4 D is the profile that cuts open the peripheral transistor of Fig. 4 B that gets along line A-A;
Fig. 5 is a circuit diagram of showing the exemplary matrix arrangements of the first embodiment memory cell;
Fig. 6 A-6C is the profile that the exemplary processes step of the memory cell of first embodiment and peripheral circuit transistor is made in diagram;
Fig. 7 A-7D is the schematic diagram of diagram second embodiment of the invention, Fig. 7 A is the plane graph of memory cell, Fig. 7 B is the plane graph of peripheral circuit transistor, Fig. 7 C is the profile that cuts open the memory cell of getting along Fig. 7 A line A-A ', and Fig. 7 D is the profile that cuts open the peripheral circuit transistor of getting along Fig. 7 B line B-B ';
Fig. 8 A-8C is the profile that the exemplary processes step of the memory cell of second embodiment and peripheral circuit transistor is made in diagram;
Fig. 9 A-9E is the schematic diagram of diagram third embodiment of the invention, the plane graph of Fig. 9 A memory cell, Fig. 9 B is the plane graph of peripheral circuit transistor, Fig. 9 C is the profile that cuts open the memory cell of getting along Fig. 9 A line A-A ', Fig. 9 D is the profile that cuts open the peripheral circuit transistor of getting along Fig. 9 B line B-B ', and Fig. 9 E is the profile that cuts open the capacitor of getting along Fig. 9 A line C-C;
Figure 10 A-10C is the profile of the exemplary processes step of diagram memory cell, peripheral circuit transistor and the capacitor of making the 3rd embodiment;
Figure 11 A-11E is the schematic diagram of diagram fourth embodiment of the invention, Figure 11 A is the plane graph of memory cell and capacitor, Figure 11 B is the plane graph of peripheral circuit transistor, Figure 11 C is the profile that cuts open the memory cell of getting along Figure 11 A line A-A ', Figure 11 D is the profile that cuts open the peripheral circuit transistor of getting along Figure 11 B line B-B ', and Figure 11 E is the profile that cuts open the capacitor of getting along Figure 11 A line C-C ';
Figure 12 A-12C is the profile of the exemplary processes step of diagram memory cell, peripheral circuit transistor and the capacitor of making the 4th embodiment;
Figure 13 A-13F is the schematic diagram of diagram fifth embodiment of the invention, Figure 13 A is the plane graph of memory cell, Figure 13 B is as the transistorized plane graph of the PMOS of peripheral circuit transistor, Figure 13 C is the profile that Figure 13 A A-A ' along the line cuts open the memory cell of getting, Figure 13 D is that Figure 13 B B-B ' along the line cuts open the transistorized profile of the PMOS that gets, Figure 13 E is the plane graph as the nmos pass transistor of another peripheral circuit transistor, and Figure 13 F is the profile that Figure 13 E D-D ' along the line cuts open the nmos pass transistor of getting;
Figure 14 is diagram produces circuit according to the constant voltage that comprises the distributor resistance circuit of the embodiment of the invention a circuit diagram;
Figure 15 is the circuit diagram of diagram according to the voltage detection circuit that comprises the distributor resistance circuit of the embodiment of the invention
Figure 16 A-16D is the schematic diagram of diagram sixth embodiment of the invention, Figure 16 A is the plane graph of memory cell, Figure 16 B is the plane graph of peripheral circuit transistor, to be Figure 16 A cut open the profile of the memory cell of getting along line A-A ' to Figure 16 C, and Figure 16 D is Figure 16 B cuts open the peripheral transistor of getting along line B-B ' a profile;
Figure 17 is the figure line of expression according to the charge-retention property of the memory transistor of the embodiment of the invention;
Figure 18 is the circuit diagram of exemplary matrix arrangements of showing the memory cell of the 6th embodiment;
Figure 19 A-19C is the profile that the exemplary processes step of the memory cell of the 6th embodiment and peripheral circuit transistor is made in diagram;
Figure 20 A-20D is the schematic diagram of diagram seventh embodiment of the invention, Figure 20 A is the plane graph of memory cell, Figure 20 B is the plane graph of peripheral circuit transistor, Figure 20 C is the profile that Figure 20 A A-A ' along the line cuts open the memory cell of getting, and Figure 20 D is the profile that Figure 20 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 21 A-21C is the profile that the exemplary processes step of the memory cell of the 7th embodiment and peripheral circuit transistor is made in diagram;
Figure 22 A-22D is the schematic diagram of diagram eighth embodiment of the invention, Figure 22 A is the plane graph of memory cell, Figure 22 B is the plane graph of peripheral circuit transistor, Figure 22 C is the profile that Figure 22 A A-A ' along the line cuts open the memory cell of getting, and Figure 22 D is the profile that Figure 22 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 23 A-23C is the profile that the exemplary processes step of the memory cell of the 8th embodiment and peripheral circuit transistor is made in diagram;
Figure 24 A-24D is the schematic diagram of diagram ninth embodiment of the invention, Figure 24 A is the plane graph of memory cell, Figure 24 B is the plane graph of peripheral circuit transistor, Figure 24 C is the profile that Figure 24 A A-A ' along the line cuts open the memory cell of getting, and Figure 24 D is the profile that Figure 24 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 25 A-25C is the profile that the exemplary processes step of the memory cell of the 9th embodiment and peripheral circuit transistor is made in diagram;
Figure 26 A-26D is the schematic diagram of diagram tenth embodiment of the invention, Figure 26 A is the plane graph of memory cell, Figure 26 B is the plane graph of peripheral circuit transistor, Figure 26 C is the profile that Figure 26 A A-A ' along the line cuts open the memory cell of getting, and Figure 26 D is the profile that Figure 26 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 27 A-27C is the profile that the exemplary processes step of the memory cell of the tenth embodiment and peripheral circuit transistor is made in diagram;
Figure 28 A-28D is the schematic diagram of diagram eleventh embodiment of the invention, Figure 28 A is the plane graph of memory cell, Figure 28 B is the plane graph of peripheral circuit transistor, Figure 28 C is the profile that Figure 28 A A-A ' along the line cuts open the memory cell of getting, and Figure 28 D is the profile that Figure 28 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 29 A-29C is the profile that the exemplary processes step of the memory cell of the 11 embodiment and peripheral circuit transistor is made in diagram;
Figure 30 A-30D is the schematic diagram of diagram twelveth embodiment of the invention, Figure 30 A is the plane graph of memory cell, Figure 30 B is the plane graph of peripheral circuit transistor, Figure 30 C is the profile that Figure 30 A A-A ' along the line cuts open the memory cell of getting, and Figure 30 D is the profile that Figure 30 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 31 A-31C is the profile that the exemplary processes step of the memory cell of the 12 embodiment and peripheral circuit transistor is made in diagram;
Figure 32 A-32D is the schematic diagram of diagram thriteenth embodiment of the invention, Figure 32 A is the plane graph of memory cell, Figure 32 B is the plane graph of peripheral circuit transistor, Figure 32 C is the profile that Figure 32 A A-A ' along the line cuts open the memory cell of getting, and Figure 32 D is the profile that Figure 32 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 33 A-33C is the profile that the exemplary processes step of the memory cell of the 13 embodiment and peripheral circuit transistor is made in diagram;
Figure 34 A-34D is the schematic diagram of diagram fourteenth embodiment of the invention, Figure 34 A is the plane graph of memory cell, Figure 34 B is the plane graph of peripheral circuit transistor, Figure 34 C is the profile that Figure 34 A A-A ' along the line cuts open the memory cell of getting, and Figure 34 D is the profile that Figure 34 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 35 A-35C is the profile that the exemplary processes step of the memory cell of the 14 embodiment and peripheral circuit transistor is made in diagram;
Figure 36 A-36D is the schematic diagram of diagram fifteenth embodiment of the invention, Figure 36 A is the plane graph of memory cell, Figure 36 B is the plane graph of peripheral circuit transistor, Figure 36 C is the profile that Figure 36 A A-A ' along the line cuts open the memory cell of getting, and Figure 36 D is the profile that Figure 36 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 37 A-37C is the profile that the exemplary processes step of the memory cell of the 15 embodiment and peripheral circuit transistor is made in diagram;
Figure 38 A-38D is the schematic diagram of diagram sixteenth embodiment of the invention, Figure 38 A is the plane graph of memory cell, Figure 38 B is the plane graph of peripheral circuit transistor, Figure 38 C is the profile that Figure 38 A A-A ' along the line cuts open the memory cell of getting, and Figure 38 D is the profile that Figure 38 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 39 A-39C is the profile that the exemplary processes step of the memory cell of the 16 embodiment and peripheral circuit transistor is made in diagram;
Figure 40 A-40D is the schematic diagram of diagram seventeenth embodiment of the invention, Figure 40 A is the plane graph of memory cell, Figure 40 B is the plane graph of peripheral circuit transistor, Figure 40 C is the profile that Figure 40 A A-A ' along the line cuts open the memory cell of getting, and Figure 40 D is the profile that Figure 40 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 41 A-41C is the profile that the exemplary processes step of the memory cell of the 17 embodiment and peripheral circuit transistor is made in diagram;
Figure 42 A-42D is the schematic diagram of diagram eighteenth embodiment of the invention, Figure 42 A is the plane graph of memory cell, Figure 42 B is the plane graph of peripheral circuit transistor, Figure 42 C is the profile that Figure 42 A A-A ' along the line cuts open the memory cell of getting, and Figure 42 D is the profile that Figure 42 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 43 A-43C is the profile that the exemplary processes step of the memory cell of the 18 embodiment and peripheral circuit transistor is made in diagram;
Figure 44 A-44D is the schematic diagram of diagram nineteenth embodiment of the invention, Figure 44 A is the plane graph of memory cell, Figure 44 B is the plane graph of peripheral circuit transistor, Figure 44 C is the profile that Figure 44 A A-A ' along the line cuts open the memory cell of getting, and Figure 44 D is the profile that Figure 44 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 45 A-45D is the schematic diagram of diagram twentieth embodiment of the invention, Figure 45 A is the plane graph of memory cell, Figure 45 B is the plane graph of peripheral circuit transistor, Figure 45 C is the profile that Figure 45 A A-A ' along the line cuts open the memory cell of getting, and Figure 45 D is the profile that Figure 45 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 46 A-46D is the schematic diagram of diagram 21st embodiment of the invention, Figure 46 A is the plane graph of memory cell, Figure 46 B is the plane graph of peripheral circuit transistor, Figure 46 C is the profile that Figure 46 A A-A ' along the line cuts open the memory cell of getting, and Figure 46 D is the profile that Figure 46 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 47 A-47D is the schematic diagram of diagram 22nd embodiment of the invention, Figure 47 A is the plane graph of memory cell, Figure 47 B is the plane graph of peripheral circuit transistor, Figure 47 C is the profile that Figure 47 A A-A ' along the line cuts open the memory cell of getting, and Figure 47 D is the profile that Figure 47 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 48 A-48C is the profile that the exemplary processes step of the memory cell of the 22 embodiment and peripheral circuit transistor is made in diagram;
Figure 49 A-49D is the schematic diagram of diagram 23th embodiment of the invention, Figure 49 A is the plane graph of memory cell, Figure 49 B is the plane graph of peripheral circuit transistor, Figure 49 C is the profile that Figure 49 A A-A ' along the line cuts open the memory cell of getting, and Figure 49 D cuts open the profile of the peripheral circuit transistor of getting for Figure 49 B B-B ' along the line;
Figure 50 A-50D is the schematic diagram of diagram 24th embodiment of the invention, Figure 50 A is the plane graph of memory cell, Figure 50 B is the plane graph of peripheral circuit transistor, Figure 50 C is the profile that Figure 50 A A-A ' along the line cuts open the memory cell of getting, and Figure 50 D is the profile that Figure 50 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 51 A-51D is the schematic diagram of diagram 25th embodiment of the invention, Figure 51 A is the plane graph of memory cell, Figure 51 B is the plane graph of peripheral circuit transistor, Figure 51 C is the profile that Figure 51 A A-A ' along the line cuts open the memory cell of getting, and Figure 51 D is the profile that Figure 51 B B-B ' along the line cuts open the peripheral circuit transistor of getting;
Figure 52 is that diagram comprises the circuit diagram that produces circuit according to the constant voltage of the distributor resistance circuit of the embodiment of the invention; With
Figure 53 is that diagram comprises the circuit diagram according to the voltage detection circuit of the distributor resistance circuit of the embodiment of the invention.
Embodiment
Below, describe the preferred embodiments of the present invention with reference to the accompanying drawings.
Fig. 4 A to 4D is the schematic diagram of diagram first embodiment of the invention.Fig. 4 A is the plane graph of memory cell, and Fig. 4 B is the plane graph of peripheral circuit transistor, and Fig. 4 C is the profile that Fig. 4 A A-A ' along the line cuts open the memory cell of getting, and Fig. 4 D is the profile that Fig. 4 B B-B ' along the line cuts open the peripheral circuit transistor of getting.
As shown in these figures, n-trap 2 is arranged on the presumptive area of p-substrate 1.The field oxide film 3 that implement device is isolated is arranged on the surface of p-substrate 1, and field oxide film 3 has for example thickness of 450-700nm (being 500nm in the present example).P- type diffusion layer 5,7 and 9 be arranged in the n-trap 2 corresponding to by 3 of field oxide films around the zone.It should be noted, between p- type diffusion layer 5 and 7, be provided with at interval, and between p- type diffusion layer 7 and 9, be provided with at interval.
Select gate oxidation films 11 to be arranged on the zone of p-substrate 1, this zone comprises the zone between p- type diffusion layer 5 and 7, selects gate oxidation films 11 to have for example thickness of 10.0-15.0nm (being 13.5nm in this example).Have the selection grid of making by the thick many silicon oxidations film of for example 250-450nm (in this example for 350nm) 13 and be arranged on and select on the gate oxidation films 11, with partly with the part crossover of n-type diffusion layer 5 and 7.It should be noted that p- type diffusion layer 5 and 7, selection gate oxidation films 11 and selection grid 13 have been realized the selection transistor.
Storage gate oxidation films 15 is arranged on the zone that comprises on the surface of p-substrate 1 between p- type diffusion layer 7 and 9, and storage gate oxidation films 15 has for example thickness of 6.0-10.0nm (being 7.5nm in this example).Have the floating grid of making by the thick many silicon oxidations film of for example 250-450nm (350nm in this example) 17 be arranged on the storage gate oxidation films 15 on, with partly with p- type diffusion layer 7 and 9 crossovers.It should be noted that p- type diffusion layer 7,9, storage gate oxidation films 15 and floating grid 17 have been realized memory transistor.
Select transistor and memory transistor to realize memory cell.
Equally, p- type diffusion layer 19 and 21 is arranged in another n-trap 2, corresponding to by 3 of field oxide films that is different from memory cell region around another zone.It should be noted, between p- type diffusion layer 19 and 21, be provided with at interval.
Peripheral circuit gate oxidation films 23 is arranged on the zone of p-substrate 1, and this zone comprises the zone between p- type diffusion layer 19 and 21, and peripheral circuit gate oxidation films 23 has for example thickness of 10.0-15.0nm (being 13.5nm in this example).Have the peripheral circuit grid 25 that 250-450nm for example (being 350nm in this example) thickness made by many silicon oxidations film and be arranged on the peripheral circuit gate oxidation films 23, with partly with the part crossover of p-type diffusion layer 19 and 21.It should be noted that p- type diffusion layer 19,21, peripheral circuit gate oxidation films 23 and peripheral circuit grid 25 have been realized peripheral circuit transistor.
Fig. 5 is the circuit diagram of the exemplary matrix arrangements of the diagram first embodiment memory cell.
In graphic layout, memory cell is with matrix arrangements.Particularly, unit i0, i1 and the selection grid 13 that are arranged in the point ' ' on the horizontal direction (word line WL direction) are electrically connected on the common word line WLi.Equally, p-type diffusion layer 5 is electrically connected on the common source line SLi.Unit 0i, 1i and the p-type diffusion layer 9 that is arranged in the point ' ' on the vertical direction (bit line Bit direction) are electrically connected on the common bit lines Biti.It should be noted that in above-mentioned description, i represents 0 or natural number.
In the present embodiment, erase operation is carried out by ultraviolet irradiation, so that all unit can be wiped immediately.
In write operation, only on unit 00, carry out and write, for example, word line WL0 and the bit line Bit0 that is connected on the unit 00 that carries out write operation is biased to predetermined potential-Vpp, and other word line WLi, other bit line Biti and source line SLi are biased to 0V.Like this, electronics can be injected in the floating grid 17 of unit 00 by the storage gate oxidation films, so that can carry out write operation on unit 00.
Fig. 6 A to 6C is the profile that the exemplary processes step of the memory cell of first embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Fig. 6 A to 6C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Fig. 4 C and the 4D.Below, with reference to Fig. 4 A-4D and Fig. 6 A-6C the memory cell of making first embodiment and the exemplary method of peripheral circuit transistor are described.
(1) after creating n-trap 2 on the p-substrate 1, field oxide film 3 is arranged on the p-substrate 1 by traditional LOCOS (selective oxidation silicon) technology, isolates (seeing Fig. 4 A and 4B) with implement device.Have the sacrificial oxidation film 27 of 6-16nm thickness for example and be arranged on the surface by the active area of field oxide film 3 definition, and carry out channel doping (seeing Fig. 6 A).
(2) resist pattern 29 is arranged on the sacrificial oxidation film 27, and the resist pattern covers selects transistor formation region and peripheral circuit transistor to form the district, and has opening portion in memory transistor formation district.This resist pattern 29 is as mask, optionally to remove the sacrificial oxidation film 27 (seeing Fig. 6 B) that is arranged on the memory transistor zone.
(3) after removing resist pattern 29, on the surface of the n-trap 2 on the memory transistor zone, carry out thermal oxidation technology and have for example storage gate oxidation films 15 of 6-10nm thickness with generation.In this technology,, become respectively thus and select gate oxidation films 11 and peripheral circuit gate oxidation films 23 selecting the sacrificial oxidation film 27 in transistor area and the peripheral circuit transistor district to increase thickness to for example 10-20nm.Then, thickness is that the polysilicon film 31 of for example 250-450nm is arranged on gate oxidation films 11,15 and 23 and (sees Fig. 6 C).
(4) by on polysilicon film 31, carrying out optical-mechanical technology and etching, selection grid 13 are created on the selection gate oxidation films of selecting on the transistor area 11 and field oxide film 3, floating grid 17 is created on the storage gate oxidation films 15 and field oxide film 3 on the memory transistor zone, and peripheral circuit grid 25 are created on the peripheral circuit gate oxidation films 23 and field oxide film 3 on the peripheral circuit transistor zone.Then,, utilize and select grid 13, floating grid 17 and peripheral circuit grid 25 to inject boron, therefore create p- type diffusion layer 5,7,9,19 and 21 (seeing Fig. 4 A-4D) as mask by ion doping technology.
Fig. 7 A to 7D is the schematic diagram of diagram second embodiment of the invention.Fig. 7 A is the plane graph according to the memory cell of second embodiment, Fig. 7 B is the plane graph according to the peripheral circuit transistor of second embodiment, Fig. 7 C is the profile that Fig. 7 A A-A ' along the line cuts open the memory cell of getting, and Fig. 7 D is the profile that Fig. 7 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted, in these accompanying drawings, as providing same reference number, and omitted description of them at those the same elements shown in Fig. 4 A to 4D.
Present embodiment is different from the first embodiment part shown in Fig. 4 A to 4D and is, selects transistorized selection gate oxidation films 33 to be arranged to have as storing the identical film thickness of thickness of gate oxidation films 15, and thickness is for example 6-10nm scope (being 7.5nm in this example).In the present embodiment, select gate oxidation films 33 and storage gate oxidation films 15 to create simultaneously.
Fig. 8 A to 8C is the profile that the exemplary processes step of the memory cell of second embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile shown in Fig. 8 A to 8C is corresponding to cut open the profile of getting along line A-A ' and B-B ' shown in Fig. 7 C-7D.Below, with reference to Fig. 7 A-7D and Fig. 8 A-8C the memory cell of making second embodiment and the exemplary method of peripheral circuit transistor are described.
(1) n-trap 2, field oxide film 3 (seeing Fig. 7 C and 7D) and sacrificial oxidation film 27 are arranged on the p-substrate 1 by the technology that is similar to as above with reference to the described processing step of Fig. 6 A (1), after this carry out channel doping (seeing Fig. 8 A).
(2) resist pattern 29 is arranged on the sacrificial oxidation film 27, and resist pattern 29 covers peripheral circuit transistors and forms the district, and has opening portion on the zone selecting transistor formation region territory and memory transistor to form.Resist pattern 29 selects transistor formation region territory and memory transistor to form sacrificial oxidation film 27 (seeing Fig. 8 B) on the zone as mask optionally to remove to be arranged on.
(3) after optionally removing resist pattern 29, carry out thermal oxidation technology, the selection gate oxidation films of the thickness of 6-10nm for example is based upon selection transistor formation region territory with the storage gate oxidation films and memory transistor forms on the surface of the n-trap 2 on the zone so that have.In this technology, sacrificial oxidation film 27 thickness on the peripheral circuit transistor zone increase, to become peripheral circuit gate oxidation films 23.Then, polysilicon film 31 is arranged on gate oxidation films 15,23 and 33 and (sees Fig. 8 C).
(4) select grid 13, floating grid 17 and peripheral circuit grid 25 to create, and p- type diffusion layer 5,7,9,19 and 21 is created (seeing Fig. 7 A-7D) via being similar to as above to inject by ion with reference to the technology of the described processing step of Fig. 4 A-4D (4) by polysilicon film 31.
Fig. 9 A to 9E is the schematic diagram of diagram third embodiment of the invention.Fig. 9 A is the plane graph of memory cell and electric capacity, Fig. 9 B is the plane graph of peripheral circuit transistor, Fig. 9 C is the profile that Fig. 9 A A-A ' along the line cuts open the memory cell of getting, and profile and Fig. 9 E that Fig. 9 D is Fig. 9 B B-B ' along the line cuts open the peripheral circuit transistor of getting are the profiles that Fig. 9 A C-C ' along the line cuts open the electric capacity of getting.It should be noted, in these accompanying drawings, as providing same reference number, and omitted description of them at those the same elements shown in Fig. 4 A to 4D.
According to present embodiment, n-trap 2 is arranged on the presumptive area of p-substrate 1, and field oxide film 3 is arranged on the surface of p-substrate 1.
The selection transistor of being realized by p- type diffusion layer 5 and 7, selection gate oxidation films 11 and selection grid 13 is arranged on the selection transistor area.
The memory transistor of being realized by p- type diffusion layer 7 and 9, storage gate oxidation films 15 and floating grid 17 is arranged on the memory transistor zone.
The peripheral circuit transistor of being realized by p- type diffusion layer 19 and 21, peripheral circuit gate oxidation films 23 and peripheral circuit grid 25 is arranged on the peripheral circuit transistor zone.
Having the bottom electrode 37 that equals floating grid 17 thickness is arranged on the field oxide film 3.Having capacitor insulating film 39 that 15-40nm thickness for example (being 20nm in this example) made by silicon fiml is arranged on the surface of bottom electrode 37 (seeing Fig. 6 C and 6E).Have and equal to select the top electrode of making by polysilicon film 41 of grid 13 and peripheral circuit grid 25 thickness to be arranged on the capacitor insulating film 39.It should be noted that bottom electrode 37, capacitor insulating film 39 and top electrode 41 are realized the electric capacity of present embodiment.
Capacitor insulating film 39 also is arranged on the surface of floating grid 17.
Figure 10 A to 10C is the profile of the exemplary processes step of diagram memory cell, peripheral circuit transistor and the capacitor of making the 3rd embodiment.It should be noted that the profile shown in Figure 10 A-10C is corresponding to cut open the cross section of getting along line A-A ' and C-C ' shown in Fig. 9 C-9E.The exemplary method of memory cell, peripheral circuit transistor and the capacitor of making the 3rd embodiment is described with reference to Fig. 9 A-9E and Figure 10 A-10C below.
(1) after creating n-trap 2 on the p-substrate 1, field oxide film 3 is arranged on the p-substrate 1 by traditional LOCOS (selective oxidation silicon) technology, isolates (seeing Fig. 9 A and 9B) with implement device.Have the sacrificial oxidation film 27 of 10-20nm thickness for example and be arranged on the surface by the active area of field oxide film 3 definition, and carry out channel doping.After removing sacrificial oxidation film, storage gate oxidation films 15 is arranged on the surface of p-substrate 1.Then, for example having, the polysilicon film of 250-450nm thickness is arranged on the surface of p-substrate 1, and on polycrystalline film, carry out composition, create floating grid 17 on the storage gate oxidation films 15 on the zone and on the field oxide film 3 in the electric capacity formation district, create bottom electrode 37 (seeing Figure 10 A) to form at memory transistor.
(2) on the surface of bottom electrode 37 and floating grid 17, carry out thermal oxidation technology, have the capacitor insulating film of making by silicon oxide film 39 of 15-40nm thickness for example with establishment.In this technology,, select gate oxidation films 11 and peripheral circuit gate oxidation films 23 to become selecting the storage gate oxidation films 15 on the transistor area and on the peripheral circuit transistor zone to grow to have for example thickness of 12-50nm.
(3) having the polysilicon film 31 of 250-450nm thickness for example is arranged on the surface of p-substrate 1 (seeing Figure 10 C).
(4) by on polysilicon film 31, carrying out optical-mechanical technology and etching, select grid 13 to be created in and select on the gate oxidation films 11, peripheral circuit grid 25 are created on the peripheral circuit gate oxidation films 23, and top electrode 41 is created on the capacitor insulating film 39 that is arranged on the bottom electrode 37.Then,, utilize and select grid 13, floating grid 17 and peripheral circuit grid 25 to inject boron, create p- type diffusion layer 5,7,9,19 and 21 (seeing Fig. 9 A-9E) thus as mask by ion implantation technology.
Figure 11 A-11E is the schematic diagram of diagram fourth embodiment of the invention.Figure 11 A is according to the memory cell of the 4th embodiment and the plane graph of electric capacity, Figure 11 B is the plane graph according to the peripheral circuit transistor of the 4th embodiment, Figure 11 C is the profile that Figure 11 A A-A ' along the line cuts open the memory cell of getting, and Figure 11 E is the profile that Figure 11 A C-C ' along the line cuts open the electric capacity of getting.Should notice being that in these accompanying drawings, those the same elements shown in Fig. 4 A to 4D and Fig. 9 A-9E provide same reference number, and have omitted description of them.
Present embodiment is different from aforesaid the 3rd embodiment part and is, selects transistorized selection gate oxidation films 33 to be arranged to have as storing the identical thickness of thickness of gate oxidation films 15, and for example its thickness can be 6-10nm scope (being 7.5nm in this example).Equally, in the present embodiment, capacitor insulating film 39 is arranged on the surface of selecting grid 13.In addition, select gate oxidation films 33 and storage gate oxidation films 15 to create simultaneously.
Figure 12 A-12C is the profile of the exemplary processes step of diagram memory cell, peripheral circuit transistor and the electric capacity of making the 4th embodiment.It should be noted that the profile shown in Figure 12 A-12C is corresponding to cut open the profile of getting along line A-A ', B-B ' and C-C ' shown in Figure 11 C-11E.The exemplary method of memory cell, peripheral circuit transistor and the electric capacity of making the 4th embodiment is described with reference to Figure 11 A-11E and Figure 12 A-12C below.
(1) after creating n-trap 2 on the p-substrate 1, field oxide film 3 is arranged on the p-substrate 1 by traditional LOCOS (selective oxidation silicon) technology, isolates (seeing figure HA and HB) with implement device.Have the sacrificial oxidation film of 10-20nm ranges of thicknesses for example and be arranged on the surface by the active area of field oxide film 3 definition, and carry out channel doping.After removing sacrificial oxidation film, store gate oxidation films 15 and as select the silicon oxide film of gate oxidation films to be arranged on the surface of p-substrate 1.Then, for example having, the polysilicon film of 250-450nm thickness is arranged on the surface of p-substrate 1, and on polycrystalline film, carry out composition, to form the bottom electrode 37 on the field oxide film 3 of creating floating grid 17 and electric capacity formation district (seeing Figure 12 A) on the storage gate oxidation films 15 in the district at memory transistor.
(2) at bottom electrode 37, select to carry out thermal oxidation technology on the surface of grid 13 and floating grid 17, have the capacitor insulating film 39 that 15-40nm thickness range is for example made by silicon oxide film with establishment.In this technology, grow to have for example thickness of 12-50nm, to become peripheral circuit gate oxidation films 23 (seeing Figure 12 B) at the silicon oxide film in peripheral circuit transistor district.
(3) having the polysilicon film 31 of 250-450nm thickness for example is arranged on the surface of p-substrate 1 (seeing Figure 12 C).
(4) by carry out optical-mechanical technology and etching on polysilicon film 31, peripheral circuit grid 25 are created on the peripheral circuit gate oxidation films 23, and top electrode 41 is created on the capacitor insulating film 39 that is arranged on the bottom electrode 37.Then,, utilize and select grid 13, floating grid 17 and peripheral circuit grid 25 to inject boron, therefore create p- type diffusion layer 5,7,9,19 and 21 (seeing Figure 11 A-11E) as mask by ion implantation technology.
Should notice that in above-mentioned graphic embodiment the PMOS transistor is as peripheral circuit transistor.Yet, the invention is not restricted to such embodiment, for example nmos pass transistor can be used as peripheral circuit transistor, or nmos pass transistor and PMOS transistor all can be used as peripheral circuit transistor.
Figure 13 A-13F illustrates fifth embodiment of the invention, and wherein nmos pass transistor and PMOS transistor all can be used as peripheral circuit transistor.Should notice that in these accompanying drawings those the same elements shown in Fig. 4 A-4D provide same reference number, and have omitted description of them.
In the present embodiment, n-trap 2 and p-trap 43 are arranged on the presumptive area of p-substrate 1, and field oxide film 3 is arranged on the surface of p-substrate 1.
By p- type diffusion layer 5 and 7, select gate oxidation films 11 and select grid 13 " the selection transistor realized is arranged on and selects on the transistor area.
The memory transistor of being realized by p- type diffusion layer 7 and 9, storage gate oxidation films 15 and floating grid 17 is arranged on the memory transistor zone.
The PMOS peripheral circuit transistor of being realized by p- type diffusion layer 19 and 21, peripheral circuit gate oxidation films 23 and peripheral circuit grid 25 is arranged on the PMOS peripheral circuit transistor zone.
N-type diffusion layer 45 and 47 be arranged on by 3 of field oxide films around the zone of p-trap 43 in.It should be noted, between n-type diffusion layer 45 and 47, be provided with at interval.
Peripheral circuit gate oxidation films 49 with 10-50nm thickness for example (being 13.5nm in this example) is arranged on the zone of p-trap 43, and this zone is included in the zone between n-type diffusion layer 45 and 47.For example have the thick peripheral circuit grid of making by polysilicon film 50 of 250-450nm (being 350nm in this example) and be arranged on the peripheral circuit gate oxidation films 49, with partly with the part crossover of n-type diffusion layer 45 and 47.N-type diffusion layer 45 and 47, peripheral circuit gate oxidation films 49 and peripheral circuit grid 50 are realized the NMOS peripheral circuit transistor.
It should be noted that being arranged on the PMOS transistor on the identical p-substrate 1 and the structure of nmos pass transistor can realize by traditional CMOS (complementary MOS) technology.
Figure 14 is diagram produces circuit according to the constant voltage that comprises the distributor resistance circuit of the embodiment of the invention a circuit diagram.
Constant voltage as shown in figure 14 produces circuit 52 and is configured to regulate the power supply that provides from DC power supply 51.Constant voltage produce circuit 52 comprise the input (Vbat) 53 that is connected to DC power supply 51, generating circuit from reference voltage (Vref) 55, computing amplifier 57, as the p-channel type MOS transistor of output driver (below be called ' PMOS ') 59, distributor resistor 61,63 and output (Vout) 65.
Distributor resistor 63 comprises resistive element R0.Distributor resistor 61 comprises a plurality of resistances adjusting resistive element R1, R2, Ri-1 and the Ri that is connected in series.Fuse MOS transistor SW1, SW2, SWi-1 and SWi and resistance are regulated resistive element R1, R2, Ri-1 and Ri and are connected in parallel respectively.
The constant voltage of present embodiment produces circuit 52 and also comprises reading circuit 66 and the non-volatile memory cells 67 that is used for ON/OFF fuse MOS transistor SW1, SW2, SWi-1 and SWi.The output of reading circuit 66 is connected on the corresponding grid of fuse MOS transistor SW1, SW2, SWi-1 and SWi.Non-volatile memory cells 67 comprises a plurality of cell stores and ON/OFF fuse MOS transistor SW1, SW2, the SWi-1 information relevant with SWi.Reading circuit 66 is according to store status ON/OFF fuse MOS transistor SW1, SW2, SWi-1 and the SWi of non-volatile memory cells 67.
Produce in the computing amplifier 57 of circuit in constant voltage, the output of computing amplifier 57 is connected on the gate electrode of PMOS 59.Apply the inverting terminal of computing amplifier 57 from the reference voltage Vref of generating circuit from reference voltage 55.Apply on the amplifier in of computing amplifier 57 by resistor 61 and 63 voltages that output voltage produced that distribute.Resistor 61 becomes to equal reference voltage Vref with 63 distribution voltage control.
Figure 15 is that diagram comprises the circuit diagram according to the voltage detection circuit of the distributor resistance circuit of the embodiment of the invention.Should notice that in these accompanying drawings the same element of as shown in figure 14 those provides same reference number.
In voltage detection circuit 73 as shown in figure 15, distributor resistor 61,63 and anti-vibration resistive element RH are connected in series in ground potential and import between the input 68 of end voltage to be measured (input voltage Vsens).It should be noted that in the present embodiment, resistor 61 and 63 structure are arranged to identical with as shown in figure 14 resistor 61 and 63.
According to present embodiment, fuse MOS transistor SW1, SW2, SWi-1 and SWi regulate resistive element R1, R2, Ri-1 and Ri with resistance respectively and are connected in parallel.Reading circuit 66 is connected on fuse MOS transistor SW1, SW2, SWi-1 and the SWi.Non-volatile memory cells 67 is connected on the reading circuit 66.
Anti-vibration resistive element RH is arranged between resistor 61 and the ground connection.The anti-vibration of n-channel-type fuse MOS transistor SWH and anti-vibration resistive element RH are connected in parallel.The grid of anti-vibration fuse MOS transistor SWH are connected in the output of computing amplifier 57.
The inverting terminal of computing amplifier 57 is connected on the tie point between distributor resistor 61 and 63.The non-inverting input terminal of computing amplifier 57 is connected on the generating circuit from reference voltage 55, so that reference voltage Vref can apply on it.The output of computing amplifier 57 outputs to the outside by converter 69 and output (D tout) 71.
When voltage detection circuit 73 is in the high voltage acquisition mode, anti-vibration resistive element RH is closed, and when higher from the end voltage to be measured of input 68 inputs, and when being higher than reference voltage Vref by the voltage that distributor resistance 61,63 and anti-vibration resistive element RH distribute, the output of computing amplifier 57 maintains logical value 0, and this output changes into logical one by converter 69 and exports from output 71.In this case, the component voltage that is input to computing amplifier 57 inverting terminals can be expressed as follows:
{(RO)+(RH)}/{(R1)+...+(Ri-1)+(Ri)+(RO)+(RH)...sens}
When end voltage to be measured reduces and become when being lower than reference voltage Vref by the voltage that distributor resistance 61,63 and anti-vibration resistive element RH distribute, the output of computing amplifier 57 is set to logical value 1, and this output changes into logical value 0 by converter 69, to export from output 71.
When the output of computing amplifier 57 was set to logical value 1, anti-vibration fuse MOS transistor SWH connected, and distributor resistance 63 is connected to ground potential by anti-vibration fuse MOS transistor SWH, and the voltage between distributor resistance 61 and 63 reduces.Then, the output of computing amplifier 57 maintains logical value 1, and voltage detection circuit 73 falls into the low-voltage acquisition mode.It should be noted, as input voltage V SensDuring reduction, anti-vibration resistive element RH and anti-vibration fuse MOS transistor SWH are configured to prevent the output vibration of voltage detection circuit 73.
When voltage detection circuit 73 was in lower voltage detection state, the component voltage that is input to the inverting terminal of computing amplifier 57 can be expressed as follows:
(RO)/{(R1)+...+(Ri-1)+(Ri)+(RO)...sens}
Being used for changing voltage detection circuit 73 can be the input voltage V of level like this to the wake-up voltage of high voltage acquisition mode Sens, it makes that the component voltage of the inverting terminal that is input to computing amplifier 57 under the low-voltage acquisition mode can be greater than reference voltage V Ref
It should be noted, in Figure 14 and 15, by the MOS transistor of reading circuit 66, generating circuit from reference voltage 55 and computing amplifier 57 realizations; Fuse MOS transistor SW1, SW2, SWi-1 and SWi; With anti-vibration fuse MOS transistor SWH as peripheral circuit transistor according to the semiconductor device of the embodiment of the invention.Yet the invention is not restricted to the embodiments described, and it does not need all MOS transistor to implement peripheral circuit transistor as described above.
Equally, in Figure 14 and 15, by the control of reading circuit 66 and non-volatile memory cells 67, fuse MOS transistor SW1, SW2, SWi-1 and SWi can ON/OFF, so that the resistance of distributor resistance 61 can be adjusted.Like this, constant voltage produces voltage is set can adjusts of output voltage of the output voltage of circuit 53 and voltage detection circuit 73.
It should be noted, produce in circuit and the conventional voltage detection circuit in traditional constant voltage, regulate resistive element R1, R2, Ri-1 and Ri by polysilicon or metal fuse and each resistance and be connected in parallel, and do not use fuse MOS transistor SW1, SW2, SWi-1 and SWi according to the embodiment of the invention; Reading circuit 66; With non-volatile memory cells 67, and in such traditional circuit, the resistance of distributor resistor is by cutting off the fuse adjustment.
In Figure 14 and 15 graphic embodiment, switch (just, fuse MOS transistor SW1, SW2, SWi-1, SWi) in case close, then can be by opening once more by the control of reading circuit 66 and non-volatile memory cells 67, its on/off operation is difficult to realize with fuse.Like this, be used for voltage is set freely changes of output voltage that constant voltage produces the output voltage of circuit 53 and voltage detection circuit 73.
According to the preferred embodiment of the present invention, the open/close state of fuse MOS transistor SW1, SW2, SWi-1, SWi can be by the conversion of the write operation on non-volatile memory cells 66, therefore even and after semiconductor device is contained in the encapsulation, constant voltage produces the voltage that is provided with of the output voltage of the output voltage of circuit 53 and voltage detection circuit 73 and also can adjust and change.
Should also be noted that in Figure 14 and 15, be applied to constant voltage according to the distributor resistance circuit of the embodiment of the invention and produce on circuit and the voltage detection circuit; Yet, the invention is not restricted to such application, and the distributor resistance circuit also can be used the circuit of other type.
Figure 16 A-16D is the schematic diagram of diagram sixth embodiment of the invention.Figure 16 A is the plane graph of memory cell, and Figure 16 B is the plane graph of peripheral circuit transistor, and Figure 16 C is the profile that Figure 16 A A-A ' along the line cuts open the memory cell of getting, and Figure 16 D is the profile that Figure 16 B B-B ' along the line cuts open the peripheral circuit transistor of getting.
As shown in these figures, n-trap 202 is arranged on the presumptive area of p-substrate 201.The field oxide film 203 that implement device is isolated is arranged on the surface of p-substrate 201.Field oxide film 203 has for example thickness of 450-700nm (being 500nm in this example).P-type diffusion layer 205,207 and 209 be arranged on corresponding to by 203 of field oxide films around n-trap 202 in.It should be noted, between p- type diffusion layer 205 and 207, be provided with at interval, and between p- type diffusion layer 207 and 209, be provided with at interval.
Select gate oxidation films 211 to be arranged on the zone that is included on the zone of p-substrate 201 between p- type diffusion layer 205 and 207, select gate oxidation films 211 to have for example thickness of 10.0-15.0nm (being 13.5nm in this example).Have the thick selection grid of making by polysilicon film 213 of 250-450nm for example (being 350nm in this example) and be arranged on and select on the gate oxidation films 211, with partly with the part crossover of p-type diffusion layer 205 and 207.It should be noted, will introduce such as the n-type impurity of phosphorus and select grid 213, and basic phosphorus concentration can be for example about 7.0 * 10 in selecting grid 213 18To 5.0 * 10 19Atom/cm 3P- type diffusion layer 205 and 207, selection gate oxidation films 211 and selection grid 213 realize selecting transistors.
Storage gate oxidation films 215 is arranged on the surface of the p-substrate 201 that is included in the zone between p- type diffusion layer 207 and 209, and storage gate oxidation films 215 has for example thickness of 10.0-15.0nm scope (being 13.5nm in this example).Have the thick floating grid of making by polysilicon film 217 of 250-450nm scope for example (being 350nm in this example) and be arranged on the storage gate oxidation films 215, with partly with P- type diffusion layer 207 and 209 crossovers.It should be noted, will introduce in the floating grid 217, and basic phosphorus concentration can be for example about 7.0 * 10 in floating grid 217 such as the n-type impurity of phosphorus 18To 5.0 * 10 19Atom/cm 3P- type diffusion layer 207 and 209, storage gate oxidation films 215 and floating grid 217 are realized memory transistor.
Select transistor and memory transistor to realize memory cell.
Equally, p- type diffusion layer 219 and 221 be arranged on corresponding to 203 of field oxide films that is different from memory cell region around another regional n-trap 202 in.It should be noted, between p- type diffusion layer 219 and 221, be provided with at interval.
Peripheral circuit gate oxidation films 223 is arranged on the zone of p-substrate 201, and this zone is included in the zone between p- type diffusion layer 219 and 221, and the thickness of peripheral circuit gate oxidation films 223 for example is 10.0-15.0nm (being 13.5nm in this example).For example the peripheral circuit grid of being made by polysilicon 225 that 250-450nm (being 350nm in this example) is thick are arranged on the peripheral circuit gate oxidation films 223, with partly with the part crossover of p-type diffusion layer 219 and 221.It should be noted, can be introduced in the peripheral circuit grid 225 than the higher concentration of phosphorus concentration in selecting grid 213 and floating grid 217 that basic phosphorus concentration for example can be at least 1.0 * 10 in peripheral circuit grid 225 such as the n-type impurity of phosphorus 20Atom/cm 3P- type diffusion layer 219 and 221, memory circuit gate oxidation films 223 and peripheral circuit grid 225 are realized peripheral circuit transistor.
In the present embodiment, the impurity concentration in floating grid 217 is arranged to be lower than the impurity concentration in the peripheral circuit grid 225, so that can improve the charge-retention property of memory transistor.
Equally, in the present embodiment, the impurity concentration in peripheral circuit grid 225 is arranged to be higher than the impurity concentration in the floating grid 217, so that the resistance of peripheral circuit grid 225 can be very low, reduces to prevent the peripheral circuit transistor processing speed.
Figure 17 is the schematic diagram of displaying according to the charge-retention property of the memory transistor of the embodiment of the invention.It should be noted that in this schematic diagram, vertical axis is represented the critical voltage of memory transistor, and trunnion axis is represented elapsed time (h).In graphic example, under 250 ℃ temperature, carry out heat treatment, and as an example, having basic phosphorus concentration is 3.0 * 10 19Atom/cm 3The memory transistor of floating grid as according to the memory transistor of the embodiment of the invention, be 3.0 * 10 and have basic phosphorus concentration 19Atom/cm 3The memory transistor of floating grid as comparative example.It should be noted in comparative example, be dispersed in by phosphorus deposition and heat and introduce phosphorus in the floating grid.
As shown in Figure 17, in memory transistor, can improve charge-retention property, wherein in floating grid, introduce phosphorus with the concentration low than comparative example according to the embodiment of the invention.
Figure 18 is a circuit diagram of showing the exemplary matrix arrangements of the 6th embodiment memory cell.
In graphic layout, memory cell is arranged to matrix.Particularly, (word line WL direction) becomes the selection grid 213 of the point ' ' of delegation to be electrically connected on the common word line WLi with in the horizontal direction for unit i0, i1.Equally, p-type diffusion layer 205 is electrically connected on the common source line SLi.Unit 0i, 1i and the p-type diffusion layer 209 that is arranged in the point ' ' on the vertical direction (bit line Bit direction) are electrically connected on the common bit lines Biti.It should be noted that in above-mentioned description, i represents 0 or natural number.
In the present embodiment, carry out erase operation by ultraviolet irradiation, so that all unit can be wiped immediately.
In write operation, only on unit 00, carry out and write, for example, word line WL0 and the bit line Bit0 that is connected on the unit 00 that carries out write operation is biased into predetermined potential-Vpp, and other word line WLi, other bit line Biti and source line SLi are biased into 0V.Like this, by the storage gate oxidation films, electronics can be injected in the floating grid 217 of unit 00, so that can carry out write operation on unit 00.
Figure 19 A to 19C is the profile that the exemplary processes step of the memory cell of the 6th embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 19 A to 19C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 16 C and the 16D.Below, with reference to Figure 16 A-16D and Figure 19 A-19C the memory cell of making the 6th embodiment and the exemplary method of peripheral circuit transistor are described.
(1) after creating n-trap 202 on the p-substrate 201, field oxide film 3 is arranged on the p-substrate 201 by traditional LOCOS (selective oxidation silicon) technology, isolates (seeing Fig. 4 A and 4B) with implement device.Thickness is that the gate oxidation films 211,215,223 of for example 13.5nm is arranged on the surface of the active area that is defined by field oxide film 203, and carries out channel doping.Then, the polysilicon film of non-doping is arranged on the p-substrate 201, and by 5.0 * 10 15Atom/cm 2Inject by ion, phosphorus is injected in the un-doped polysilicon film to create polysilicon film 227 (seeing Figure 19 A).
(2) covering memory transistor formation distinguishes and selects transistor formation region and form HTO (high-temperature oxydation) film 229 that has opening portion in the district at peripheral circuit transistor to be arranged on the polysilicon film 227.Then, PGS (phosphosilicate glass, not shown) is deposited on polysilicon film 227 and the HTO film 229, and in peripheral circuit transistor formation district phosphorus heat is distributed on the polysilicon film 227, to create polysilicon film 231 (seeing Figure 19 B).
(3) after removing PGS and HTO film 229, carry out optical-mechanical technology and etching, to select transistor area to be created in field oxide film 203 and the selection grid of selecting on the gate oxidation films 211 213 from polysilicon film 227, be created in floating grid 217 on field oxide film 203 and the storage gate oxidation films 215 from polysilicon film 227 in the memory transistor zone, be created in the peripheral circuit grid 225 (seeing Figure 19 C) on field oxide film 203 and the peripheral circuit gate oxidation films 223 in the peripheral circuit transistor zone from polysilicon film 231.
It should be noted, according to an embodiment, after removing PGS and HTO film 229, the HTO film can be arranged on polysilicon film 227 and 231, and can and be etched on HTO film and polysilicon film 227 and 231 by optical-mechanical technology and carry out composition, select to create the HTO film figure on grid 213, floating grid 217 and the peripheral circuit grid 225.Like this, at the BF that carries out subsequently 2In the injection technology, can prevent BF 2Be injected into and select in grid 213, floating grid 217 and the peripheral circuit grid 225.Impurity injects protecting film, such as aforesaid HTO film, is not suitable for injecting under the situation of the polysilicon gate of being created by composition technology at impurity, can be arranged on the polysilicon film before carrying out composition technology.In this case, on impurity injection protecting film and polysilicon film, carry out composition to form the pattern of layering, so that can prevent that in technology afterwards impurity is injected in the polysilicon gate.
(4) then, utilize and select grid 213, floating grid 217 and peripheral circuit grid 225, BF as mask 2Inject by the ion injection mode, to set up p-type diffusion layer 205,207,209 and 221 (seeing Figure 16 A-16D).
According to present embodiment, the impurity concentration in selecting grid 213 is arranged to equal the impurity concentration of floating grid 217, and therefore, and two grid 213 and 217 can be created simultaneously.Establishment selection grid 213, floating grid 217 and peripheral circuit grid 225 are relatively created the required technology amount of these grid and can be reduced like this, with respectively.
Figure 20 A to 20D is the schematic diagram of diagram seventh embodiment of the invention.Figure 20 A is the plane graph of memory cell, and Figure 20 B is the plane graph of peripheral circuit transistor, and Figure 20 C is the profile that Figure 20 A A-A ' along the line cuts open the memory cell of getting, and Figure 20 D is the profile that Figure 20 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that same element provides same reference number shown in Figure 16 A-16D, and omitted description of them.
Present embodiment is different from the 6th embodiment part and is, is incorporated in the polysilicon of selecting grid 233 and floating grid 235 such as the p-type impurity of boron, and opposite the 6th embodiment phosphorus is not incorporated in these grid.For example, the boron concentration in selecting grid 233 and floating grid 235 can be 7.0 * 10 18To 5.0 * 10 19Atom/cm 3
According to present embodiment, the impurity concentration in the floating grid 235 is arranged to be lower than the impurity concentration in the peripheral circuit grid 225, and therefore, can improve the charge-retention property of memory transistor.
Equally, according to present embodiment, because the impurity concentration of peripheral circuit grid 225 is arranged to be higher than the impurity concentration of floating grid 235, so the resistance of peripheral circuit grid 225 can be very low, so that prevent to reduce the processing speed of peripheral circuit transistor.
Figure 21 A to 21C is the profile that the exemplary processes step of the memory cell of the 7th embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 21 A to 21C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 20 C and the 20D.Below, with reference to Figure 20 A-20D and Figure 21 A-21C the memory cell of making the 7th embodiment and the exemplary method of peripheral circuit transistor are described.
(1) n-trap 202, field oxide film 203 (seeing Figure 20 C and 20D) and gate oxidation films 211,215 and 223 are arranged on the p-substrate 201, and carry out channel doping by being similar to as top with reference to the described technology of Figure 21 A.Then, on p-substrate 201, set up un-doped polysilicon film 237 (seeing Figure 21 A).
(2) HTO film 229 is arranged on the non-polysilicon film 237, and HTO film 229 covers memory transistor and forms the district and select transistor formation region, and has opening portion in peripheral circuit transistor formation district.Then, the PGS (not shown) is deposited on polysilicon film 227 and the HTO film 229, and phosphorus is distributed to by heat on the un-doped polysilicon film 237 in peripheral circuit transistor formation district, to create polysilicon film 231 (seeing Figure 21 B).
(3) after optionally removing PGS and HTO film 229, on un-doped polysilicon film 237 and polysilicon film 231, carry out optical-mechanical technology and etching, to select transistor area to be created in field oxide film 203 and the selection grid of selecting on the gate oxidation films 211 233 from un-doped polysilicon film 237, be created in the floating grid 235 on field oxide film 203 and the storage gate oxidation films 215 in the memory transistor zone from un-doped polysilicon film 237, be created in the peripheral circuit grid 225 (seeing Figure 21 C) on field oxide film 203 and the peripheral circuit gate oxidation films 223 in the peripheral circuit transistor zone from polysilicon film 231.
(4) utilize selection grid 233, floating grid 235 and peripheral circuit grid 225 as mask, BF 2With 3.0 * 10 15To 5.0 * 10 15Atom/cm 3Concentration inject by the ion injection mode, to set up p-type diffusion layer 205,207,209,219 and 221.Equally, selecting to carry out boron injection (seeing Figure 20 A-20D) on grid 233 and the floating grid 235.
According to present embodiment, select the impurity concentration of grid 233 to be arranged to equal the impurity concentration of floating grid 235, and therefore, two grid 233 and 235 can be created simultaneously.Establishment selection grid 233, floating grid 235 and peripheral circuit grid 225 relatively can reduce the required technology amount of these grid of creating like this, with respectively.
Figure 22 A to 22D is the schematic diagram of diagram eighth embodiment of the invention.Figure 22 A is the plane graph of memory cell, and Figure 22 B is the plane graph of peripheral circuit transistor, and Figure 22 C is the profile that Figure 22 A A-A ' along the line cuts open the memory cell of getting, and Figure 22 D is the profile that Figure 22 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that in these accompanying drawings, same element provides same reference number shown in Figure 16 A-16D, and omitted description of them.
Present embodiment is different from the 6th embodiment part and is, selects grid 239 and peripheral circuit grid 225 to create simultaneously.N-type impurity such as phosphorus is incorporated in the selection grid 239 with the concentration that is higher than floating grid 217, and selects grid 239 interior basic phosphorus concentrations to be arranged at least 1.0 * 10 20Atom/cm 3
According to present embodiment, because the impurity concentration in the floating grid 217 is arranged to be lower than the impurity concentration as in the peripheral circuit grid 225 in the 6th embodiment, so can improve the charge-retention property of memory transistor.
Equally, according to present embodiment, because the impurity concentrations in peripheral circuit grid 225 and the selection grid 239 are arranged to be higher than the impurity concentration of floating grid 217, so the resistance of peripheral circuit grid 225 and selection grid 239 can be very low, so that prevent to reduce peripheral circuit transistor and select transistorized processing speed.
Figure 23 A to 23C is the profile that the exemplary processes step of the memory cell of the 8th embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 23 A to 23C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 22 C and the 22D.Below, with reference to Figure 22 A-22D and Figure 23 A-23C the memory cell of making the 8th embodiment and the exemplary method of peripheral circuit transistor are described.
(1) n-trap 202, field oxide film 203 (seeing Figure 22 C and 22D), gate oxidation films 211,215 and 223 and polysilicon film 227 be arranged on the p-substrate 201 by the technology that is similar to as the described processing step of reference Figure 19 A (1).
(2) HTO film 241 is arranged on the polysilicon film 227, and HTO film 241 covers memory transistor and forms the district and selecting to have opening portion in transistor formation region territory and the peripheral circuit transistor formation district.Then, the PGS (not shown) is deposited on polysilicon film 227 and the HTO film 241, and forms on district and the selection transistor formation region at peripheral circuit transistor, and phosphorus is distributed on the polysilicon film 227 by heat, to create polysilicon film 231 (seeing Figure 23 B).
(3) after removing PGS and HTO film 241, on polysilicon film 227 and polysilicon film 231, carry out optical-mechanical technology and etching, be created in field oxide film 203 and the floating grid of storing on the gate oxidation films 215 217 with the memory transistor zone from polysilicon film 227, selecting transistor area to be created in field oxide film 203 from polysilicon film 231 and selecting selection grid 239 on the gate oxidation films 231, at the peripheral circuit grid 225 (seeing Figure 23 C) that are created in from polysilicon film 231 on the peripheral circuit transistor zone on field oxide film 203 and the peripheral circuit gate oxidation films 223.
It should be noted according to an embodiment, after removing PGS and HTO film 241, the HTO film can be arranged on polysilicon film 227 and 231, carry out composition technology by optical-mechanical technology on HTO film and polysilicon film 227 and 231 with being etched in, to select the creating HTO film figure on grid 239, floating grid 217 and the peripheral circuit grid 225.Like this, can prevent the BF that carried out afterwards 2In the injection technology BF 2Be injected into and select in grid 239, floating grid 217 and the peripheral circuit grid 225.
(4) then, utilize and select grid 213, floating grid 217 and peripheral circuit grid 225, BF as mask 2Inject by ion implantation technology, to set up p-type diffusion layer 205,207,209,219 and 221 (seeing Figure 22 A-22D).
According to present embodiment, select the impurity concentration of grid 239 to be arranged to equal the impurity concentration of floating grid 225, and therefore, can create this two grid 225 and 239 simultaneously.Like this, creating the required technology amount of grid can reduce with the situation ratio of creating selection grid 239, floating grid 217 and peripheral circuit grid 225 respectively.
Figure 24 A to 24D is the schematic diagram of diagram ninth embodiment of the invention.Figure 24 A is the plane graph of memory cell, and Figure 24 B is the plane graph of peripheral circuit transistor, and Figure 24 C is the profile that Figure 24 A A-A ' along the line cuts open the memory cell of getting, and Figure 24 D is the profile that Figure 24 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that same element provides same reference number shown in Figure 16 A-16D, 20A-20D and Figure 22 A-22D, and has omitted description of them.
Present embodiment is different from the 7th embodiment part and is, selects grid 239 and peripheral circuit grid 225 to create simultaneously, and selects in the grid 239 to be incorporated into than the high concentration of impurity concentration in the floating grid 235 such as the n-type impurity of phosphorus.Select in the grid 239 basic phosphorus concentrations for example can be set at least 1.0 * 10 20Atom/cm 3
According to present embodiment, the impurity concentration in the floating grid 235 is arranged to be lower than the impurity concentration as in the peripheral circuit grid 225 in the 7th embodiment, and therefore, can improve the charge-retention property of memory transistor.
Equally, according to present embodiment, because the impurity concentrations in peripheral circuit grid 225 and the selection grid 239 are arranged to be higher than the impurity concentration in the floating grid 235, peripheral circuit grid 225 and selection grid 239 resistance can fully reduce, so that can prevent the reduction of peripheral circuit transistor and selection transistor processing speed.
Figure 25 A to 25C is the profile that the exemplary processes step of the memory cell of the 9th embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 25 A to 25C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 24 C and the 24D.Below, with reference to Figure 24 A-24D and Figure 25 A-25C the memory cell of making the 9th embodiment and the exemplary method of peripheral circuit transistor are described.
(1) n-trap 202, field oxide film 203 (seeing Figure 24 C and 24D), gate oxidation films 211,215,223 and un-doped polysilicon film 237 are arranged on the p-substrate 201 by the technology that is similar to as reference Figure 23 A (seeing Figure 25 A) described processing step (1).
(2) HTO film 241 is arranged on the un-doped polysilicon film 237, and HTO film 237 covers memory transistor and forms the district and distinguish and select to have opening portion on the transistor formation region in peripheral circuit transistor formation.Then, the PGS (not shown) is deposited on un-doped polysilicon film 237 and the HTO film 241, and form on district and the selection transistor formation region at peripheral circuit transistor, phosphorus is distributed on the un-doped polysilicon film 237 by heat, to create polysilicon film 231 (seeing Figure 25 B).
(3) after removing PGS and HTO film 241, on un-doped polysilicon film 237 and polysilicon film 231, carry out optical-mechanical technology and etching, to be created in the floating grid 235 on field oxide film 203 and the storage gate oxidation films 215 from un-doped polysilicon film 237 in the memory transistor zone, selecting on the transistor area to be created in field oxide film 203 from polysilicon film 231 and selecting selection grid 239 on the gate oxidation films 211, at the peripheral circuit grid 225 (seeing Figure 25 C) that are created in from polysilicon film 231 on the peripheral circuit transistor zone on field oxide film 203 and the peripheral circuit gate oxidation films 223.
(4) utilize to select grid 239, floating grid 235 and peripheral circuit grid 225 as mask, by with for example 3.0 * 10 15To 5.0 * 10 15Atom/cm 3The concentration ion inject, inject BF 2To set up p-type diffusion layer 205,207,209,219 and 221.Equally, boron is injected in the floating grid 235 and (sees Figure 24 A-24D).
According to present embodiment, select the impurity concentration in the grid 239 to be arranged to equal the impurity concentration of peripheral circuit grid 225, and therefore, can create this two grid 239 and 225 simultaneously.Like this, creating the required technology amount of grid can reduce with the situation ratio of creating selection grid 239, floating grid 235 and peripheral circuit grid 225 respectively.
Figure 26 A to 26D is the schematic diagram of diagram tenth embodiment of the invention.Figure 26 A is the plane graph of memory cell, and Figure 26 B is the plane graph of peripheral circuit transistor, and Figure 26 C is the profile that Figure 26 A A-A ' along the line cuts open the memory cell of getting, and Figure 26 D is the profile that Figure 26 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that same element provides same reference number shown in Figure 16 A-16D, and omitted description of them.
According to present embodiment, n-trap 202 is created on the presumptive area on the p-substrate 201, and field oxide film 203 is arranged on the surface on the p-substrate 201.
The selection transistor of being realized by p-type diffusion layer 205,207, selection gate oxidation films 243 and selection grid 213 is arranged on the selection transistor area.
The memory transistor of being realized by p-type diffusion layer 207,209, storage gate oxidation films 245 and floating grid 217 is arranged on the storage crystal area under control.
The peripheral circuit transistor of being realized by p- type diffusion layer 219 and 221, peripheral circuit gate oxidation films 247 and peripheral circuit grid 225 is arranged in the peripheral circuit transistor district.
In the present embodiment, select gate oxidation films 243 and storage gate oxidation films 245 to create with same method.Peripheral circuit gate oxidation films 247 is created with the technology different with the technology of creating selection gate oxidation films 243 and storage gate oxidation films.Select gate oxidation films 243 and storage gate oxidation films 245 can be arranged to for example thickness of 6.0-10.0nm (being 7.5nm in this example).Peripheral circuit gate oxidation films 247 can be arranged to for example thickness of 10.0-15.0nm (being 13.5nm in this example).
Silicon oxide film 249 is arranged on the surface of selecting grid 213 and floating grid 217.
In the present embodiment, the impurity concentration in the floating grid 217 is arranged to be lower than the impurity concentration as in the peripheral circuit grid 225 in the 6th embodiment, and therefore, can improve the charge-retention property of memory transistor.
Equally, in the present embodiment, impurity concentration in the peripheral circuit grid 225 is arranged to be higher than the impurity concentration in the floating grid 217, and therefore, the resistance of peripheral circuit grid 225 can reduce fully so that prevent to reduce peripheral circuit transistor and select transistorized processing speed.
Equally, in the present embodiment, storage gate oxidation films 245 is arranged to thinner than peripheral circuit gate oxidation films 247.Therefore, peripheral circuit gate oxidation films 247 can be arranged to fully thick so that can prevent its damage when on memory transistor, carrying out write operation, and the storage gate oxidation films can be arranged to fully thin so that on memory transistor, can obtain good write attribute.Therefore can be suitable on memory transistor, carrying out write operation, and prevent that peripheral circuit gate oxidation films 247 from damaging and prevention punctures generation rapidly.
Figure 27 A to 27C is the profile that the exemplary processes step of the memory cell of the tenth embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 27 A to 27C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 26 C and the 26D.Below, with reference to Figure 26 A-26D and Figure 27 A-27C the memory cell of making the tenth embodiment and the exemplary method of peripheral circuit transistor are described.
(1) after creating n-trap 202 on the p-substrate 201, field oxide film 203 is arranged on the p-substrate on 201, with implement device isolation (seeing Figure 26 A and 26B) by traditional LOCOS (selective oxidation silicon) technology.Thickness is that the gate oxidation films 243 and 245 of for example 7.5nm is arranged on the surface of the active area that is defined by field oxide film 203, and carries out channel doping.Then, the un-doped polysilicon film is arranged on the p-substrate 201, with 5.0 * 10 15Atom/cm 3Concentration inject by ion phosphorus be injected into the un-doped polysilicon film, to create polysilicon film.By optical-mechanical technology be etched on the polysilicon film and carry out composition technology, to be created in the field oxide film of selecting on the transistor area 203 and to select the selection grid 213 on the gate oxidation films 243, the floating grid 217 on field oxide film on the storage crystal area under control 203 and storage gate oxidation films 245.Then, utilize field oxide film 203, selection grid 213 and floating grid 217 as mask, to remove p-substrate 201 lip-deep oxide-films.When removing oxide-film, can use optical-mechanical technology, select transistor area and storage crystal area under control (seeing Figure 27 A) to cover.
(2) creating thickness by thermal oxidation is the gate oxidation films 247 of for example 13.5nm.In this case, silicon oxide film 249 is created on the surface of selecting grid 213 and floating grid 217.Then, un-doped polysilicon is arranged on the p-substrate 201, and PGS (not shown) deposition thereon, and after this phosphorus is distributed in the un-doped polysilicon film to create polysilicon film 231 (seeing Figure 27 B) by heat.
(3) after removing PGS, on peripheral circuit transistor, pass through optical-mechanical technology and etching, from creating peripheral circuit grid 225 (seeing Figure 27 C) at field oxide film 203 and peripheral circuit gate oxidation films 247 from polysilicon film 231.
(4) then, utilize and select grid 213, floating grid 217 and peripheral circuit grid 225, inject, inject BF by ion as mask 2To create p-type diffusion layer 205,207,209 and 221 (seeing Figure 26 A-26D).
According to present embodiment, select impurity concentrations in the grid 213 to be arranged to equal impurity concentration in the floating grid 217.And therefore, two grid 213 and 217 can be created simultaneously.Like this, creating the required technology amount of these grid can reduce with the situation ratio of creating selection grid 213, floating grid 217 and peripheral circuit grid 225 respectively.
Equally, in the present embodiment, select gate oxidation films 243 to be arranged to and to store gate oxidation films 245 and have identical thickness, and therefore, two gate oxidation films 243 and 245 can be created simultaneously, create the required technology amount of gate oxidation films and create respectively and select the situation ratio of gate oxidation films 243, storage gate oxidation films 245 and peripheral circuit gate oxidation films 247 to reduce.
Figure 28 A to 28D is the schematic diagram of diagram eleventh embodiment of the invention.Figure 28 A is the plane graph of memory cell, and Figure 28 B is the plane graph of peripheral circuit transistor, and Figure 28 C is the profile that Figure 28 A A-A ' along the line cuts open the memory cell of getting, and Figure 28 D is the profile that Figure 28 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that same element provides same reference number shown in Figure 16 A-16D, Figure 20 A-20D and Figure 26 A-26D, and has omitted description of them.
Present embodiment is different from the 6th embodiment part and is, p-type impurity such as phosphorus is introduced and selected in grid 233 and the floating grid 235, but phosphorus is not introduced as in these grid in the tenth embodiment.For example, the concentration of boron can be 7.0 * 10 in selecting grid 233 and floating grid 235 18To 5.0 * 10 19Atom/cm 3
Silicon oxide film 249 is arranged on the surface of selecting grid 233 and floating grid 235.
According to present embodiment, the impurity concentration in the floating grid 235 is arranged to be lower than the impurity concentration as in the peripheral circuit grid 225 in the 7th embodiment, and therefore, can improve the charge-retention property of memory transistor.Equally, because the impurity concentration in the peripheral circuit grid 225 is arranged to be higher than the impurity concentration in the floating grid 235, so the resistance of peripheral circuit grid 225 can be low fully, so that prevent to reduce the processing speed of peripheral circuit transistor.
Equally, in the present embodiment, storage gate oxidation films 245 is arranged to thinner than peripheral circuit gate oxidation films 247, and therefore, can be suitable for carrying out write operation on memory transistor, and prevents that peripheral circuit gate oxidation films 247 from damaging and preventing to puncture rapidly generation.
Figure 29 A to 29C is the profile that the exemplary processes step of the memory cell of the 17 embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 29 A to 29C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 28 C and the 28D.Below, with reference to Figure 28 A-28D and Figure 29 A-29C the memory cell of making the 11 embodiment and the exemplary method of peripheral circuit transistor are described.
(1) after creating n-trap 202 on the p-substrate 201, field oxide film 203 is arranged on the p-substrate 201 by traditional LOCOS (selective oxidation silicon) technology, isolates (seeing Figure 28 A and 28B) with implement device.Thickness is that the gate oxidation films 243 and 245 of for example 7.5nm is arranged on by on the surfaces of active regions of field oxide film 203 definition and carry out channel doping.Then, the un-doped polysilicon film is arranged on the p-substrate 201.Then, by optical-mechanical technology be etched on the un-doped polysilicon film and carry out composition technology, to be created in the field oxide film of selecting on the transistor area 203 and to select the selection grid 233 on the gate oxidation films 243, the floating grid 235 on field oxide film on the storage crystal area under control 203 and storage gate oxidation films 245.Then, utilize field oxide film 203, select grid 233 and floating grid 235, be arranged on p-substrate 201 lip-deep oxide-films to remove as mask.When removing oxide-film, can use optical-mechanical technology to select transistor area and storage crystal area under control (seeing Figure 29 A) to cover.
(2) gate oxidation films 247, silicon oxide film 249 and polysilicon film 231 are created (seeing Figure 29 B) by the technology that is similar to the processing step of describing with reference to figure 27B.
(3) technology by the processing step (3) described with reference to figure 27C above being similar to is created peripheral circuit transistor 225 (seeing Figure 29 C) on field oxide film 203 and peripheral circuit gate oxidation films 247 on the peripheral circuit transistor zone.
(4) then, utilize and select grid 233, floating grid 235 and peripheral circuit grid 225, inject, inject BF by ion as mask 2, to realize 3.0 * 10 15To 5.0 * 10 15Atom/cm 3Concentration, to create p-type diffusion layer 205,207,209,219 and 221.Equally, selecting to carry out boron injection (seeing Figure 28 A-28D) on grid 233 and the floating grid 235.
According to present embodiment, select the impurity concentration of grid 233 to be arranged to equal the impurity concentration of floating grid 235, and therefore, can create this two grid 233 and 235 simultaneously.Like this, can reduce than creating the required technology amount of these grid with the situation of creating selection grid 233, floating grid 235 and peripheral circuit grid 225 respectively.
Equally, according to present embodiment, select gate oxidation films 243 to be arranged to identical thickness, and therefore, can create this two gate oxidation films 243 and 245 simultaneously with storage gate oxidation films 245.Like this, can reduce than creating the required technology amount of these gate oxidation films with the situation of creating selection gate oxidation films 243, storage gate oxidation films 245 and peripheral circuit gate oxidation films 247 respectively.
Figure 30 A to 30D is the schematic diagram of diagram twelveth embodiment of the invention.Figure 30 A is the plane graph of memory cell, and Figure 30 B is the plane graph of peripheral circuit transistor, and Figure 30 C is the profile that Figure 30 A A-A ' along the line cuts open the memory cell of getting, and Figure 30 D is the profile that Figure 30 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that same element provides same reference number shown in Figure 16 A-16D and Figure 26 A-26D, and has omitted description of them.
Above being different from, present embodiment is with reference to described the tenth embodiment part of Figure 26 A-26D, silicon oxide film 251 is arranged on the surface of peripheral circuit grid 225, is different from as the silicon oxide film 249 that is provided with among the tenth embodiment selecting on grid 213 and floating grid 217 surfaces.
In the present embodiment, the impurity concentration in the floating grid 217 is arranged to be lower than the impurity concentration in the peripheral circuit grid 225, and therefore, can improve the charge-retention property of memory transistor.
Equally, in the present embodiment, because the impurity concentration in the peripheral circuit grid 225 is arranged to be higher than the impurity concentration in the floating grid 217, so the resistance of peripheral circuit grid 225 can be low fully, so that prevent to reduce peripheral circuit transistor and select transistorized processing speed.
Equally, in the present embodiment, storage gate oxidation films 245 is arranged to thinner than peripheral circuit gate oxidation films 247, and therefore, can be suitable for carrying out write operation on memory transistor, and prevents that peripheral circuit gate oxidation films 247 from damaging and preventing to puncture rapidly generation.
Figure 31 A to 31C is the profile that the exemplary processes step of the memory cell of the 12 embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 31 A to 31C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 30 C and the 30D.Below, with reference to Figure 30 A-30D and Figure 31 A-31C the memory cell of making the 12 embodiment and the exemplary method of peripheral circuit transistor are described.
(1) after creating n-trap 202 on the p-substrate 201, field oxide film 203 is arranged on the p-substrate 201 by traditional LOCOS (selective oxidation silicon) technology, isolates (seeing Figure 30 A and 30B) with implement device.Thickness is that the peripheral circuit gate oxidation films 247 of for example 13.5nm is arranged on the surface of the active area that is defined by field oxide film 203, and carries out channel doping.Then, the un-doped polysilicon film is arranged on the p-substrate 201, and the PSG deposition thereon.Then, spread on the un-doped polysilicon film to create polysilicon film by hot dispersing technology phosphorus.After removing PSG, by optical-mechanical technology be etched on the polysilicon film and carry out composition technology, to be created in field oxide film 203 in the peripheral circuit transistor district and the peripheral circuit grid 225 on the peripheral circuit gate oxidation films 247.Then, utilize field oxide film 203, peripheral circuit grid 225 as mask, to remove the oxide-film that is arranged on the p-substrate 201.In one embodiment, when removing oxide-film, utilize optical-mechanical technology can cover peripheral circuit transistor district (seeing Figure 31 A).
(2) thickness is that the gate oxidation films 243 and 245 of for example 7.5nm is created by carrying out thermal oxidation technology.In this case, silicon oxide film 251 is created on the peripheral circuit grid 225.Then, the un-doped polysilicon film is arranged on the p-substrate 201.After this, phosphorus is injected in the un-doped polysilicon film to realize 5.0 * 10 15Atom/cm 3Concentration to create polysilicon film 227 (seeing Figure 31 B).
(3) by optical-mechanical technology and etching, select transistor area from polysilicon film 227 at field oxide film 203 with select gate oxidation films 243 to create and select grid 213, and create floating grids 217 (seeing Figure 31 C) from polysilicon film 227 at field oxide film 203 and storage gate oxidation films 245 in the storage crystal area under control.
In one embodiment, before carrying out composition technology, the HTO film can be arranged on the polysilicon film 227, and by optical-mechanical technology and etching, can on HTO film and polysilicon film 227, carry out composition technology, to select the creating HTO film figure on grid 213 and the floating grid hurdle 217.Like this, can prevent BF 2Be injected at BF 2Among selection grid 213 and floating grid hurdle 217 in.
(4) then, utilize and select grid 213, floating grid 217 and peripheral circuit grid 225, inject, inject BF by ion as mask 2To create p-type diffusion layer 205,207,209,219 and 221 (seeing Figure 30 A-30D).
According to present embodiment, select impurity concentrations in the grid 213 to be arranged to equal impurity concentration in the floating grid 217, and therefore, can create this two grid 213 and 217 simultaneously.Like this, can reduce than creating the required technology amount of these grid with the situation of creating selection grid 213, floating grid 217 and peripheral circuit grid 225 respectively.
Equally, in the present embodiment, select gate oxidation films 243 to be arranged to the identical thickness of storage gate oxidation films 245, and therefore, can create this two grid 243 and 245 simultaneously, and can reduce than creating the required technology amount of these grid with the situation of creating selection grid 243, storage gate oxidation films 245 and peripheral circuit gate oxidation films 247 respectively.
Figure 32 A to 32D is the schematic diagram of diagram thriteenth embodiment of the invention.Figure 32 A is the plane graph of memory cell, and Figure 32 B is the plane graph of peripheral circuit transistor, and Figure 32 C is the profile that Figure 32 A A-A ' along the line cuts open the memory cell of getting, and Figure 32 D is the profile that Figure 32 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that same element provides same reference number and omitted description of them shown in Figure 16 A-16D, Figure 20 A-20D, Figure 26 A-26D and Figure 30 A-30D.
Present embodiment is with reference to described the 12 embodiment part of Figure 30 A-30D above being different from, and is incorporated in the polysilicon of selecting grid 233 and floating grid 235 such as the p-type impurity of boron, replace as in the 12 embodiment phosphorus introduce the there.For example, the boron concentration in selecting grid 233 and floating grid 235 can be 7.0 * 10 18To 5.0 * 10 19Atom/cm 3
In the present embodiment, the impurity concentration in the floating grid 235 is arranged to be lower than as above-mentioned with reference to the impurity concentration in the described peripheral circuit grid 225 of Figure 20 A-20D in the 7th embodiment, and therefore, can improve the charge-retention property of memory transistor.Equally, because the impurity concentration in the peripheral circuit grid 225 is arranged to be higher than the impurity concentration in the floating grid 235,, and can prevent the reduction of the processing speed of peripheral circuit transistor so the resistance of peripheral circuit grid 225 can be low fully.
Equally, in the present embodiment, storage gate oxidation films 245 is arranged to than in the tenth embodiment as above-mentioned thin with reference to the described peripheral circuit gate oxidation films of Figure 26 A-26D 247, and therefore, can be suitable on memory transistor, carrying out write operation, and prevent that peripheral circuit gate oxidation films 247 from damaging and preventing to puncture rapidly generation.
Figure 33 A to 33C is the profile that the exemplary processes step of the memory cell of the 13 embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 33 A to 33C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 32 C and the 32D.Below, with reference to Figure 32 A-32D and Figure 33 A-33C the memory cell of making the 13 embodiment and the exemplary method of peripheral circuit transistor are described.
(1) n-trap 202, field oxide film 203 (seeing Figure 32 A and 32B), peripheral circuit gate oxidation films 247 and peripheral circuit grid 225 are created (seeing Figure 33 A) by being similar to as above with reference to the technology of the described processing step of Figure 31 A (1).
(2) thickness is that the gate oxidation films 243 and 245 of for example 7.5nm is created by thermal oxidation technology.In this case, silicon oxide film 51 is arranged on the surface of peripheral circuit grid 225.Then, un-doped polysilicon film 237 is arranged on the p-substrate 201 and (sees Figure 33 B).
(3), select grid 233 to be created on the field oxide film 203 and selection gate oxidation films 243 of selecting transistor area from un-doped polysilicon film 237 by optical-mechanical technology and etching.And on floating grid 235 is created in field oxide film 203 and storage gate oxidation films 245 on the storage crystal area under control from un-doped polysilicon film 237 (seeing Figure 33 C).
(4) utilize selection grid 233, floating grid 235 and peripheral circuit grid 225 as mask, by ion implantation technology, BF2 is with 3.0 * 10 15To 5.0 * 10 15Atom/cm 3Concentration inject, to create p-type diffusion layer 205,207,209,219 and 221.Equally, selecting to inject boron (seeing Figure 32 A-32D) on grid 233 and the floating grid 235.
According to present embodiment, select the impurity concentration of grid 233 to be arranged to equal the impurity concentration of floating grid 235, and therefore, can create two grid 233 and 235 simultaneously.Like this, can reduce the required technology amount of these grid of creating with the situation ratio of creating selection grid 233, floating grid 235 and peripheral circuit grid 225 respectively.
Equally, in the present embodiment, select gate oxidation films 243 to be arranged to and to store gate oxidation films 245 and have identical thickness, and therefore, two gate oxidation films 243 and 245 can be created simultaneously, like this, with situation that create to select grid 243, storage grid 245 and peripheral circuit grid 247 respectively than reducing the required technology amount of these grid of establishment.
It should be noted, in with reference to figure 26A-26D, Figure 28 A-28D, Figure 30 A-30D and the described embodiment of Figure 32 A-32D, select gate oxidation films 243 to be arranged to have identical thickness, and peripheral circuit gate oxidation films 247 is arranged to be different from the thickness of selecting gate oxidation films 243 and storage gate oxidation films 245 with storage gate oxidation films 245; Yet the invention is not restricted to such embodiment, and for example gate oxidation films 243,245 and 247 can be arranged to have identical thickness.
Figure 34 A to 34D is the schematic diagram of diagram fourteenth embodiment of the invention.Figure 34 A is the plane graph of memory cell, and Figure 34 B is the plane graph of peripheral circuit transistor, and Figure 34 C is the profile that Figure 34 A A-A ' along the line cuts open the memory cell of getting, and Figure 34 D is the profile that Figure 34 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that same element provides same reference number shown in Figure 16 A-16D, Figure 22 A-22D and Figure 26 A-26D, and has omitted description of them.
Above being different from, present embodiment is with reference to described the tenth embodiment part of Figure 26 A-26D, select gate oxidation films 253 and peripheral circuit gate oxidation films 247 to create simultaneously, and select the thickness of gate oxidation films 253 to be arranged to for example 10.0-15.0nm (being 13.5nm in this example).
Equally, in the present embodiment, select grid 239 and peripheral circuit grid 225 to create simultaneously, and be injected in the selection grid 239 with the concentration that is higher than floating grid 217 such as the n-type impurity of phosphorus.Select in the grid 239 basic phosphorus concentrations to be for example 1.0 * 10 20Atom/cm 3
In the present embodiment, the impurity concentration in floating grid 217 is arranged to be lower than the impurity concentration in the peripheral circuit 225, and therefore can improve the charge-retention property of memory transistor.
Equally, in the present embodiment, as in the 8th embodiment as above-mentionedly be arranged to be higher than impurity concentration in the floating grid with reference to the described impurity concentration in peripheral circuit grid 225 and selection grid 239 of figure 22A-22D, and therefore, the resistance of peripheral circuit grid 225 and selection grid 239 can reduce fully, so that can prevent peripheral circuit transistor and select the transistor processing speed to reduce.
Equally, in the present embodiment, storage gate oxidation films 245 is arranged to such as approaching with reference to the described peripheral circuit gate oxidation films 247 of figure 26A-26D as above-mentioned in the tenth embodiment, and therefore, can be suitable on memory transistor, carrying out write operation, and prevent from that peripheral circuit gate oxidation films 247 from damaging and puncture rapidly to take place.
Figure 35 A to 35C is the profile that the exemplary processes step of the memory cell of the 14 embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 35 A to 35C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 34 C and the 34D.Below, described with reference to Figure 34 A-34D and Figure 35 A-35C and made the memory cell of the 14 embodiment and the exemplary method of peripheral circuit transistor.
(1) n-trap 202, field oxide film 203, storage gate oxidation films 245 and floating grid 217 are created on the p-substrate 201 by the technology that is similar to as above with reference to Figure 27 A (seeing Figure 35 A) described processing step (1).
(2) thickness is the gate oxidation films 247 and 253 of for example 13.5nm, creates by carrying out thermal oxidation technology.In this case, silicon oxide film 249 is created on the surface of peripheral grid 217.Then, the un-doped polysilicon film is arranged on the p-substrate 201, and PSG (not shown) deposition thereon, and after this phosphorus is distributed on the un-doped polysilicon film to create polysilicon film 231 (seeing Figure 35 B) by heat.
(3) after removing PSG, carry out optical-mechanical technology and be etched with and selecting transistor area at field oxide film 203 with select gate oxidation films 53 to create and select grid 239 from polysilicon film 231, and on peripheral circuit grid 225 are created in field oxide film 203 and peripheral circuit gate oxidation films 247 in the peripheral circuit transistor district from polysilicon film 231 (seeing Figure 35 C).
(4) then, utilize and select grid 239, floating grid 217 and peripheral circuit grid 225, inject, inject BF by ion as mask 2To create p-type diffusion layer 205,207,209,219 and 221 (seeing Figure 34 A-34D).
According to present embodiment, select impurity concentrations in the grid 239 to be arranged to equal impurity concentration in the peripheral circuit grid 225, and therefore, can create two grid 225 and 239 simultaneously.Like this, with situation that create to select grid 239, floating grid 217 and peripheral circuit grid 225 respectively than reducing the required technology amount of these grid of establishment.
Equally, in the present embodiment, select gate oxidation films 253 to be arranged to have identical thickness with peripheral circuit gate oxidation films 247, and therefore, two gate oxidation films 247 and 253 can be created simultaneously, and with create respectively select gate oxidation films 253, storage gate oxidation films 245 and peripheral circuit gate oxidation films 247 situation than reducing the required technology amount of this gate oxidation films of establishment.
Figure 36 A to 36D is the schematic diagram of diagram fifteenth embodiment of the invention.Figure 36 A is the plane graph of memory cell, and Figure 36 B is the plane graph of peripheral circuit transistor, and Figure 36 C is the profile that Figure 36 A A-A ' along the line cuts open the memory cell of getting, and Figure 36 D is the profile that Figure 36 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that shown in Figure 16 A-16D, Figure 20 A-20D, Figure 22 A-22D, Figure 26 A-26D and Figure 34 A-34D, same element provides same reference number, and has omitted description of them.
Present embodiment is different from as top and is with reference to described the 14 embodiment part of Figure 34 A-34D, is injected in the polysilicon of floating grid 235 such as the p-type impurity of boron, and replaces as inject phosphorus there in the 14 embodiment.Select the boron concentration in the grid 235 to be for example 7.0 * 10 18To 5.0 * 10 19Atom/cm 3
Silicon oxide film 249 is arranged on the surface of floating grid 235.
According to present embodiment, the impurity concentrations in the floating grid 235 be arranged to be lower than as in the 17 embodiment with reference to the impurity concentration in the described peripheral circuit grid 225 of Figure 20 A-20D, and therefore, can improve charge-retention property in the memory circuit.
Equally, in the present embodiment, storage gate oxidation films 245 is arranged to than thin with reference to the described peripheral circuit gate oxidation films of Figure 26 A-26D 247 in the tenth embodiment, and therefore, can be suitable on memory transistor, carrying out write operation, and prevent that peripheral circuit gate oxidation films 247 from damaging and preventing to puncture rapidly generation.
Figure 37 A to 37C is the profile that the exemplary processes step of the memory cell of the 15 embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 37 A to 37C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 36 C and the 37D.Below, with reference to Figure 36 A-36D and Figure 37 A-37C the memory cell of making the 15 embodiment and the exemplary method of peripheral circuit transistor are described.
(1) n-trap 202, field oxide film 203 (seeing Figure 36 A and 36B), gate oxidation films 245 and floating grid 235 are created on the p-substrate 201 by the technology that is similar to as above with reference to Figure 29 A (seeing Figure 37 A) described processing step (1).
(2) create gate oxidation films 247,253 and silicon oxide film 249, after this, polysilicon gate 231 is created with reference to the technology of Figure 35 B (seeing Figure 37 B) described processing step (2) by being similar to as above.
(3) selection grid 239 are created in the field oxide film of selecting on the transistor area 203 and select on the gate oxidation films 253, and by being similar to above-mentioned technology with reference to the described processing step of Figure 35 C (3), peripheral circuit grid 225 are created on the field oxide film 203 and peripheral circuit gate oxidation films 247 on the peripheral circuit transistor zone (seeing Figure 37 C).
(4) then, utilize and select grid 239, floating grid 235 and peripheral circuit grid 225, inject, inject BF by ion as mask 2To realize about 3.0 * 10 15To 5.0 * 10 15Atom/cm 3Concentration, to create p-type diffusion layer 205,207,209,219 and 221.
According to present embodiment, select impurity concentrations in the grid 239 to be arranged to equal impurity concentration in the peripheral circuit grid 225, and therefore, can create two grid 225 and 239 simultaneously.Like this, with situation that create to select grid 239, floating grid 235 and peripheral circuit grid 225 respectively than reducing the required technology amount of these grid of establishment.
Equally, in the present embodiment, select gate oxidation films 253 to be arranged to have identical thickness with peripheral circuit gate oxidation films 247, and therefore, two gate oxidation films 247 and 253 can be created simultaneously.Like this, with situation that create to select gate oxidation films 253, storage gate oxidation films 245 and peripheral circuit gate oxidation films 247 respectively than reducing the required technology amount of these gate oxidation films of establishment.
Figure 38 A to 38D is the schematic diagram of diagram sixteenth embodiment of the invention.Figure 38 A is the plane graph of memory cell, and Figure 38 B is the plane graph of peripheral circuit transistor, and Figure 38 C is the profile that Figure 38 A A-A ' along the line cuts open the memory cell of getting, and Figure 38 D is the profile that Figure 38 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that shown in Figure 16 A-16D, Figure 22 A-22D, Figure 26 A-26D, Figure 30 A-30D and Figure 34 A-34D, same element provides same reference number, and has omitted description of them.
Present embodiment is different from as top and is that with reference to described the tenth embodiment part of Figure 26 A-26D silicon oxide film 249 is not arranged on the surface of floating grid 217, and silicon oxide film 251 is arranged on peripheral circuit grid 225 and selects on the surface of grid 239.
In the present embodiment, the impurity concentration in floating grid 217 be arranged to be lower than as in the 6th embodiment with reference to the impurity concentration in described peripheral circuit 225 grid of Figure 16 A-16D, therefore and can improve the charge-retention property of memory transistor.
Equally, in the present embodiment, since peripheral circuit grid 225 and select impurity concentration in the grid 239 be arranged to be higher than as in the 8th embodiment with reference to Figure 22 A-22D the impurity concentration in the described floating grid 217, the resistance of peripheral circuit 225 grid can be fully low, so that can prevent the minimizing of peripheral circuit transistor and selection transistor processing speed.
Equally, in the present embodiment, storage gate oxidation films 245 is arranged to thinner than peripheral circuit gate oxidation films 247, and therefore, can be suitable for carrying out write operation on memory transistor, and prevents that peripheral circuit gate oxidation films 247 from damaging and puncture generation rapidly.
Figure 39 A to 39C is the profile that the exemplary processes step of the memory cell of the 16 embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 39 A to 39C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 38 C and the 38D.Below, with reference to Figure 38 A-38D and Figure 39 A-39C the memory cell of making the 16 embodiment and the exemplary method of peripheral circuit transistor are described.
(1) n-trap 202, field oxide film 203 (seeing Figure 38 A and 38B), peripheral circuit gate oxidation films 247, select gate oxidation films 253, peripheral circuit grid 225 and select grid 239 to be created on the p-substrate 201 by the technology that is similar to as above with reference to Figure 31 A (seeing Figure 39 A) described processing step (1).
(2) create storage gate oxidation films 245 and silicon oxide film 251, after this, create polysilicon film 227 with reference to the technology of Figure 31 B (seeing Figure 39 B) described processing step (2) by being similar to as above.
(3) floating grid 217 is created on field oxide film 203 and the storage grid oxide-film 245 in the memory transistor zone by the technology that is similar to the above-mentioned processing step of describing with reference to figure 31C (3) and (sees Figure 39 C).
(4) then, utilize and select grid 239, floating grid 217 and peripheral circuit grid 225, inject, inject BF by ion as mask 2To create p-type diffusion layer 205,207,209,219 and 221 (seeing Figure 38 A-38D).
According to present embodiment, select impurity concentrations in the grid 239 to be arranged to equal impurity concentration in the peripheral circuit grid 225, and therefore, can create two grid 225 and 239 simultaneously.Like this, with situation that create to select grid 239, floating grid 217 and peripheral circuit grid 225 respectively than reducing the required technology amount of these grid of establishment.
Equally, in the present embodiment, select gate oxidation films 253 to be arranged to have identical thickness with peripheral circuit gate oxidation films 247, and therefore, two gate oxidation films 247 and 253 can be created simultaneously, and with create respectively select gate oxidation films 253, storage gate oxidation films 245 and peripheral circuit gate oxidation films 247 situation than reducing the required technology amount of this gate oxidation films of establishment.
Figure 40 A to 40D is the schematic diagram of diagram seventeenth embodiment of the invention.Figure 40 A is the plane graph of memory cell, and Figure 40 B is the plane graph of peripheral circuit transistor, and Figure 40 C is the profile that Figure 40 A A-A ' along the line cuts open the memory cell of getting, and Figure 40 D is the profile that Figure 40 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that shown in Figure 16 A-16D, Figure 20 A-20D, Figure 22 A-22D, Figure 26 A-26D, Figure 30 A-39-D and Figure 34 A-34D, same element provides same reference number, and has omitted description of them.
Present embodiment is different from as top and is with reference to described the 16 embodiment part of Figure 38 A-38D, replaces phosphorus to be injected in the polysilicon of floating grid 235 such as the p-type impurity of boron.Select the boron concentration in the grid 235 for example can be about 7.0 * 10 18To 5.0 * 10 19Atom/cm 3
In the present embodiment, the impurity concentration in floating grid 235 is arranged to be lower than as above-mentioned with reference to the impurity concentration in described peripheral circuit 225 grid of Figure 20 A-20D in the 7th embodiment, and therefore can improve the charge-retention property of memory transistor.
Equally, because the impurity concentration in peripheral circuit grid 225 and selection grid 239 is arranged to be higher than the impurity concentration in the floating grid 235, so the resistance in peripheral circuit 225 grid and the selection grid 239 can be fully low, and can prevent peripheral circuit transistor and the reduction of selecting the grid processing speed.
Equally, in the present embodiment, storage gate oxidation films 245 is arranged to than thin with reference to the described peripheral circuit gate oxidation films of Figure 26 A-26D 247 in the above-mentioned the tenth implements, and therefore, can be suitable on memory transistor, carrying out write operation, and prevent that peripheral circuit gate oxidation films 247 from damaging and puncture generation rapidly.
Figure 41 A to 41C is the profile that the exemplary processes step of the memory cell of the 17 embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 41 A to 41C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 40 C and the 40D.Below, described with reference to Figure 40 A-40D and Figure 41 A-41C and made the memory cell of the 17 embodiment and the exemplary method of peripheral circuit transistor.
(1) n-trap 202, field oxide film 203 (seeing Figure 40 A and 40B), peripheral circuit gate oxidation films 247, selection gate oxidation films 253, peripheral circuit grid 225 and selection grid 239 are created with reference to the technology of Figure 31 A (seeing Figure 41 A) described processing step (1) by being similar to as above.
(2) thickness is that the storage gate oxidation films 245 of for example 7.5nm is created by thermal oxidation technology.In this case, silicon oxide film 51 is arranged on peripheral circuit grid 225 and selects on the surface of grid.Then, un-doped polysilicon film 237 is arranged on the p-substrate 201 and (sees Figure 41 B).
(3) by optical-mechanical technology and etching, floating grid 235 is created on the field oxide film 203 in storage crystal area under control and the storage gate oxidation films 245 (seeing Figure 41 B) from un-doped polysilicon film 237.
(4), utilize and select grid 239, floating grid 235 and peripheral circuit grid 225, BF as mask by ion implantation technology 2With for example about 3.0 * 10 15To 5.0 * 10 15Atom/cm 3Concentration inject, to create p-type diffusion layer 205,207,209,219 and 221.Equally, boron is injected in the floating grid 235 and (sees Figure 40 A-40D).
According to present embodiment, select impurity concentrations in the grid 239 to be arranged to equal impurity concentration in the floating grid 235, and therefore, can create this two grid 239 and 235 simultaneously.Like this, can reduce than creating the required technology amount of these grid with the situation of creating selection grid 239, floating grid 235 and peripheral circuit grid 225 respectively.
Equally, in the present embodiment, select gate oxidation films 253 to be arranged to have identical thickness with peripheral circuit gate oxidation films 247, and therefore, can create this two grid 253 and 247 simultaneously, and can reduce than creating the required technology amount of these grid with the situation of creating selection gate oxidation films 253, storage gate oxidation films 245 and peripheral circuit gate oxidation films 247 respectively.
Figure 42 A to 42D is the schematic diagram of diagram eighteenth embodiment of the invention.Figure 42 A is the plane graph of memory cell, and Figure 42 B is the plane graph of peripheral circuit transistor, and Figure 42 C is the profile that Figure 42 A A-A ' along the line cuts open the memory cell of getting, and Figure 42 D is the profile that Figure 42 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that shown in Figure 16 A-16D, same element provides same reference number, and has omitted description of them.
According to present embodiment, n-trap 202 is created on the presumptive area of p-substrate 201, and field oxide film 203 is arranged on the surface of p-substrate 201.
The selection transistor of being realized by p-type diffusion layer 205,207, selection gate oxidation films 243 and selection grid 213 is arranged on the selection transistor area.
The memory transistor of being realized by p-type diffusion layer 207,209, storage gate oxidation films 245 and floating grid 217 is arranged on the selection storage crystal area under control.
The peripheral circuit transistor of being realized by p-type diffusion layer 219,221, peripheral circuit gate oxidation films 259 and peripheral circuit grid 225 is arranged in the peripheral circuit transistor district.
In the present embodiment, select gate oxidation films 255 to create simultaneously with the technology identical with carrying out oxidation technology with storage gate oxidation films 257.Peripheral circuit grid 259 are carried out oxidation technology by twice and are created with independent technology.Select gate oxidation films 255 and storage gate oxidation films 257 can be set to for example 6.0-10.0nm thick (being 7.5nm in this example).Peripheral circuit gate oxidation films 259 can be arranged to thickness and be for example 10.0-15.0nm (being 13.5nm in this example).
In the present embodiment, can obtain with as above in the 6th embodiment with reference to the similar advantageous effects of the described effect of Figure 16 A-16D.
Equally, in the present embodiment, storage gate oxidation films 257 is arranged to thinner than peripheral circuit gate oxidation films 259, therefore, peripheral circuit gate oxidation films 259 can be arranged to enough thick so that can prevent that it from damaging when carrying out write operation on memory transistor, and storage gate oxidation films 257 can be arranged to enough approach so that can obtain good write attribute on memory transistor.Like this, can be suitable on memory transistor, carrying out write operation, and prevent that peripheral circuit gate oxidation films 247 from damaging and preventing to puncture rapidly generation.
Figure 43 A to 43C is the profile that the exemplary processes step of the memory cell of the 18 embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 43 A to 43C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 42 C and the 42D.Below, with reference to Figure 42 A-42D and Figure 43 A-43C the memory cell of making the 18 embodiment and the exemplary method of peripheral circuit transistor are described.
(1) after creating n-trap 202 on the p-substrate 201, field oxide film 203 is arranged on the p-substrate 201 by traditional LOCOS (selective oxidation silicon) technology, isolates (seeing Figure 42 A and 42B) with implement device.Then, thickness is that the sacrificial oxidation film 261 of for example 6-16nm is created on the surface, source region that is defined by field oxide film 203, and carries out channel doping (seeing Figure 43 A).
(2) resist pattern 263 creates and covers peripheral circuit transistor formation district, and is selecting to have opening portion in transistor formation region and the memory transistor formation district.Then, the sacrificial oxidation film 261 on selection transistor area and memory transistor zone is utilized resist pattern 63 to make mask and is optionally removed (seeing Figure 43 B).
(3) after removing resist pattern 263, thickness is each selection gate oxidation films 255 and the storage gate oxidation films 257 of for example 7.5nm, is created on the surface of selecting the n-trap 202 on transistor area and the storage crystal area under control by carrying out thermal oxidation technology.In this technology, the sacrificial oxidation film 261 on the peripheral circuit transistor zone increases thickness to become peripheral circuit gate oxidation films 259 (seeing Figure 43 C).
(4) be similar to as above technology by execution with reference to the described processing step of Figure 19 A-19C (1) to (3), selection grid 213 are created in the field oxide film of selecting on the transistor area 203 and select on the gate oxidation films 255, floating grid 217 is created on the field oxide film 203 and storage gate oxidation films 257 on the storage crystal area under control, and peripheral circuit grid 225 are created on the field oxide film 203 and peripheral circuit gate oxidation films 259 in the peripheral circuit transistor district.Then, p-type diffusion layer 205,207,209,219 and 221 is similar to as above by execution and creates (seeing Figure 42 A-42D) with reference to the technology of the described processing step of Figure 16 A-16D (4).
Figure 44 A to 44D is the schematic diagram of diagram nineteenth embodiment of the invention.Figure 44 A is the plane graph of memory cell, and Figure 44 B is the plane graph of peripheral circuit transistor, and Figure 44 C is the profile that Figure 44 A A-A ' along the line cuts open the memory cell of getting, and Figure 44 D is the profile that Figure 44 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that shown in Figure 16 A-16D, Figure 20 A-20D and Figure 42 A-42D, same element provides same reference number, and has omitted description of them.
Present embodiment is different from as top and is with reference to described the 18 embodiment part of Figure 42 A-42D, replaces phosphorus to be injected in the polysilicon of selecting grid 233 and floating grid 235 such as the p-type impurity of boron.Select the boron concentration in grid 233 and the floating grid 235 for example can be about 7.0 * 10 18To 5.0 * 10 19Atom/cm 3
According to present embodiment, carry out as above with reference to the described processing step of Figure 43 A-43C (1) to (3), after this carry out as above with reference to Figure 20 A-20D and the described processing step of Figure 21 A-21C (1) to (4) to create memory cell and peripheral circuit transistor.
In the present embodiment, can obtain with as above in the 7th embodiment with reference to the same advantageous effects of the described effect of Figure 20 A-20D.
Equally, in the present embodiment, storage gate oxidation films 257 is arranged to thinner than peripheral circuit gate oxidation films 259, and therefore, can be suitable for carrying out write operation on memory transistor, and prevents that peripheral circuit gate oxidation films 259 from damaging and preventing to puncture rapidly generation.
Figure 45 A to 45D is the schematic diagram of diagram twentieth embodiment of the invention.Figure 45 A is the plane graph of memory cell, and Figure 45 B is the plane graph of peripheral circuit transistor, and Figure 45 C is the profile that Figure 45 A A-A ' along the line cuts open the memory cell of getting, and Figure 45 D is the profile that Figure 45 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that shown in Figure 16 A-16D, Figure 22 A-22D and Figure 42 A-42D, same element provides same reference number, and has omitted description of them.
Present embodiment is different from as top and is with reference to described the 18 embodiment part of Figure 42 A-42D, selects grid 239 and peripheral circuit grid 225 to create simultaneously, and is injected in the selection grid 239 with the concentration that is higher than in the floating grid 217 such as the n-type impurity of phosphorus.Select grid 239 interior basic phosphorus concentrations for example can be about 1.0 * 10 20Atom/cm 3
According to present embodiment, carry out as above with reference to the described processing step of Figure 43 A-43C (1) to (3), after this carry out as above with reference to Figure 22 A-22D and the described processing step of Figure 23 A-23C (1) to (4) to create memory cell and peripheral circuit transistor.
In the present embodiment, can obtain with as above in the 8th embodiment with reference to the same advantageous effects of the described effect of Figure 22 A-22D.
Equally, in the present embodiment, storage gate oxidation films 257 is arranged to thinner than peripheral circuit gate oxidation films 259, and therefore, can be suitable for carrying out write operation on memory transistor, and prevents that peripheral circuit gate oxidation films 259 from damaging and preventing to puncture rapidly generation.
Figure 46 A to 46D is the schematic diagram of diagram twentieth embodiment of the invention.Figure 46 A is the plane graph of memory cell, and Figure 46 B is the plane graph of peripheral circuit transistor, and Figure 46 C is the profile that Figure 46 A A-A ' along the line cuts open the memory cell of getting, and Figure 46 D is the profile that Figure 46 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted that shown in Figure 16 A-16D, Figure 20 A-20D, Figure 22 A-22D, Figure 24 A-24D and Figure 42 A-42D, same element provides same reference number, and has omitted description of them.
Present embodiment is different from as top and is with reference to described the 20 embodiment part of Figure 45 A-45D, replaces phosphorus to be injected in the floating grid 235 in the polysilicon such as the p-type impurity of boron.The concentration of boron for example can be about 7.0 * 10 in the floating grid 235 18To 5.0 * 10 19Atom/cm 3
According to present embodiment, carry out as above with reference to the described processing step of Figure 43 A-43C (1) to (3), after this carry out as above with reference to Figure 24 A-24D and the described processing step of Figure 25 A-25C (1) to (4) to create memory cell and peripheral circuit transistor.
In the present embodiment, can obtain with as above in the 9th embodiment with reference to the same advantageous effects of the described effect of Figure 24 A-24D.
Equally, in the present embodiment, storage gate oxidation films 257 is arranged to thinner than peripheral circuit gate oxidation films 259, and therefore, can be suitable for carrying out write operation on memory transistor, and prevents that peripheral circuit gate oxidation films 259 from damaging and preventing to puncture rapidly generation.
As above-mentioned with reference to figure 42A-42D and described the 18 embodiment of Figure 43 A-43C, as above-mentioned with reference to described the 19 embodiment of figure 44A-44D, as above-mentioned with reference to described the 20 embodiment of figure 45A-45D and as above-mentioned with reference to described the 21 embodiment of figure 46A-46D in, it is identical with the thickness of storing gate oxidation films 257 to select gate oxidation films 255 to be arranged to, and therefore two gate oxidation films 255 and 257 can be created simultaneously.Establishment selection gate oxidation films 255, storage gate oxidation films 257 and peripheral circuit gate oxidation films 259 are relatively created the required technology amount of this gate oxidation films and can be reduced like this, with respectively.
Figure 47 A to 47D is the schematic diagram of diagram twentieth embodiment of the invention.Figure 47 A is the plane graph of memory cell, and Figure 47 B is the plane graph of peripheral circuit transistor, and Figure 47 C is the profile that Figure 47 A A-A ' along the line cuts open the memory cell of getting, and Figure 47 D is the profile that Figure 47 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted, provide same reference number with element same shown in Figure 16 A-16D, and omitted description of them.
Present embodiment is different from as above and is with reference to described the 18 embodiment part of figure 42A-42D, carries out oxidation technology by twice, selects gate oxidation films 265 and peripheral circuit gate oxidation films 259 to create simultaneously.Select the thickness of gate oxidation films 265 and peripheral circuit gate oxidation films 259 for example can be approximately 10.0-15.0nm (being 13.5nm in this example).
In the present embodiment, can obtain with in the 6th embodiment as above with reference to the similar advantageous effects of the described effect of Figure 16 A-16D.
Equally, in the present embodiment, storage gate oxidation films 257 is arranged to thinner than peripheral circuit gate oxidation films 259, and therefore, can be suitable for carrying out write operation on memory transistor, and prevents that peripheral circuit gate oxidation films 247 from damaging and preventing to puncture rapidly generation.
Figure 48 A to 48C is the profile that the exemplary processes step of the memory cell of the 20 embodiment and peripheral circuit transistor is made in diagram.It should be noted that the profile of Figure 48 A to 48C cuts open the profile of getting corresponding to A-A ' along the line and B-B ' among Figure 47 C and the 47D.Below, with reference to Figure 47 A-47D and Figure 48 A-48C the memory cell of making the 18 embodiment and the exemplary method of peripheral circuit transistor are described.
(1) n-trap 202, field oxide film 203 (seeing Figure 47 A and 47B) and sacrificial oxidation film 261 are created on the p-substrate 201, and carry out channel doping by being similar to as above with reference to the technology of Figure 43 A (seeing Figure 48 A) described processing step (1).
(2) establishment covers the resist pattern 263 of selecting transistor area and peripheral circuit transistor to form the district, and has opening portion in memory transistor formation district.Then, the sacrificial oxidation film on the storage crystal area under control 261 is utilized resist pattern 63 to make mask and is optionally removed (seeing Figure 48 B).
(3) after removing resist pattern 263, on the surface of the n-trap 2 on the memory transistor zone, carry out thermal oxidation technology and have for example storage gate oxidation films 257 of 7.5nm thickness with establishment.In this technology,, select gate oxidation films 265 and peripheral circuit gate oxidation films 259 (seeing Figure 48 C) to become selecting the sacrificial oxidation film 261 on the transistor area and on the peripheral circuit transistor zone to increase thickness.
(4) be similar to as above technology by execution with reference to the described processing step of Figure 19 A-19C (1) to (3), selection grid 213 are created in the field oxide film of selecting on the transistor area 203 and select on the gate oxidation films 255, floating grid 217 is created on the field oxide film 203 and storage gate oxidation films 257 on the storage crystal area under control, and peripheral circuit grid 225 are created on the field oxide film 203 and peripheral circuit gate oxidation films 259 in the peripheral circuit transistor district.Then, p-type diffusion layer 205,207,209,219 and 221 is similar to as above by execution and creates (seeing Figure 47 A-47D) with reference to the technology of the described processing step of Figure 16 A-16D (4).
Figure 49 A to 49D is the schematic diagram of diagram 23th embodiment of the invention.Figure 49 A is the plane graph of memory cell, and Figure 49 B is the plane graph of peripheral circuit transistor, and Figure 49 C is the profile that Figure 49 A A-A ' along the line cuts open the memory cell of getting, and Figure 49 D is the profile that Figure 49 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted, provide same reference number with element same shown in Figure 16 A-16D, Figure 20 A-20D, Figure 42 A-42D and Figure 47 A-47D, and omitted description of them.
Present embodiment is different from as top and is with reference to described the 22 embodiment part of Figure 47 A-47D, replaces phosphorus to be injected in the polysilicon of selecting grid 233 and floating grid 235 such as the p-type impurity of boron.Select the concentration of boron in grid 233 and the floating grid 235 for example can be about 7.0 * 10 18To 5.0 * 10 19Atom/cm 3
According to present embodiment, carry out as above with reference to the described processing step of Figure 48 A-48C (1) to (3), after this carry out as above with reference to Figure 20 A-20D and the described processing step of Figure 21 A-21C (1) to (4) to create memory cell and peripheral circuit transistor.
In the present embodiment, can obtain to as above in the 7th embodiment with reference to the similar advantageous effects of the described effect of Figure 20 A-20D.
Equally, in the present embodiment, storage gate oxidation films 257 is arranged to thinner than peripheral circuit gate oxidation films 259, and therefore, can be suitable for carrying out write operation on memory transistor, and prevents that peripheral circuit gate oxidation films 259 from damaging and preventing to puncture rapidly generation.
Figure 50 A to 50C is the schematic diagram of diagram 24th embodiment of the invention.Figure 50 A is the plane graph of memory cell, and Figure 50 B is the plane graph of peripheral circuit transistor, and Figure 50 C is the profile that Figure 50 A A-A ' along the line cuts open the memory cell of getting, and Figure 50 D is the profile that Figure 50 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted, provide same reference number with element same shown in Figure 16 A-16D, Figure 22 A-22D, Figure 42 A-42D and Figure 47 A-47D, and omitted description of them.
Present embodiment is different from as above and is with reference to described the 20 embodiment part of Figure 47 A-47D, wherein selects grid 239 and peripheral circuit grid 225 to create simultaneously, and is incorporated into the concentration that is higher than floating grid 217 such as the n-type impurity of phosphorus and selects in the grid 239.Select grid 239 interior basic phosphorus concentrations for example can be about 1.0 * 10 20Atom/cm 3
According to present embodiment, carry out as above with reference to the described processing step of Figure 48 A-48C (1) to (3), after this carry out as above with reference to Figure 22 A-22D and the described processing step of Figure 23 A-23C (1) to (4), to create memory cell and peripheral circuit transistor.
In the present embodiment, can obtain with as above in the 8th embodiment with reference to the similar advantageous effects of the described effect of Figure 22 A-22D.
Equally, in the present embodiment, storage gate oxidation films 257 is arranged to thinner than peripheral circuit gate oxidation films 259, and therefore, can be suitable for carrying out write operation on memory transistor, and prevents that peripheral circuit gate oxidation films 259 from damaging and preventing to puncture rapidly generation.
Figure 51 A to 51D is the schematic diagram of diagram 25th embodiment of the invention, Figure 51 A is the plane graph of memory cell, Figure 51 B is the plane graph of peripheral circuit transistor, Figure 51 C is the profile that Figure 51 A A-A ' along the line cuts open the memory cell of getting, and Figure 51 D is the profile that Figure 51 B B-B ' along the line cuts open the peripheral circuit transistor of getting.It should be noted, provide same reference number with element same shown in Figure 16 A-16D, Figure 20 A-20D, Figure 22 A-22D, Figure 24 A-24D, Figure 42 A-42D and Figure 47 A-47D, and omitted description of them.
Present embodiment is different from as above and is with reference to described the 24 embodiment part of Figure 50 A-50D, replaces phosphorus to be incorporated in the polysilicon of floating grid 235 such as the p-type impurity of boron.Boron concentration in floating grid 235 for example can be 7.0 * 10 18To 5.0 * 10 19Atom/cm 3
According to present embodiment, carry out as above with reference to the described processing step of Figure 48 A-48C (1) to (3), after this carry out as above with reference to Figure 24 A-24D and the described processing step of Figure 25 A-25C (1) to (4) to create memory cell and peripheral circuit transistor.
In the present embodiment, can obtain with as above in the 9th embodiment with reference to the same advantageous effects of the described effect of Figure 24 A-24D.
Equally, in the present embodiment, storage gate oxidation films 257 is arranged to thinner than peripheral circuit gate oxidation films 259, and therefore, can be suitable for carrying out write operation on memory transistor, and prevents that peripheral circuit gate oxidation films 259 from damaging and preventing to puncture rapidly generation.
As above with reference to described the 22 embodiment of Figure 47 A-47D, as above with reference to described the 23 embodiment of Figure 49 A-49D, as above with reference to described the 24 embodiment of Figure 50 A-50D with as above with reference among described the 25 embodiment of Figure 51 A-51D, select gate oxidation films 265 to be arranged to thinner than peripheral circuit gate oxidation films 259, and therefore, gate oxidation films 259 and 265 can be created simultaneously, thereby with create to select gate oxidation films 265 respectively, storage gate oxidation films 257 and peripheral circuit gate oxidation films 259 are relatively created the required technology amount of this gate oxidation films and can be reduced.
Should note in above-mentioned graphic embodiment, memory transistor and selection transistor are corresponding to PMOS transistor (voltage of writing that has about 6-7V), and therefore, so-called control gate is not must be used to write, and writes voltage and can reduce with the situation ratio that utilizes nmos pass transistor to make memory transistor (voltage of writing that has about 10V).
Yet, the invention is not restricted to the transistorized use of PMOS, and nmos pass transistor can and be selected transistor as memory transistor in another embodiment of the present invention.
Equally, in above-mentioned graphic embodiment, the PMOS transistor is shown as peripheral circuit transistor, yet the invention is not restricted to such embodiment, and for example can be arranged on the other zone as the transistorized nmos pass transistor of other peripheral circuit.
Equally, according to alternate embodiment of the present invention, semiconductor substrate can be the n-substrate.
In another embodiment, silicide film can be arranged at least one that select grid, storage grid and peripheral circuit grid, to reduce gate resistance.
Figure 52 is that diagram comprises the circuit diagram that produces circuit according to the constant voltage of the distributor resistance circuit of the embodiment of the invention.
Constant voltage shown in Figure 52 produces circuit 290 and is configured to regulate the power supply that provides from DC power supply 271.Constant voltage produce circuit 290 comprise the input (Vbat) 273 that is connected to DC power supply 271, generating circuit from reference voltage (Vref) 275, computing amplifier 277, as the p-channel type MOS transistor of output driver (below be called ' PMOS ') 279, distributor resistor 281,283 and output (Vout) 285.
Distributor resistor 283 comprises resistive element RO.Distributor resistor 281 comprises a plurality of resistances adjusting resistive element R1, R2, Ri-1 and the Ri that is connected in series.Fuse MOS transistor SW1, SW2, SWi-1 and SWi and resistance are regulated resistive element R1, R2, Ri-1 and Ri and are connected in parallel respectively.
The constant voltage of present embodiment produces circuit 290 and also comprises the reading circuit 287 that is used for ON/OFF fuse MOS transistor SW1, SW2, SWi-1 and SWi and non-volatile memory cells 289.The output of reading circuit 287 is connected on the grid of correspondence of fuse MOS transistor SW1, SW2, SWi-1 and SWi.Non-volatile memory cells 289 comprises a plurality of memory cell, and its storage is fit to the information of ON/OFF fuse MOS transistor SW1, SW2, SWi-1 and SWi.Reading circuit 287 is according to store status ON/OFF fuse MOS transistor SW1, SW2, SWi-1 and the SWi of non-volatile memory cells 289.
Produce in the computing amplifier 277 of circuit 290 in constant voltage circuit, the output of computing amplifier 277 is connected on the gate electrode of PMOS279.Apply the inverting terminal of computing amplifier 277 from the reference voltage Vref of generating circuit from reference voltage 275.Be applied on the amplifier in of computing amplifier 277 by resistor 281 and 283 voltages that output voltage produced that distribute.The voltage control of resistor 281 and 283 distribution becomes to equal reference voltage Vref.
Figure 53 is that diagram comprises the circuit diagram according to the voltage detection circuit of the distributor resistance circuit of the embodiment of the invention.It should be noted in this accompanying drawing, provide identical reference number with components identical shown in Figure 52.
In the voltage detection circuit shown in Figure 53 291, distributor resistance 281,283 and anti-vibration resistive element RH are at ground potential and import between the input 293 of terminal voltage to be measured (input voltage Vsens) and be connected in series.It should be noted that in the present embodiment, it is identical with the structure of resistor 281 shown in Figure 52 and 283 that resistance 281 and 283 structure are arranged to.
According to present embodiment, fuse MOS transistor SW1, SW2, SWi-1 and SWi regulate resistive element R1, R2, Ri-1 and Ri with resistance respectively and are connected in parallel.Reading circuit 287 is connected on fuse MOS transistor SW1, SW2, SWi-1 and the SWi.Non-volatile memory cells 289 is connected on the reading circuit 287.
Anti-vibration resistive element RH is arranged between distributor resistor 283 and the ground connection.The anti-vibration of n-channel-type fuse MOS transistor SWH and anti-vibration resistive element RH are connected in parallel.The grid of anti-vibration fuse MOS transistor SWH is connected in the output of computing amplifier 277.
The inverting terminal of computing amplifier 277 is connected on the tie point between distributor resistor 281 and 283.The non-inverting input terminal of computing amplifier 277 is connected on the generating circuit from reference voltage 275, so that reference voltage Vref can apply on it.The output of computing amplifier 277 outputs to the outside by converter 295 and output (D Tout) 297.
When voltage detection circuit 291 is in the high voltage acquisition mode, anti-vibration resistive element RH is closed, and when higher from the end voltage to be measured of input 293 inputs, and when being higher than reference voltage Vref by the voltage that distributor resistance 281,283 and anti-vibration resistive element RH distribute, the output of computing amplifier 277 maintains logical value 0, and this output changes into logical one by converter 295, and from output 297 outputs.In this case, the voltage of distribution that is input to the inverting terminal of computing amplifier 277 can be expressed as follows:
{(RO)+(RH)}/{(R1)+...+(Ri-1)+(Ri)+(RO)+...}
When end voltage to be measured reduces, and become when being lower than reference voltage Vref by the voltage that distributor resistance 281,283 and anti-vibration resistive element RH distribute, the output of computing amplifier 277 is set to logical value 1, and this output changes into logical value 0 by converter 295, to export from output 297.
When the output of computing amplifier 277 was set to logical value 1, anti-vibration fuse MOS transistor SWH connected, and distributor resistance 283 is connected to ground potential by anti-vibration fuse MOS transistor SWH, and the voltage between distributor resistance 281 and 283 reduces.Then, the output of computing amplifier 277 maintains logical value 1, and voltage detection circuit 291 falls into the low-voltage acquisition mode.It should be noted that when input voltage Vsens reduced, anti-vibration resistive element RH and anti-vibration fuse MOS transistor SWH were configured to prevent the output vibration of voltage detection circuit 291.
When voltage detection circuit 291 was in lower voltage detection state, the component voltage that is input to the inverting terminal of computing amplifier 277 can be expressed as follows:
(RO)/{(R1)+...+(Ri-1)+(Ri)+...}
Being used for changing voltage detection circuit 291 can be the input voltage Vsens of level like this to the wake-up voltage of high voltage acquisition mode, makes that the voltage of distribution of the inverting terminal that is input to computing amplifier 277 under the low-voltage acquisition mode can be greater than reference voltage Vref.
It should be noted, in Figure 52 and 53, by the MOS transistor of reading circuit 287, generating circuit from reference voltage 275 and computing amplifier 277 realizations; Fuse MOS transistor SW1, SW2, SWi-1 and SWi; With anti-vibration fuse MOS transistor SWH as peripheral circuit transistor according to the semiconductor device of the embodiment of the invention.Yet the invention is not restricted to the embodiments described, and it does not require that all MOS transistor implement the peripheral circuit transistor of present embodiment as described above.
Equally, in Figure 52 and 53, by the control by reading circuit 287 and non-volatile memory cells 289, fuse MOS transistor SW1, SW2, SWi-1 and SWi can ON/OFF, so that the resistance of distributor resistance 281 can be adjusted.Like this, constant voltage produces voltage is set can adjusts of output voltage of the output voltage of circuit 290 and voltage detection circuit 291.
It should be noted, produce in circuit and the conventional voltage detection circuit in traditional constant voltage, regulating resistive element R1, R2, Ri-1 and Ri by polysilicon or metal fuse and each resistance is connected in parallel, and do not use fuse MOS transistor SWi, SW2, SWi-1, SWi, reading circuit 287 and non-volatile memory cells 289 according to present embodiment, and in such traditional circuit, the resistance of distributor resistor is by cutting off the fuse adjustment.
In Figure 52 and 53 graphic embodiment, in case the switch of cutting out (just, fuse MOS transistor SW1, SW2, SWi-1, SWi) can be by opening once more by reading circuit 287 and non-volatile memory cells 289 controls, such on/off operation is difficult to realize with fuse.Like this, be used for voltage is set freely changes of output voltage that constant voltage produces the output voltage of circuit 290 and voltage detection circuit 291.
According to the preferred embodiment of the present invention, the open/close state of fuse MOS transistor SW1, SW2, SWi-1, SWi can be by the conversion of the write operation on non-volatile memory cells 289, and therefore, even after semiconductor device is contained in the encapsulation, the voltage that is provided with of the output voltage of constant voltage generation circuit 290 and the output voltage of voltage detection circuit 291 also can be adjusted and be changed.
Equally, it should be noted in Figure 52 and 53, be applied to constant voltage according to the distributor resistance circuit of the embodiment of the invention and produce on circuit and the voltage detection circuit; Yet, the invention is not restricted to such application, and the distributor resistance circuit can be applied on the circuit of other type also.
The exemplary advantageous effects that obtains by one or more embodiment of the present invention is described below.
According to one aspect of the invention, comprise the memory transistor that do not have control gate by having floating grid and select non-volatile memory cells that transistor makes and the semiconductor device of peripheral circuit transistor in, by the storage gate oxidation films thinner than peripheral circuit gate oxidation films is set, the peripheral circuit gate oxidation films can be arranged to enough thick so that can prevent that it from damaging when carrying out write operation on memory transistor, and the storage gate oxidation films can be arranged to thin fully so that can obtain good write attribute on memory transistor.Like this, can be suitable on memory transistor, carrying out write operation, and prevent that the peripheral circuit gate oxidation films from damaging and preventing to puncture rapidly generation.
According to a further aspect in the invention, by using the PMOS transistor to make memory transistor and (for example selecting transistor, the voltage of writing that has about 6-7V), control gate can be used on the write operation, and writing voltage can reduce with the situation ratio that utilizes nmos pass transistor to make memory transistor (voltage of writing that for example, has about 10V).Yet, it should be noted, the invention is not restricted to make memory transistor and select transistor, and nmos pass transistor can similarly use according to an alternative embodiment of the invention with the PMOS transistor.
According to a further aspect in the invention, select gate oxidation films to have identical thickness by being provided with the storage gate oxidation films, two gate oxidation films can be created simultaneously, and with for example respectively fill order original creation build the technology ratio of selecting gate oxidation films, storage gate oxidation films and peripheral circuit gate oxidation films, create the required processing step amount of these grid and can reduce.
According to a further aspect in the invention, select gate oxidation films to have identical thickness by being provided with the peripheral circuit gate oxidation films, two gate oxidation films can be created simultaneously, and can reduce with the processing step amount of creating each gate oxidation films respectively separately than creating selection gate oxidation films, storage gate oxidation films and peripheral circuit gate oxidation films.In addition, in this case, select gate oxidation films to be arranged to, and therefore, can improve and select transistorized endurance than storage gate oxidation thickness.
According to a further aspect in the invention, by capacitor is provided, this capacitor comprises by dielectric film and is arranged on the bottom electrode of being made by polysilicon on the semiconductor substrate, and comprises by capacitor insulating film and be arranged on the top electrode of being made by polysilicon on the bottom electrode; Floating grid and bottom electrode that setting is created by identical polysilicon layer; On floating grid He on the side, capacitor insulating film is set, thereby floating grid can fully be covered by capacitor insulating film, so that can improve retention performance.
According to a further aspect in the invention, by peripheral circuit grid and the top electrode of being created by identical polysilicon layer is set,, create the required processing step amount of these grid and can reduce with the situation ratio of creating peripheral circuit grid and top electrode respectively.
According to a further aspect in the invention, by selection grid and the bottom electrode of being created by identical polysilicon layer is set,, create the required processing step amount of these grid and can reduce with the situation ratio of creating peripheral circuit grid and top electrode respectively.
According to a further aspect in the invention, by selection grid, peripheral circuit grid and the top electrode of being created by identical polysilicon layer is set, with the situation ratio of creating these grid respectively, the processing step amount can reduce.
According to a further aspect in the invention, in the semiconductor device that comprises the distributor resistance circuit, the output voltage of distributor resistance circuit can be according to the store status adjustment of the non-volatile memory cells with good write attribute, this distributor resistance circuit is configured to obtain voltage output and adjust voltage output by cutting off one or more fuse elements by voltage distribution, and this regulates resistive element by configuration distributor resistance circuit to comprise a plurality of resistances that are connected in series, to regulate resistive element in parallel and be used as a plurality of fuse MOS transistor of fuse element with resistance, non-volatile memory cells and be used for reading circuit according to an embodiment of the invention according to non-volatile memory cells store status ON/OFF fuse MOS transistor, and by in configuration fuse MOS transistor and the reading circuit at least one in peripheral circuit transistor according to an embodiment of the invention.In addition, for example by changing the store status of non-volatile memory cells, the output voltage of distributor resistance circuit can reset.
According to a further aspect in the invention, in comprising the semiconductor device of voltage detection circuit, the output voltage of voltage detection circuit can change by the store status that changes non-volatile memory cells, this voltage detection circuit comprises the distributor resistance circuit that distributes input voltage and export this distribution voltage, produce the generating circuit from reference voltage of reference voltage, from the component voltage of distributor resistance circuit and reference voltage comparison circuit relatively from generating circuit from reference voltage, this is again by using according to an embodiment of the invention the distributor resistance circuit as the distributor resistance circuit of voltage detection circuit.
According to a further aspect in the invention, comprising that constant voltage produces in the semiconductor device of circuit, the output voltage setting that constant voltage produces circuit can change by the store status that changes non-volatile memory cells, this constant voltage produces the output driver that circuit comprises the output of control input voltage, the distributor resistance circuit that distributes the voltage of output voltage and output distribution, produce reference voltage generating circuit from reference voltage and from the component voltage of distributor resistance circuit with from the reference voltage of generating circuit from reference voltage relatively and according to the comparison circuit of the operation of comparative result control output driver, this is by using distributor resistance circuit according to an embodiment of the invention produces circuit as constant voltage distributor resistance circuit.
According to a further aspect in the invention, comprise the memory transistor that do not have control gate by having floating grid and select non-volatile memory cells that transistor makes and the semiconductor device of peripheral circuit transistor in, be lower than the impurity concentration in the polysilicon of peripheral circuit grid of peripheral circuit transistor by impurity concentration in the polysilicon that floating grid is set, the basic impurity concentration in the polysilicon of floating grid can be set to and for example be lower than 1.0 * 10 20Atom/cm 3Concentration so that the charge-retention property of memory transistor can improve.In addition, because impurity concentration is arranged to be higher than impurity concentration in the polysilicon of floating grid in the polysilicon of peripheral circuit grid, so the resistance of peripheral circuit grid can fully reduce, and can prevent the reduction of peripheral circuit grid processing speed.
According to a further aspect in the invention, by the impurity concentration in the polysilicon that impurity concentration in the polysilicon of selecting grid equals floating grid is set, these two grid can be created simultaneously, compare with the situation of creating selection grid, floating grid and peripheral circuit grid respectively, create the required technology amount of these grid and can reduce.
According to a further aspect in the invention, by the impurity concentration in the polysilicon that impurity concentration in the polysilicon of selecting grid equals the peripheral circuit grid is set, these two grid can be created simultaneously, compare with the situation of creating selection grid, floating grid and peripheral circuit grid respectively, create the required technology amount of these grid and can reduce.
According to a further aspect in the invention, by the storage gate oxidation films being set, selecting gate oxidation films to have identical thickness with the peripheral circuit gate oxidation films, these gate oxidation films can be created simultaneously, and create the required technology amount of these grid and relatively can reduce with the situation of creating selection gate oxidation films, floating grid oxide-film and peripheral circuit gate oxidation films respectively.
It should be noted, in the semiconductor device that comprises memory transistor, selection transistor and the peripheral circuit transistor of not being with control gate, when transistorized gate oxidation films is arranged to have identical thickness, and when gate oxide film thickness was set to half grade of the branch of 7.5nm for example, the memory transistor gate oxidation films of memory transistor became 7.5nm.In this case, according to the inventor's discovery,, need 6-7V or higher predetermined voltage Vpp in order on memory transistor, to obtain good write attribute.
Yet in this case, when carrying out write operation on memory transistor, for example 6-7V or higher voltage must be applied to and be arranged on the peripheral circuit transistor that applies predetermined voltage Vpp on the memory.This means that the electric field that reaches 10MV/cm must apply on the peripheral circuit gate oxidation films that thickness only is 7.5nm.Thereby the peripheral circuit gate oxidation films may damage easily, and then the productive rate of semiconductor device and reliability may reduce.
Equally, according to inventor's discovery, gate oxide film thickness is the predetermined voltage Vpp that snapback's voltage of the nmos pass transistor (n-channel MOS transistor) of 7.5nm is substantially equal to 6-7V, and therefore, when carrying out write operation, peripheral circuit may be very easy to damage.Therefore, the productive rate of semiconductor device and reliability are also because this may reduce on the one hand.
Even memory transistor, select the film thickness of the gate oxidation films of transistor and peripheral circuit transistor to be increased to half grade of the branch of 13.5nm for example, in order to offset top problem, writing voltage also must correspondingly increase, and therefore can not deal with problems.Particularly, when gate oxide film thickness is set to about 13.5nm and writes voltage Vpp and be set to about 6-7V,, store gate oxidation films and can reach 13.5nm, can not realize good write attribute because of too thick though can prevent the damage of peripheral circuit gate oxidation films.
Thereby, according to a further aspect in the invention, it is thinner by the storage gate oxidation films is set than peripheral circuit gate oxidation films, the peripheral circuit gate oxidation films can be arranged to enough thick, can prevent that it from damaging when carrying out write operation on the convenient memory transistor, and the storage gate oxidation films can be arranged to enough approach so that can obtain good write attribute on memory transistor.Like this, can be suitable on memory transistor carrying out and write and prevent that the peripheral circuit gate oxidation films from damaging and preventing to puncture rapidly generation.
According to a further aspect in the invention, by memory transistor being set and selecting transistor is PMOS transistor (voltage of writing that has 6-7V), control gate needn't look like using nmos pass transistor (voltage of writing that has about 10V) to do to use under the situation of memory transistor, and therefore can reduce and write voltage.Yet, it should be noted, the invention is not restricted to use the PMOS transistor to make memory transistor and selection transistor, and in selectivity embodiment, for example these transistors can be arranged to nmos pass transistor.
According to a further aspect in the invention, be arranged among the embodiment thinner at the storage gate oxidation films than peripheral circuit gate oxidation films, select gate oxidation films to have identical thickness by being provided with the storage gate oxidation films, two grid can be created simultaneously, create the required technology amount of these grid and relatively can reduce with the situation of creating selection gate oxidation films, storage gate oxidation films and peripheral circuit gate oxidation films respectively.
According to a further aspect in the invention, select gate oxidation films to have identical thickness by being provided with the peripheral circuit gate oxidation films, two grid can be created simultaneously, and create the required technology amount of these grid and relatively can reduce with the situation of creating selection gate oxidation films, storage gate oxidation films and peripheral circuit gate oxidation films respectively.Equally, arrangement like this, the situation ratio with selecting gate oxidation films and storage gate oxidation films to be arranged to have same thickness can improve and select transistorized pressure drag (pressure resistance).
According to a further aspect in the invention, in semiconductor device according to the embodiment of the invention, by memory transistor being set and selecting transistor to become PMOS transistor (voltage of writing that has 6-7V), control gate needn't look like using nmos pass transistor (voltage of writing that has about 10V) to do to use under the situation of memory transistor, and therefore can reduce and write voltage.Yet, it should be noted, the invention is not restricted to use the PMOS transistor as memory transistor and selection transistor, and in selectivity embodiment, for example these transistors can be arranged to nmos pass transistor.
According to a further aspect in the invention, in the semiconductor device that comprises the distributor resistance circuit, store status according to non-volatile memory cells with good write attribute, can adjust the output voltage of distributor resistance circuit, this distributor resistance circuit is configured to obtain voltage output and adjust voltage output by cutting off one or more fuse elements by voltage distribution, this comprises a plurality of resistances adjusting resistive elements that are connected in series by configuration distributor resistance circuit, regulate with resistance that resistive element is connected in parallel and as a plurality of fuse MOS transistor of fuse element, non-volatile memory cells and be used for reading circuit according to an embodiment of the invention according to non-volatile memory cells store status ON/OFF fuse MOS transistor, and by in configuration fuse MOS transistor and the reading circuit at least one in peripheral circuit transistor according to an embodiment of the invention.In addition, for example by changing the store status of non-volatile memory cells, the output voltage of distributor resistance circuit can reset.
According to a further aspect in the invention, in comprising the semiconductor device of voltage detection circuit, the output voltage of voltage detection circuit can change by the store status that changes non-volatile memory cells, this voltage detection circuit comprises the distributor resistance circuit that distributes input voltage and export the voltage of this distribution, produce the generating circuit from reference voltage of reference voltage, from the voltage of the distribution of distributor resistance circuit and reference voltage comparison circuit relatively from generating circuit from reference voltage, this makes the distributor resistance circuit of voltage detection circuit by using distributor resistance circuit according to an embodiment of the invention.
According to a further aspect in the invention, comprising that constant voltage produces in the semiconductor device of circuit, being provided with of output voltage that constant voltage produces circuit can change by the store status that changes non-volatile memory cells, this constant voltage produces the output driver that circuit comprises the output of control input voltage, distribute input voltage and export the distributor resistance circuit of the voltage of this distribution, produce reference voltage generating circuit from reference voltage and from the component voltage of distributor resistance circuit with from the reference voltage of generating circuit from reference voltage relatively and according to the comparison circuit of comparative result control output driver operation, this makes the distributor resistance circuit that constant voltage produces circuit by using according to an embodiment of the invention the distributor resistance circuit.
It should be noted, although the present invention shows with reference to certain embodiment and describes, but the feature of describing about preferred embodiment such as numerical value, structure, material and layout etc. also only are illustrative examples, clearly to one skilled in the art, will produce equivalent feature and modification after understanding this specification.The present invention includes all such equivalent feature and modifications, and limited by claim.
The application is based on Japanese patent application No.2004-372775 that submitted on December 24th, 2004 and the Japanese patent application No.2005-097472 that submitted on March 30th, 2005, and require in them the priority of the applying date the earliest, quote in full with for referencial use in this content with them.

Claims (22)

1. semiconductor device comprises:
Semiconductor substrate;
Non-volatile memory cells, it comprises
Memory transistor is realized by MOS transistor, comprises the storage gate oxidation films that is arranged on this semiconductor substrate and is arranged on the floating grid of being made by polysilicon on this storage gate oxidation films, and this floating grid is in electric floating state; With
Select transistor, realized by MOS transistor, be connected in series on this memory transistor, this selection transistor comprises the selection gate oxidation films that is arranged on this semiconductor substrate and is arranged on the selection grid of being made by polysilicon on this selection gate oxidation films; With
Peripheral circuit transistor is realized by MOS transistor, comprises the peripheral circuit gate oxidation films that is arranged on this semiconductor substrate and is arranged on the peripheral circuit gate oxidation films of being made by polysilicon on this peripheral circuit gate oxidation films;
Wherein this storage gate oxidation films is arranged to thinner than this peripheral circuit gate oxidation films.
2. semiconductor device as claimed in claim 1, wherein this memory transistor and this selection transistor are the PMOS transistors.
3. semiconductor device as claimed in claim 1, wherein this selection gate oxidation films is arranged to have identical thickness with this storage gate oxidation films.
4. semiconductor device as claimed in claim 1, wherein this selection gate oxidation films is arranged to have identical thickness with this peripheral circuit gate oxidation films.
5. semiconductor device as claimed in claim 1 also comprises:
Capacitor comprises by dielectric film being arranged on the bottom electrode of being made by polysilicon on this semiconductor substrate and comprising by capacitor insulating film and be arranged on the top electrode of being made by polysilicon film on this bottom electrode;
Wherein this floating grid is created by identical polysilicon layer with this bottom electrode, and this capacitor insulating film is arranged on the top and side of this floating boom.
6. semiconductor device as claimed in claim 5,
Wherein these peripheral circuit grid are created by identical polysilicon layer with this top electrode.
7. semiconductor device as claimed in claim 5,
Wherein should select grid, this floating grid and this bottom electrode to create by this identical polysilicon layer.
8. semiconductor device as claimed in claim 6,
Wherein should select grid, peripheral circuit grid and top electrode to create by this identical polysilicon layer.
9. semiconductor device comprises:
The distributor resistance circuit is configured to obtain voltage output and adjust this voltage output by cutting off one or more fuse elements by voltage distribution;
This distributor resistance circuit comprises
A plurality of resistances are regulated resistive element, are connected in series;
A plurality of fuse MOS transistor as this fuse element, are regulated resistive element with this resistance and are connected in parallel;
Non-volatile memory cells, comprise memory transistor and select transistor, this memory transistor is realized by MOS transistor, comprise the storage gate oxidation films that is arranged on the semiconductor substrate and be arranged on the floating grid of being made by polysilicon on this storage gate oxidation films, this floating grid is in electric floating state; This selection transistor is realized by the MOS transistor that is connected in series on this memory transistor, and is comprised the selection gate oxidation films that is arranged on this semiconductor substrate and be arranged on the selection grid of being made by polysilicon on this selection gate oxidation films; With
Reading circuit is used for this fuse MOS transistor of this store status ON/OFF according to this non-volatile memory cells;
Wherein at least one in this fuse MOS transistor and this reading circuit is configured to the peripheral circuit transistor by the MOS transistor realization, this peripheral circuit transistor comprises the peripheral circuit gate oxidation films that is arranged on this semiconductor substrate and is arranged on the peripheral circuit grid of being made by polysilicon on this peripheral circuit gate oxidation films that its peripheral circuit gate oxidation films is arranged to than this storage gate oxidation thickness.
10. semiconductor device comprises:
Voltage detection circuit comprises that the distributor resistance appliance that distributes input voltage and export the voltage of this distribution, the generating circuit from reference voltage that produces reference voltage, comparison are from the voltage of this distribution of this distributor resistance circuit and comparison circuit from this reference voltage of this generating circuit from reference voltage;
The distributor resistance appliance comprises
A plurality of resistances are regulated resistive element, are connected in series;
A plurality of fuse MOS transistor as this fuse element, are regulated resistive element with this resistance and are connected in parallel;
Non-volatile memory cells, it comprises memory transistor and selects transistor, this memory transistor is realized by MOS transistor, comprise the storage gate oxidation films that is arranged on the semiconductor substrate and be arranged on the floating grid of being made by polysilicon on this storage gate oxidation films, this floating grid is in electric floating state; This selection transistor is realized by the MOS transistor that is connected in series on this memory transistor, and is comprised the selection gate oxidation films that is arranged on this semiconductor substrate and be arranged on the selection grid that are made of polysilicon on this selection gate oxidation films; With
Reading circuit is used for this fuse MOS transistor of this store status ON/OFF according to this non-volatile memory cells;
Wherein at least one in this fuse MOS transistor and this reading circuit is configured to the peripheral circuit transistor by the MOS transistor realization, this peripheral circuit transistor comprises the peripheral circuit gate oxidation films that is arranged on this semiconductor substrate and is arranged on the peripheral circuit grid of being made by polysilicon on this peripheral circuit gate oxidation films that its peripheral circuit gate oxidation films is arranged to than this storage gate oxidation thickness.
11. a semiconductor device comprises:
Constant voltage produces circuit, comprise the output of control input voltage output driver, distribute output voltage and export the voltage of this distribution the distributor resistance circuit, produce the generating circuit from reference voltage of reference voltage and relatively from the voltage of this distribution of this distributor resistance circuit with from this reference voltage of this generating circuit from reference voltage and control the comparison circuit of this output driver operation according to this comparative result;
The distributor resistance appliance comprises
A plurality of resistances are regulated resistive element, are connected in series;
A plurality of fuse MOS transistor as this fuse element, are regulated resistive element with this resistance and are connected in parallel;
Non-volatile memory cells, comprise memory transistor and select transistor, this memory transistor is realized by MOS transistor, comprise the storage gate oxidation films that is arranged on the semiconductor substrate and be arranged on the floating grid of being made by polysilicon on this storage gate oxidation films, this floating grid is in electric floating state; This selection transistor is realized by the MOS transistor that is connected in series on this memory transistor, and is comprised the selection gate oxidation films that is arranged on this semiconductor substrate and be arranged on the selection grid of being made by polysilicon on this selection gate oxidation films; With
Reading circuit is used for this fuse MOS transistor of this store status ON/OFF according to this non-volatile memory cells;
Wherein at least one in this fuse MOS transistor and this reading circuit is configured to the peripheral circuit transistor by the MOS transistor realization, this peripheral circuit transistor comprises the peripheral circuit gate oxidation films that is arranged on this semiconductor substrate and is arranged on the peripheral circuit grid of being made by polysilicon on this peripheral circuit gate oxidation films that its peripheral circuit gate oxidation films is arranged to than this storage gate oxidation thickness.
12. a semiconductor device comprises:
Semiconductor substrate;
Non-volatile memory cells, it comprises
Memory transistor is realized by MOS transistor, comprises the storage gate oxidation films that is arranged on the semiconductor substrate and is arranged on the floating grid of being made by polysilicon on this storage gate oxidation films, and this floating grid is in electric floating state; With
Select transistor, realized by the MOS transistor that is connected in series on this memory transistor, this selection transistor comprises the selection gate oxidation films that is arranged on this semiconductor substrate and is arranged on the selection grid of being made by polysilicon on this selection gate oxidation films; With
Peripheral circuit transistor is realized by MOS transistor, comprises the peripheral circuit gate oxidation films that is arranged on this semiconductor substrate and is arranged on the peripheral circuit grid of being made by polysilicon on this peripheral circuit gate oxidation films;
Wherein the impurity concentration in this polysilicon of this floating grid is arranged to be lower than the interior impurity concentration of this polysilicon of this peripheral circuit gate oxidation films.
13. semiconductor device as claimed in claim 12,
Wherein the impurity concentration in this polysilicon of these selection grid equals this interior impurity concentration of this polysilicon of this floating grid.
14. semiconductor device as claimed in claim 12,
Wherein the impurity concentration in this polysilicon of these selection grid equals this interior impurity concentration of this polysilicon of these peripheral circuit grid.
15. semiconductor device as claimed in claim 12,
Wherein this storage gate oxidation films, this selection gate oxidation films and this peripheral circuit gate oxidation films are arranged to have identical thickness.
16. semiconductor device as claimed in claim 12,
Wherein this storage gate oxidation films is arranged to thinner than this peripheral circuit gate oxidation films.
17. semiconductor device as claimed in claim 16,
Wherein this selection gate oxidation films is arranged to have identical thickness with this storage gate oxidation films.
18. semiconductor device as claimed in claim 16,
Wherein this selection gate oxidation films is arranged to have identical thickness with this peripheral circuit gate oxidation films.
19. semiconductor device as claimed in claim 12,
Wherein this memory transistor and this selection transistor are the PMOS transistors.
20. a semiconductor device comprises:
The distributor resistance circuit is configured to obtain voltage output and adjust this voltage output by cutting off one or more fuse elements by voltage distribution;
This distributor resistance circuit comprises
A plurality of resistances are regulated resistive element, are connected in series;
A plurality of fuse MOS transistor as this fuse element, are regulated resistive element with this resistance and are connected in parallel;
Non-volatile memory cells, comprise memory transistor and select transistor, this memory transistor is realized by MOS transistor, comprise the storage gate oxidation films that is arranged on the semiconductor substrate and be arranged on the floating grid of being made by polysilicon on this storage gate oxidation films, this floating grid is in electric floating state; This selection transistor is realized by the MOS transistor that is connected in series on this memory transistor, and is comprised the selection gate oxidation films that is arranged on this semiconductor substrate and be arranged on the selection grid of being made by polysilicon on this selection gate oxidation films; With
Reading circuit is used for this fuse MOS transistor of this store status ON/OFF according to this non-volatile memory cells;
Wherein at least one in this fuse MOS transistor and this reading circuit is configured to the peripheral circuit transistor by the MOS transistor realization, this peripheral circuit transistor comprises the peripheral circuit gate oxidation films that is arranged on this semiconductor substrate and is arranged on the peripheral circuit grid of being made by polysilicon on this peripheral circuit gate oxidation films that this polysilicon of these peripheral circuit grid is arranged to have the high impurity concentration of impurity concentration than in this polysilicon of this floating grid.
21. a semiconductor device comprises:
Voltage detection circuit comprises that the distributor resistance circuit of the voltage that distributes input voltage and this distribution of output, the generating circuit from reference voltage that produces reference voltage, comparison are from the voltage of this distribution of this distributor resistance circuit and comparison circuit from this reference voltage of this generating circuit from reference voltage;
This distributor resistance appliance comprises:
A plurality of resistances are regulated resistive element, are connected in series;
A plurality of fuse MOS transistor, as this fuse element, itself and this resistance is regulated resistive element and is connected in parallel;
Non-volatile memory cells, comprise memory transistor and select transistor, this store storage transistor is realized by MOS transistor, comprise the storage gate oxidation films that is arranged on the semiconductor substrate and be arranged on the floating grid of being made by polysilicon on this storage gate oxidation films, this floating grid is in electric floating state; This selection transistor is realized by the MOS transistor that is connected in series on this memory transistor, and is comprised the selection gate oxidation films that is arranged on this semiconductor substrate and be arranged on the selection grid of being made by polysilicon on this selection gate oxidation films; With
Reading circuit is used for this fuse MOS transistor of this store status ON/OFF according to this non-volatile memory cells;
Wherein at least one in this fuse MOS transistor and this reading circuit is configured to the peripheral circuit transistor by the MOS transistor realization, this peripheral circuit transistor comprises the peripheral circuit gate oxidation films that is arranged on this semiconductor substrate and is arranged on the peripheral circuit grid of being made by polysilicon on this peripheral circuit gate oxidation films that the polysilicon of these peripheral circuit grid is arranged to have the impurity concentration higher than the impurity concentration in the polysilicon of this floating grid.
22. a semiconductor device comprises:
Constant voltage produces circuit, comprise the output of control input voltage output driver, distribute output voltage and export the distributor resistance circuit of the voltage of this distribution, the generating circuit from reference voltage that produces reference voltage, comparison from the voltage of the distribution of this distributor resistance circuit with from the reference voltage of this generating circuit from reference voltage and control the comparison circuit of this output driver operation according to this comparative result;
This distributor resistance circuit comprises
A plurality of resistances are regulated resistive element, are connected in series;
A plurality of fuse MOS transistor, as this fuse element, itself and this resistance is regulated resistive element and is connected in parallel;
Non-volatile memory cells, comprise memory transistor and select transistor, this memory transistor is realized by MOS transistor, comprise the storage gate oxidation films that is arranged on the semiconductor substrate and be arranged on the floating grid of being made by polysilicon on this storage gate oxidation films, this floating grid is in electric floating state; This selection transistor is realized by the MOS transistor that is connected in series on this memory transistor, and is comprised the selection gate oxidation films that is arranged on this semiconductor substrate and be arranged on the selection grid of being made by polysilicon on this selection gate oxidation films; With
Reading circuit is used for this fuse MOS transistor of this store status ON/OFF according to this non-volatile memory cells;
Wherein at least one in this fuse MOS transistor and this reading circuit is configured to the peripheral circuit transistor by the MOS transistor realization, this peripheral circuit transistor comprises the peripheral circuit gate oxidation films that is arranged on this semiconductor substrate and is arranged on the peripheral circuit grid of being made by polysilicon on this peripheral circuit gate oxidation films that this polysilicon of these peripheral circuit grid is arranged to have the high impurity concentration of impurity concentration than in this polysilicon of this floating grid.
CN200580008875A 2004-12-24 2005-12-19 Semiconductor device Expired - Fee Related CN100576545C (en)

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JP5004419B2 (en) 2012-08-22
JP2006179750A (en) 2006-07-06

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