CN1925118A - Solid multi-grid component and its manufacturing method - Google Patents
Solid multi-grid component and its manufacturing method Download PDFInfo
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- CN1925118A CN1925118A CN 200510097896 CN200510097896A CN1925118A CN 1925118 A CN1925118 A CN 1925118A CN 200510097896 CN200510097896 CN 200510097896 CN 200510097896 A CN200510097896 A CN 200510097896A CN 1925118 A CN1925118 A CN 1925118A
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Abstract
This invention provides one space grating element and its process method, wherein, the element comprises one tar silicon, one grating structure and one stress adjusting layer; grating structure and tar silicon both sides contact into space grating structure with stress adjusting layer cover on the grating structure to provide grating with parallel force along its tank strengthening direction. This stress force can improve grating structure down groove area electron transferring to improve space grating element drive current characteristics.
Description
Technical field
The present invention relates to a kind of solid multi-grid component with and manufacture method, relate in particular to a kind of have solid multi-grid component that a stress adjusts layer with and manufacture method.
Background technology
Along with dwindling of semiconductor element size, the usefulness of keeping the small size semiconductor element is the main target of present industry.In order to improve the usefulness of semiconductor element, develop gradually at present and various solid multi-grid components.Solid multi-grid component comprises following several advantages.At first, the technology of solid multi-grid component can with traditional logic element process integration, therefore have suitable process compatibility; Secondly, because therefore the particularity of its structure need not carry out the electrical isolation of element from (shallow trench isolation) technology with traditional shallow trench isolation; Moreover, because stereochemical structure has increased the contact area of grid and substrate, therefore can increase the control of grid for the channel region electric charge, thereby the leakage inductance that the reduction small-sized component is brought answers potential barrier to reduce (Drain Induced Barrier Lowering, DIBL) effect and short-channel effect (short channel effect); In addition, because the grid of same length has bigger channel width, therefore also can increase the magnitude of current between source electrode and drain electrode.
Existing solid multi-grid structure still has development space on electron mobility.Therefore the present invention promptly improves at existing solid multi-grid component, with the usefulness of further lift elements.
Summary of the invention
The present invention disclose a kind of solid multi-grid component with and manufacture method, adjust layer by on grid structure, forming a stress, with the usefulness of effective lifting solid multi-grid component.
According to the present invention, provide a fin-shaped silicon of being located on the silicon-coated insulated body substrate, and fin-shaped silicon have a upper surface and two sides parallel to each other.Then on fin-shaped silicon, form a grid structure, and grid structure covers the upper surface and the part two sides of fin-shaped silicon part.Then fin-shaped silicon is carried out an ion implantation technology to form the regions and source of solid multi-grid component.Form at last one at least the stress of overlies gate structure adjust layer.
Compared to prior art, the solid multi-grid component of manufacturing of the present invention has a stress and adjusts layer.This stress adjustment layer can provide grid structure the stress parallel with orientation, and improves the electron mobility of grid structure below channel region, effectively promotes the electrical performance of solid multi-grid component.
Description of drawings
Fig. 1 to Fig. 9 is the method schematic diagram that a preferred embodiment of the present invention is made solid multi-grid component;
Figure 10 shows the electric current comparison diagram of the present invention and existing solid multi-grid component;
Figure 11 shows the difference of solid multi-grid component of the present invention and existing solid multi-grid component channel region electron mobility;
Figure 12 shows solid multi-grid component of the present invention and the difference of existing solid multi-grid component in the DIBL performance.
The main element symbol description
120 silicon substrate 134b silicon nitride layers
122 insulating barriers, 136,138 regions and source
124 monocrystalline silicon layers, 142 self-aligned metal silicate layers
125 oxide layers, 144 self-aligned metal silicate layers
126 hard mask oxide layer 146 self-aligned metal silicate layers
127 fin-shaped silicon, 150 stress are adjusted layer
128 sacrifice layers, 152 interlayer dielectric layers
130 nitrogen oxide layers, 154 contact holes
132 polysilicon layers, 156 patterned copper layer
133 polysilicon gate construction A sides
134 spacer structure B sides
134a skew oxide layer C upper surface
Embodiment
The invention provides a kind of solid multi-grid component with and manufacture method.Please refer to Fig. 1 to Fig. 9.Fig. 1 to Fig. 9 is a method schematic diagram of making solid multi-grid component according to a preferred embodiment of the invention, and Fig. 9 has also shown the solid multi-grid component structure of a preferred embodiment of the present invention.
At first please refer to Fig. 1, as shown in Figure 1, method of the present invention is a silicon-coated insulated body to be provided earlier (it comprises that a silicon substrate 120, is overlying on insulating barrier 122 and on the silicon substrate 120 and is overlying on monocrystalline silicon layer 124 on the insulating barrier 122 for silicon-on-insulator, SOI) substrate.At first monocrystalline silicon layer 124 is carried out an oxidation technology, with the upper surface C oxidation of monocrystalline silicon layer 124, to form an oxide layer 125.In the present embodiment, after the formation oxide layer 125, the thickness T of monocrystalline silicon layer 124 is maintained between 50 to 100 nanometers (nm).Then, as shown in Figure 2, form a photoresist layer (not shown) on oxide layer 125, and carry out a photoetching and etch process, the oxide layer 125 of removing the subregion hides the predetermined fin-shaped silicon place that forms to form the hard mask oxide layer 126 of a patterning.Then, utilize hard mask oxide layer 126 monocrystalline silicon layer 124 to be carried out etching, thereby form a fin-shaped silicon 127, as shown in Figure 3 as a hard mask.Certainly, also can monocrystalline silicon layer 124 be formed and be fin-shaped silicon 127 by alternate manner.After fin-shaped silicon 127 forms, subsequently in the two sides of fin-shaped silicon 127 A, the last formation of B sacrifice layer 128.Then, fin-shaped silicon 127 is carried out ion doping (shown in the arrow among Fig. 3), for example, mix, to adjust threshold voltage (Threshold Voltage, the V of solid multi-grid component with boron (B) ion or arsenic (As) ion
TH), and soon remove sacrifice layer 128, wherein the effect of sacrifice layer 128 is to be to make two sides A, the B of fin-shaped silicon 127 to have the excellent lattice arrangement.
Then as shown in Figure 4, form a nitrogen oxide layer 130 in fin-shaped silicon 127 two sides A, B.The formation of nitrogen oxide layer 130 can be by forming an oxide layer (not shown) on the two sides of fin-shaped silicon 127 A, B, utilize plasma that oxide layer is carried out nitrogenize again and reach.In the present embodiment, the thickness of nitrogen oxide layer 130 is about about 14 dusts ().After forming nitrogen oxide layer 130, then carry out a depositing operation, on insulating barrier 122 and fin-shaped silicon 127, to form a polysilicon layer 132.Then as shown in Figure 5, on polysilicon layer 132, form a photoresist layer (not shown), and carry out polysilicon layer 132 that a photoetching and etch process remove the subregion and be close to quadratures and length polysilicon gate construction 133 with fin-shaped silicon 127 about 80 nanometers to form one, it should be noted that wherein nitrogen oxide layer 130 in the present embodiment not to be removed and still remain in the sidewall of polysilicon gate construction 133 that the gate dielectric of being used as this solid multi-grid component uses.In addition, be positioned at hard mask oxide layer 126 on the fin-shaped silicon 127 when etching polysilicon layer 132 as the usefulness of etching stopping layer, protect fin-shaped silicon 127 to be unlikely impaired in the process of etching polysilicon layer 132 by this.
See also Fig. 6, Fig. 6 is that Fig. 5 is along the axial profile of 6-6 '.As shown in Figure 6, polysilicon gate construction 133 is carried out an ion implantation technology, phosphorus (P) ion or boron (B) ion of high concentration mixed in the polysilicon gate construction 133 so that polysilicon gate construction 133 has good electrical conductivity.Then form skew oxide layer (offset oxide layer) 134a and a silicon nitride layer 134b on polysilicon gate construction 133, hard mask oxide layer 126 and insulating barrier 122 in regular turn, the thickness that wherein is offset oxide layer 134a and silicon nitride layer 134b in the present embodiment is respectively 100 dusts and 500 dusts.As shown in Figure 7, etch away part silicon nitride layer 134b and skew oxide layer 134a subsequently in regular turn, to form a spacer structure 134 in polysilicon gate construction 133 both sides, simultaneously when making spacer structure 134, remove the hard mask oxide layer 126 that is not covered in the lump, in order to follow-up formation regions and source by spacer structure 134.Then carry out the ion implantation technology of a high concentration again, with ion doping in fin-shaped silicon 127, with in the fin-shaped silicon 127 of polysilicon gate construction 133 and spacer structure 134 down either side, form regions and source 136,138.For example, be to mix fin-shaped silicon 127 to form N type solid multi-grid component in the present embodiment with arsenic (As) ion and phosphonium ion.
As shown in Figure 8, carry out a self-aligned metal silicate (self-aligned silicide) technology, form self-aligned metal silicate layer 142,144,146 respectively in regions and source 136,138 and polysilicon gate construction 133 tops.Self-aligned metal silicate layer 142,144,146 can be cobalt (Co) self-aligned silicide layer or other for example nickel (Ni), titanium (Ti) or platinum self-aligned silicide layers such as (Pt).(chemical vapor deposition, CVD) technology are adjusted layer 150 to form a stress on polysilicon gate construction 133 and fin-shaped silicon 127 then to carry out a chemical vapour deposition (CVD).Stress adjustment layer 150 can be a silicon nitride layer, and can be by feed the precursor of nitrogen in CVD technology, and for example, (bis (tertiary-butylamino) silane BTBAS) reaches two (tert-butyl group amino) silane.Certainly also can adopt other technology, for example aumospheric pressure cvd technology, low-pressure chemical vapor deposition process and plasma enhanced chemical vapor deposition technology etc., and other material carries out the making that stress is adjusted layer 150.The thickness range that stress is adjusted layer 150 at 100 dusts () between 2000 dusts, and preferably between 400 dust to 1800 dusts.Stress adjustment layer 150 by this high thickness can provide high tensile stress or the high compression stress of solid multi-grid component in X-X ' direction.
Then, as shown in Figure 9, continue at and form dielectric layer (inter layer dielectric, ILD) 152 between one deck at least on the stress adjustment layer 150.Interlayer dielectric layer 152 can be one silica layer, and can pass through aumospheric pressure cvd method (atmospheric pressure chemical vapor deposition, APCVD) undoped silicon glass of Xing Chenging (un-doped silicon glass).Perhaps, (tetraethyl orthosilicate chemical vapor deposition is that dopant (dopant) forms phosphosilicate glass (phosphosilicate glass) with as interlayer dielectric layer 152 TEOS-CVD) and with phosphorus also can to utilize the tetraethyl orthosilicate chemical vapour deposition technique.Certainly, also can adopt other technology and other material to carry out the making of interlayer dielectric layer 152.After the making of finishing interlayer dielectric layer 152, then in interlayer dielectric layer 152, form a plurality of contact holes 154, and in contact hole 154, insert tungsten (W), as the usefulness of contact plunger.Then carry out the manufacturing of metal interconnecting, for example, form a patterned copper layer 156 in interlayer dielectric layer 152 tops and be electrically connected, with as external electric connection with contact plunger.May also have titanium nitride (TiN) layer (not shown) or tantalum nitride (TaN) (not shown) layer wherein between tungsten and contact hole 154 hole walls, and between patterned copper layer 156 and the interlayer dielectric layer 152 as the diffusion of diffused barrier layer with barrier metal.
Because having a stress, the solid multi-grid component that method of the present invention manufactures adjusts layer, channel region electron mobility and drive current characteristic in the time of therefore can effectively improving element conductive.What deserves to be explained is that the foregoing description is is example with N type solid multi-grid component, the silicon nitride of high tensile stress (Tensile Stress) can be provided is material so stress adjustment layer is to use; In fact if the element that institute's desire is made is a P type solid multi-grid component, then stress adjustment layer also can provide the material of high compression stress (Compressive Stress) to be constituted by other.For instance, the material of this stress adjustment layer also can be silica or silicon oxynitride etc.
In addition, Figure 10 to Figure 12 then shown solid multi-grid component of the present invention on usefulness with the existing unstressed difference of adjusting the solid multi-grid component of layer.Please refer to Figure 10, Figure 10 shows the electric current comparison diagram of the present invention and existing solid multi-grid component, and as shown in figure 10, the present invention has high switch current ratio (I
On/ I
Off).And according to Figure 10, the present invention has 26% current gain approximately with respect to existing solid multi-grid component.Then see also Figure 11, Figure 11 shows the difference of solid multi-grid component of the present invention and existing solid multi-grid component channel region electron mobility, by finding among Figure 11 that solid multi-grid component of the present invention obviously is better than existing solid multi-grid component in the performance of electron mobility.See also Figure 12, Figure 12 shows solid multi-grid component of the present invention and the difference of existing solid multi-grid component in the DIBL performance, and according to Figure 12, under the short situation of grid length, DIBL of the present invention is comparatively slight.In other words, compared to the existing unstressed solid multi-grid component of adjusting layer, it is electrical that the present invention has comparatively superior element operation, and promptly this stress adjustment layer can increase the usefulness of multi-grid component really.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (20)
1. method of making solid multi-grid component, this method may further comprise the steps:
(a) provide semi-conductive substrate, and form a fin-shaped silicon on this Semiconductor substrate, this fin-shaped silicon has a upper surface and two sides;
(b) form a grid structure on this fin-shaped silicon, this grid structure covers this upper surface of part and these two sides of part of this fin-shaped silicon;
(c) form two doped regions in this fin-shaped silicon that is arranged in these grid structure both sides and do not covered by this grid structure; And
(d) form a stress and adjust this grid structure of layer covering.
2. the method for claim 1, wherein this Semiconductor substrate is a silicon-coated insulated body substrate.
3. the method for claim 1 also is included in preceding these two sides in this grid structure of step (c) and forms a spacer structure.
4. the method for claim 1 also is included in step (c) back and forms a self-aligned metal silicate layer respectively at this grid structure and this two doped region top.
5. the method for claim 1, wherein this stress adjustment layer also covers this fin-shaped silicon.
6. the method for claim 1, wherein this stress is adjusted the thickness range of layer between 100 dust to 2000 dusts.
7. the method for claim 1, wherein this stress adjustment layer comprises a silicon nitride layer, one silica layer or a silicon oxynitride layer.
8. method as claimed in claim 7, wherein this silicon nitride layer is to form by carrying out a chemical vapor deposition method.
9. method as claimed in claim 8, wherein the precursor of this silicon nitride layer is two (tert-butyl group amino) silane.
10. the method for claim 1 also is included in step (d) back and adjusts upward at least one dielectric layer of formation of layer in this stress.
11. method as claimed in claim 10 also is included in this dielectric layer and this stress and adjusts a plurality of contact holes of formation in the layer.
12. a solid multi-grid component structure comprises:
Semi-conductive substrate;
One fin-shaped silicon is located on this Semiconductor substrate, and this fin-shaped silicon has a upper surface and two sides;
One grid structure is located on this fin-shaped silicon, and this grid structure covers this upper surface of part and these two sides of part of this fin-shaped silicon;
Two doped regions are located in this fin-shaped silicon of this grid structure down either side; And
One stress is adjusted layer, is covered on this grid structure.
13. solid multi-grid component structure as claimed in claim 12 also comprises a plurality of self-aligned metal silicate layers, is located at this grid structure and those doped regions top respectively.
14. solid multi-grid component structure as claimed in claim 13, wherein those self-aligned metal silicate layers comprise a cobalt, nickel, titanium or platinum self-aligned silicide layer.
15. solid multi-grid component structure as claimed in claim 12, wherein this stress adjustment layer comprises a silicon nitride layer, one silica layer or a nitrogen oxide layer.
16. solid multi-grid component structure as claimed in claim 12, wherein this stress is adjusted the thickness range of layer between 100 dust to 2000 dusts.
17. solid multi-grid component structure as claimed in claim 12 also comprises at least one dielectric layer, is located at this stress and adjusts on the layer.
18. solid multi-grid component structure as claimed in claim 17 also comprises a plurality of contact holes, runs through this dielectric layer and this stress and adjusts layer.
19. solid multi-grid component structure as claimed in claim 12, wherein this solid multi-grid component structure is the N type, and this stress adjustment layer provides a tensile stress.
20. solid multi-grid component structure as claimed in claim 12, wherein this solid multi-grid component structure is the P type, and this stress adjustment layer provides a compression stress.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456734A (en) * | 2010-10-29 | 2012-05-16 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103681272A (en) * | 2012-09-04 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for fin field effect transistor |
| CN103918083A (en) * | 2011-10-01 | 2014-07-09 | 英特尔公司 | Source/drain contacts for non-planar transistors |
| CN104217964A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Forming method of conductive plug |
| CN104701377A (en) * | 2013-12-04 | 2015-06-10 | 台湾积体电路制造股份有限公司 | Semiconductor device with strained layer |
| US9580776B2 (en) | 2011-09-30 | 2017-02-28 | Intel Corporation | Tungsten gates for non-planar transistors |
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2005
- 2005-09-02 CN CNB2005100978960A patent/CN100468657C/en active Active
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456734A (en) * | 2010-10-29 | 2012-05-16 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN102456734B (en) * | 2010-10-29 | 2015-06-10 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| US10020375B2 (en) | 2011-09-30 | 2018-07-10 | Intel Corporation | Tungsten gates for non-planar transistors |
| US9580776B2 (en) | 2011-09-30 | 2017-02-28 | Intel Corporation | Tungsten gates for non-planar transistors |
| US9637810B2 (en) | 2011-09-30 | 2017-05-02 | Intel Corporation | Tungsten gates for non-planar transistors |
| US9812546B2 (en) | 2011-09-30 | 2017-11-07 | Intel Corporation | Tungsten gates for non-planar transistors |
| CN103918083A (en) * | 2011-10-01 | 2014-07-09 | 英特尔公司 | Source/drain contacts for non-planar transistors |
| US10770591B2 (en) | 2011-10-01 | 2020-09-08 | Intel Corporation | Source/drain contacts for non-planar transistors |
| US10283640B2 (en) | 2011-10-01 | 2019-05-07 | Intel Corporation | Source/drain contacts for non-planar transistors |
| US9853156B2 (en) | 2011-10-01 | 2017-12-26 | Intel Corporation | Source/drain contacts for non-planar transistors |
| CN103681272A (en) * | 2012-09-04 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for fin field effect transistor |
| CN104217964A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Forming method of conductive plug |
| CN104701377B (en) * | 2013-12-04 | 2018-06-26 | 台湾积体电路制造股份有限公司 | Semiconductor devices with strained layer |
| US9831321B2 (en) | 2013-12-04 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with strained layer |
| CN104701377A (en) * | 2013-12-04 | 2015-06-10 | 台湾积体电路制造股份有限公司 | Semiconductor device with strained layer |
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| CN100468657C (en) | 2009-03-11 |
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