CN1920903B - Pixel distribution structure applied for flexible display unit - Google Patents
Pixel distribution structure applied for flexible display unit Download PDFInfo
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- CN1920903B CN1920903B CN2005100929038A CN200510092903A CN1920903B CN 1920903 B CN1920903 B CN 1920903B CN 2005100929038 A CN2005100929038 A CN 2005100929038A CN 200510092903 A CN200510092903 A CN 200510092903A CN 1920903 B CN1920903 B CN 1920903B
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Abstract
The invention relates to a pixel distribution used in soft display, used in one flexible base plate, and driven by one data line and one scanning line, wherein the invention is characterized in that: it has several film transistors; and it via different distributions is connected to several film transistors, therefore, the pixel can normally operate when the flexible base plate aims and deflects or being bended in the production, to improve the pixel reliability of said base plate.
Description
Technical field
The present invention relates to a kind of pixel arrangement structure,,, make the pixel arrangement structure that the fiduciary level of pixel effectively promotes on the bendable substrate with multiple different layout type particularly relevant on a kind of bendable substrate that is applied in flexible display.
Background technology
In recent years, flat-panel screens is constantly towards compact trend development, yet the display of present stage is show rich of the convenience that carries and information and can't reach and make the best of both worlds.In order to take into account rich that the convenience carried and information show, but development is bendable or the flexible display of coiled-type just seems quite important.Yet the pattern position alignment offset takes place in the bendable substrate of flexible display regular meeting in processing procedure because of thermal expansion; Or the panel of flexible display is in using during deflection, and the modular construction in the pixel ruptures easily.Above-mentioned two kinds of situations all can cause pixel bad and cause image and can't normally show.
The pixel layout of traditional monitor only comprises a thin film transistor (TFT) in the common dot structure, but and whether this pixel normally shows and need look whether operate as normal of this thin film transistor (TFT).See also Figure 1A, on known active plurality of groups of substrates of thin-film transistor 100, each dot structure drives with one scan line 120 by a data line 110, and comprise a thin film transistor (TFT) 130, wherein this thin film transistor (TFT) 130 is formed from the bottom to top with two electrodes 132, oxide 134, silicon materials 136.Yet, shown in Figure 1B and Fig. 1 C, this dot structure in processing procedure, take place because of thermal expansion pattern position aim at take place about the deflection and modular construction in the pixel is deformed or when rupturing in using of skew or panel, to make that this thin film transistor (TFT) 130 can't operate as normal, and cause this pixel normally to show.Known technology is for the solution of the problems referred to above, focus on the problem that solves metal wire and electric capacity fracture more, and there is no solution at the problem of assembly fracture on the panel, more not from the viewpoint of pixel layout design disclose any solution pattern position aim at take place about the means of skew or dot structure distortion.
Summary of the invention
Technical matters to be solved by this invention is by improving the layout type in the pixel, reduces the bad or substrate deflection of manufacture process contraposition and causes the bad chance of pixel, to improve the fiduciary level of pixel on the bendable substrate.
Secondary objective of the present invention is the layout type that utilizes in the multiple pixel, under the complexity that does not increase processing procedure, but guarantee to have at least in the dot structure thin film transistor (TFT) in the processing procedure contraposition operate as normal still during bad or substrate deflection, to reach the normal function that shows of pixel.
For achieving the above object, the present invention proposes a kind of pixel arrangement structure that is applied to flexible display, be suitable for being disposed on the bendable substrate, and drive by a data line and one scan line, wherein said pixel arrangement structure comprises a plurality of thin film transistor (TFT)s, each thin film transistor (TFT) comprises a gate, a passage and one source pole/drain, links these a plurality of thin film transistor (TFT)s with a layout type in the wherein said pixel arrangement structure.
Above-mentioned pixel arrangement structure, wherein said layout type is arranged at the channel of the both sides of described data line and described two thin film transistor (TFT)s with two thin film transistor (TFT)s, and each is parallel with described data line.
Above-mentioned pixel arrangement structure, wherein said layout type is arranged at the channel of a side of described data line and described two thin film transistor (TFT)s with two thin film transistor (TFT)s, and each is parallel with described data line.
Above-mentioned pixel arrangement structure, wherein said layout type will at least three thin film transistor (TFT)s be arranged at the channel of side of described data line and described thin film transistor (TFT) each is parallel with described sweep trace.
Above-mentioned pixel arrangement structure, wherein said layout type is arranged at side of described data line and orthogonal one-tenths L type with two thin film transistor (TFT)s, and the channel of described two thin film transistor (TFT)s is respectively parallel with described data line and described sweep trace.
Above-mentioned pixel arrangement structure, wherein said layout type is arranged at four thin film transistor (TFT)s the both sides of described data line, each side of described data line respectively has the channel of described two thin film transistor (TFT)s of orthogonal and each side of described two thin film transistor (TFT)s, and each is parallel with described data line and described sweep trace, and described thin film transistor (TFT) connects to the ㄇ type.
Above-mentioned pixel arrangement structure, wherein said bendable substrate is a plastic base.
Above-mentioned pixel arrangement structure, wherein said bendable substrate are a metal forming substrate.
Above-mentioned pixel arrangement structure, the silicon materials in the wherein said thin film transistor (TFT) can be amorphous silicon material.
Above-mentioned pixel arrangement structure, the silicon materials in the wherein said thin film transistor (TFT) can be polycrystalline silicon material.
Above-mentioned pixel arrangement structure, wherein said flexible display are TFT LCD.
Above-mentioned pixel arrangement structure, wherein said flexible display are AMOLED.
Above-mentioned pixel arrangement structure, wherein said thin film transistor (TFT) are the PMOS transistor.
Above-mentioned pixel arrangement structure, wherein said thin film transistor (TFT) are nmos pass transistor.
In a word, the present invention proposes a kind of pixel arrangement structure that is applied on the bendable substrate, its dot structure is different from conventional pixel and comprises a plurality of thin film transistor (TFT)s, and these a plurality of thin film transistor (TFT)s are linked mutually with multiple layout type, and the drive current of each thin film transistor (TFT) all is enough to promote this pixel institute's pull-up resistor and electric capacity, even so bad or substrate deflection deformation of processing procedure contraposition, as long as wherein there is the transistor can operate as normal, just can guarantee that this pixel can normally show, and then effectively promote the fiduciary level of pixel on the bendable substrate.
Description of drawings
Figure 1A is a pixel arrangement structure synoptic diagram on the substrate of known display;
Figure 1B is offset synoptic diagram to the right for the pattern position aligning takes place for the dot structure of known display in processing procedure;
Fig. 1 C is that the dot structure of known display pattern position takes place in processing procedure is aimed at and to be offset synoptic diagram left;
Fig. 2 A is applied to the 1st embodiment synoptic diagram of the pixel arrangement structure on the bendable substrate for the present invention;
Fig. 2 B is offset synoptic diagram to the left and right for the pattern position aligning takes place for the dot structure of the present invention the 1st embodiment in processing procedure;
Fig. 2 C is offset synoptic diagram up and down for the pattern position aligning takes place for the dot structure of the present invention the 1st embodiment in processing procedure;
Fig. 3 A is applied to the 2nd embodiment synoptic diagram of the pixel arrangement structure on the bendable substrate for the present invention;
Fig. 3 B is offset synoptic diagram left for the pattern position aligning takes place for the dot structure of the present invention the 2nd embodiment in processing procedure;
Fig. 3 C is offset synoptic diagram to the right for the pattern position aligning takes place for the dot structure of the present invention the 2nd embodiment in processing procedure;
Fig. 4 A is applied to the 3rd embodiment synoptic diagram of the pixel arrangement structure on the bendable substrate for the present invention;
Fig. 4 B upwards is offset synoptic diagram for the pattern position aligning takes place for the dot structure of the present invention the 3rd embodiment in processing procedure;
Fig. 4 C offsets downward synoptic diagram for the pattern position aligning takes place for the dot structure of the present invention the 3rd embodiment in processing procedure;
Fig. 5 A is applied to the 4th embodiment synoptic diagram of the pixel arrangement structure on the bendable substrate for the present invention;
Fig. 5 B takes place to be offset synoptic diagram about pattern position is aimed in processing procedure for the dot structure of the present invention the 4th embodiment;
Fig. 5 C is offset synoptic diagram up and down for the pattern position aligning takes place for the dot structure of the present invention the 4th embodiment in processing procedure;
Fig. 5 D aims at oblique skew synoptic diagram for pattern position takes place for the dot structure of the present invention the 4th embodiment in processing procedure;
Fig. 6 A is applied to the 5th embodiment synoptic diagram of the pixel arrangement structure on the bendable substrate for the present invention;
Fig. 6 B takes place to be offset synoptic diagram about pattern position is aimed in processing procedure for the dot structure of the present invention the 5th embodiment;
Fig. 6 C is offset synoptic diagram up and down for the pattern position aligning takes place for the dot structure of the present invention the 5th embodiment in processing procedure;
Fig. 6 D aims at oblique skew synoptic diagram for pattern position takes place for the dot structure of the present invention the 5th embodiment in processing procedure.
Wherein, Reference numeral:
100～multiple substrate
110～data line
120～sweep trace
132～electrode
134～oxide
136～silicon materials
200,300,400,500,600～bendable substrate
210,310,410,510,610～data line
220,320,420,520,620～sweep trace
230,330,430,530,630～thin film transistor (TFT)
232,332,432,532,632～electrode
236,336,436,536,636～silicon materials
240,340,440,540,640～thin film transistor (TFT)
242,342,542,642～electrode
246,346,446,546,646～silicon materials
450,650～thin film transistor (TFT)
456,656～silicon materials
652～electrode
660～thin film transistor (TFT)
666～silicon materials
Embodiment
For further cognitive and understanding being arranged to feature of the present invention, purpose and function, conjunction with figs. is described in detail as follows:
Fig. 2 A is depicted as the 1st embodiment of pixel arrangement structure of the present invention, this dot structure is suitable for being disposed on the bendable substrate 200, and drive by a data line 210 and one scan line 220, this pixel arrangement structure comprises two thin film transistor (TFT)s 230 and 240, this two thin film transistor (TFT) is simply represented with active region silicon materials 236 and 246, electrode 232,242 is in order to provide electric connection, and wherein this two thin film transistor (TFT) 230 and 240 layout are that be arranged at the channel of the both sides of this data line 210 and this two thin film transistor (TFT) each is parallel with this data line 210.By this layout type, even skew about pattern aim to take place slightly in the processing procedure shown in Fig. 2 B, has at least the transistor can operate as normal in the certain deviation scope; Even skew slightly up and down aim to take place in pattern in the processing procedure, shown in Fig. 2 C, also has at least the transistor can operate as normal in the certain deviation scope.Because each transistorized drive current all is enough to promote the resistance and the electric capacity of this pixel institute load, as long as so there is the transistor can operate as normal, just can guarantee that this pixel can normally show, though that is bad in the processing procedure contraposition, this pixel still can be reached the effect of normal demonstration.
Wherein this bendable substrate 200 can be a plastic base or a metal forming substrate, silicon materials in these transistors can be amorphous silicon material or polycrystalline silicon material, flexible display of the present invention be can use and TFTLCD or AMOLED comprised, these thin film transistor (TFT)s are decided on demand, may be selected to be PMOS transistor or nmos pass transistor.
Fig. 3 A is depicted as the 2nd embodiment of pixel arrangement structure of the present invention, this dot structure is suitable for being disposed on the bendable substrate 300, and drive by a data line 310 and one scan line 320, this pixel arrangement structure comprises two thin film transistor (TFT)s 330 and 340, this two thin film transistor (TFT) is simply represented with active region silicon materials 336 and 346, electrode 332,342 is in order to provide electric connection, and wherein this two thin film transistor (TFT) 330 and 340 layout are that be arranged at the channel of a side of this data line 310 and this two thin film transistor (TFT) each is parallel with this data line 310.By this layout type,, shown in Fig. 3 B, in the certain deviation scope, have at least the transistor can operate as normal even skew slightly left aim to take place pattern in the processing procedure; Or skew slightly to the right aim to take place in pattern in the processing procedure, shown in Fig. 3 C, also has at least the transistor can operate as normal in the certain deviation scope.Because each transistorized drive current all is enough to promote the resistance and the electric capacity of this pixel institute load, as long as so there is the transistor can operate as normal, just can guarantee that this pixel can normally show, though that is bad in the processing procedure contraposition, this pixel still can be reached the effect of normal demonstration.
Fig. 4 A is depicted as the 3rd embodiment of pixel arrangement structure of the present invention, this dot structure is suitable for being disposed on the bendable substrate 400, and drive by a data line 410 and one scan line 420, this pixel arrangement structure comprises a plurality of thin film transistor (TFT)s 430,440 and 450, these thin film transistor (TFT)s are simply represented with active region silicon materials 436,446 and 456, electrode 432 is in order to provide electric connection, and wherein the layout of these a plurality of thin film transistor (TFT)s is that be arranged at the channel of a side of this data line 410 and these a plurality of thin film transistor (TFT)s each is parallel with this sweep trace 420.By this layout type,, shown in Fig. 4 B, in the certain deviation scope, have at least the transistor can operate as normal even slightly upwards skew aim to take place pattern in the processing procedure; Or pattern aim to take place to offset downward slightly in the processing procedure, shown in Fig. 4 C, also has at least the transistor can operate as normal in the certain deviation scope.Because each transistorized drive current all is enough to promote the resistance and the electric capacity of this pixel institute load, as long as so there is the transistor can operate as normal, just can guarantee that this pixel can normally show, though that is bad in the processing procedure contraposition, this pixel still can be reached the effect of normal demonstration.
Fig. 5 A is depicted as the 4th embodiment of pixel arrangement structure of the present invention, this dot structure is suitable for being disposed on the bendable substrate 500, and drive by a data line 510 and one scan line 520, this pixel arrangement structure comprises two thin film transistor (TFT)s 530 and 540, this two thin film transistor (TFT) is simply represented with active region silicon materials 536 and 546, electrode 532,542 in order to provide electric connection, wherein the layout of this two thin film transistor (TFT) is a side and the orthogonal one-tenth L type that is arranged at this data line 510, and the channel of this two thin film transistor (TFT) 530 and 540 is respectively parallel with this data line 510 and this sweep trace 520.By this layout type, even skew about pattern aim to take place slightly in the processing procedure shown in Fig. 5 B, has at least the transistor can operate as normal in the certain deviation scope; Or skew slightly up and down aim to take place in pattern in the processing procedure, shown in Fig. 5 C, also has at least the transistor can operate as normal in the certain deviation scope; Even oblique slightly skew aim to take place in pattern in the processing procedure, shown in Fig. 5 D, also has at least the transistor can operate as normal in the certain deviation scope.Because each transistorized drive current all is enough to promote the resistance and the electric capacity of this pixel institute load, as long as so there is the transistor can operate as normal, just can guarantee that this pixel can normally show, though that is bad in the processing procedure contraposition, this pixel still can be reached the effect of normal demonstration.
Fig. 6 A is depicted as the 5th embodiment of pixel arrangement structure of the present invention, this dot structure is suitable for being disposed on the bendable substrate 600, and drive by a data line 610 and one scan line 620, this pixel arrangement structure comprises four thin film transistor (TFT)s 630,640,650 and 660, this four thin film transistor (TFT) is with active region silicon materials 636,646,656 and 666 simply expressions, electrode 632,642 and 652 in order to provide electric connection, wherein the layout of this four thin film transistor (TFT) respectively has two thin film transistor (TFT)s orthogonal and each is parallel with data line 610 and sweep trace 620 and connect to the ㄇ type for being arranged at these data line 610 both sides, and wherein thin film transistor (TFT) 636,666 and 646, each is parallel with this data line 610 and this sweep trace 620 for 656 channel.By this layout type, even skew about pattern aim to take place slightly in the processing procedure shown in Fig. 6 B, has at least the transistor can operate as normal in the certain deviation scope; Or skew slightly up and down aim to take place in pattern in the processing procedure, shown in Fig. 6 C, also has at least the transistor can operate as normal in the certain deviation scope; Even oblique slightly skew aim to take place in pattern in the processing procedure, shown in Fig. 6 D, also has at least the transistor can operate as normal in the certain deviation scope.Because each transistorized drive current all is enough to promote the resistance and the electric capacity of this pixel institute load, as long as so there is the transistor can operate as normal, just can guarantee that this pixel can normally show, though that is bad in the processing procedure contraposition, this pixel still can be reached the effect of normal demonstration.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (9)
1. pixel arrangement structure that is applied to flexible display, be suitable for being disposed on the bendable substrate, and drive by a data line and one scan line, it is characterized in that, described pixel arrangement structure comprises a plurality of thin film transistor (TFT)s, each thin film transistor (TFT) comprises a gate, a passage and one source pole/drain, link these a plurality of thin film transistor (TFT)s with a layout type in the wherein said pixel arrangement structure, even make that by described layout type pattern is aligned in the certain deviation scope, also have a described thin film transistor (TFT) operate as normal at least;
Wherein, two thin film transistor (TFT)s are arranged at the channel of the both sides of described data line and described two thin film transistor (TFT)s that each is parallel with described data line for described layout type; Perhaps
Described layout type is arranged at the channel of a side of described data line and described two thin film transistor (TFT)s with two thin film transistor (TFT)s, and each is parallel with described data line; Perhaps
Described layout type will at least three thin film transistor (TFT)s be arranged at the channel of side of described data line and described thin film transistor (TFT) each is parallel with described sweep trace; Perhaps
Described layout type is arranged at side of described data line and orthogonal one-tenths L type with two thin film transistor (TFT)s, and the channel of described two thin film transistor (TFT)s is respectively parallel with described data line and described sweep trace; Perhaps
Described layout type is arranged at four thin film transistor (TFT)s the both sides of described data line, each side of described data line respectively has the channel of described two thin film transistor (TFT)s of orthogonal and each side of two thin film transistor (TFT)s, and each is parallel with described data line and described sweep trace, and described four thin film transistor (TFT)s connect to the ㄇ type.
2. pixel arrangement structure according to claim 1 is characterized in that, described bendable substrate is a plastic base.
3. pixel arrangement structure according to claim 1 is characterized in that, described bendable substrate is a metal forming substrate.
4. pixel arrangement structure according to claim 1 is characterized in that, the silicon materials in the described thin film transistor (TFT) are amorphous silicon material.
5. pixel arrangement structure according to claim 1 is characterized in that, the silicon materials in the described thin film transistor (TFT) are polycrystalline silicon material.
6. pixel arrangement structure according to claim 1 is characterized in that, described flexible display is TFT LCD.
7. pixel arrangement structure according to claim 1 is characterized in that, described flexible display is AMOLED.
8. pixel arrangement structure according to claim 1 is characterized in that, described thin film transistor (TFT) is the PMOS transistor.
9. pixel arrangement structure according to claim 1 is characterized in that, described thin film transistor (TFT) is a nmos pass transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2005100929038A CN1920903B (en) | 2005-08-24 | 2005-08-24 | Pixel distribution structure applied for flexible display unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2005100929038A CN1920903B (en) | 2005-08-24 | 2005-08-24 | Pixel distribution structure applied for flexible display unit |
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| Publication Number | Publication Date |
|---|---|
| CN1920903A CN1920903A (en) | 2007-02-28 |
| CN1920903B true CN1920903B (en) | 2010-06-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2005100929038A Active CN1920903B (en) | 2005-08-24 | 2005-08-24 | Pixel distribution structure applied for flexible display unit |
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| Country | Link |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI648572B (en) * | 2017-05-05 | 2019-01-21 | 元太科技工業股份有限公司 | Active device array structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4786780A (en) * | 1987-04-21 | 1988-11-22 | Alps Electric Co., Ltd. | Method for trimming thin-film transistor array |
| CN1457450A (en) * | 2001-03-06 | 2003-11-19 | 皇家菲利浦电子有限公司 | Display device |
| US6911666B2 (en) * | 2002-07-11 | 2005-06-28 | Sharp Laboratories Of America, Inc. | Flexible metal foil substrate display and method for forming same |
| CN1655341A (en) * | 2004-02-10 | 2005-08-17 | 惠普开发有限公司 | Forming a plurality of thin-film devices |
-
2005
- 2005-08-24 CN CN2005100929038A patent/CN1920903B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4786780A (en) * | 1987-04-21 | 1988-11-22 | Alps Electric Co., Ltd. | Method for trimming thin-film transistor array |
| CN1457450A (en) * | 2001-03-06 | 2003-11-19 | 皇家菲利浦电子有限公司 | Display device |
| US6911666B2 (en) * | 2002-07-11 | 2005-06-28 | Sharp Laboratories Of America, Inc. | Flexible metal foil substrate display and method for forming same |
| CN1655341A (en) * | 2004-02-10 | 2005-08-17 | 惠普开发有限公司 | Forming a plurality of thin-film devices |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2005-99410A 2005.04.14 |
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Effective date of registration: 20220331 Address after: 26, 1 song Chi Road, Xinyi District, Taipei, Taiwan, China Patentee after: HANNSTAR DISPLAY Corp. Address before: Hsinchu County, Taiwan, China Patentee before: Industrial Technology Research Institute |
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