CN1917026A - Device for driving liquid crystal display - Google Patents
Device for driving liquid crystal display Download PDFInfo
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- CN1917026A CN1917026A CN 200610110827 CN200610110827A CN1917026A CN 1917026 A CN1917026 A CN 1917026A CN 200610110827 CN200610110827 CN 200610110827 CN 200610110827 A CN200610110827 A CN 200610110827A CN 1917026 A CN1917026 A CN 1917026A
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Abstract
A driving device of liquid crystal display is featured as avoiding transmitting clock signal to data driving unit not required to store image data in order to decrease unnecessary power consumption at various stages of data driving units.
Description
Technical field
The invention relates to a kind of LCD driving mechanism, particularly about a kind of LCD driving mechanism of saving power consumption and reducing electromagnetic interference (EMI).
Background technology
Fig. 1 shows traditional LCD Organization Chart.Traditional signal generation device 10, gray scale reference voltages generation device 20, direct-current voltage conversion device 30, liquid crystal panel 40, multi-stage data drive unit and multilevel scanning drive unit 50 have wherein been comprised.
Gray scale reference voltages generation device 20 is given this multi-stage data drive unit in order to produce gray scale reference voltages, adjusts as the GTG tone of image on display.Direct-current voltage conversion device 30 is in order to provide voltage to signal generation device 10, gray scale reference voltages generation device 20, multi-stage data drive unit and multilevel scanning drive unit 50.Signal generation device 10 is in order to clocking, picture output signal and multistage enabling signal.The multi-stage data drive unit, be first order data driven unit 60, second level data driven unit 61 from left to right in regular turn, up to the most right-hand n level data drive unit 63, mainly in order to the store images data, and output image data to liquid crystal panel 40 shows.Multilevel scanning drive unit 50 is in order to drive liquid crystal panel 40, to accept to come from the view data of data driven unit.Liquid crystal panel 40 is then in order to display image data.
By learning among the figure, traditional LCD framework, be various signals and the voltage that signal generation device 10, gray scale reference voltages generation device 20 and direct-current voltage conversion device 30 are exported, offer the data driven unit of each grade in the mode of transmission arranged side by side simultaneously.Yet the multi-stage data drive unit among the figure is to produce operation from left to right in regular turn with the store images data, exports liquid crystal panel 40 at last more simultaneously to and shows.In this process,, can operate because still receive clock signal, so cause unnecessary power consumption for data driven unit that as yet need the store images data.
Fig. 2 shows the sequential chart in the conventional liquid crystal.As shown in the figure, the negative edge of picture output signal wherein, t1 is detected in time point, so data driven unit at different levels (Fig. 1) all output image data to liquid crystal panel 40 show.When time point t2, first order enabling signal then drives first order data driven unit 60, with the store images data.Yet at the same time, second level data driven unit 61, up to n level data drive unit 63 though do not receive enabling signal with the store images data, still can be operated because receiving clock signal, therefore causes unnecessary power dissipation.
By above explanation as can be known, in special time, one-level data driven unit meeting store images data are only arranged, yet remaining data driven unit at different levels can be operated all, therefore causes unnecessary power dissipation because receiving clock signal.In view of this, a kind ofly can reduce unnecessary clock operation,, its demand and importance be arranged to reach the data driven unit of saving power consumption.
Summary of the invention
The objective of the invention is to propose a kind of data driven unit that can save power, by avoid with clock signal be sent to as yet not need the data driven unit of store images data in, to reduce unnecessary clock operation.
According to above-described purpose, the invention provides a kind of LCD driving mechanism, comprise signal generation device, a plurality of data driven unit.Wherein signal generation device can be exported clock stop signal, clock signal and clock enable signal.And clock signal stops output after clock stop signal produces, and begins output before clock enable signal produces.A plurality of data driven units are cascade arrangement, but the data driven unit receive clock signal and the clock enable signal of the first order, and the data driven unit that each is secondary can receive clock signal and clock enable signal that the data driven unit that comes from prime is exported.And clock stop signal is to input to each data driven unit in regular turn, stops clock signal to secondary data driven unit in order to make each data driven unit; And each data driven unit at the output clock enable signal to the secondary data driven unit, can first clock signal to the secondary data drive unit.
The present invention also provides a kind of LCD driving mechanism, comprises: signal generation device, output clock stop signal, clock signal and clock enable signal; Wherein this clock signal stops output after this clock stop signal produces, and begins output after this clock enable signal produces; A plurality of data driven units, these a plurality of data driven units are cascade arrangement, the data driven unit of the first order can receive this clock signal and this clock enable signal, and the data driven unit that each is secondary can receive this clock signal and this clock enable signal that the data driven unit that comes from prime is exported; And wherein this clock stop signal is to input to each this data driven unit in regular turn, stops to export this clock signal to this secondary data driven unit in order to make each this data driven unit; And each this data driven unit at this clock enable signal of output to this secondary data driven unit, export this clock signal to this secondary data drive unit.
Description of drawings
Fig. 1 shows traditional LCD Organization Chart;
Fig. 2 shows the sequential chart in the conventional liquid crystal;
Fig. 3 shows the LCD Organization Chart of one embodiment of the invention; And
Fig. 4 shows the sequential chart of LCD in one embodiment of the invention.
[main element label declaration]
10,110 signal generation devices
20,120 gray scale reference voltages generation devices
30,130 direct-current voltage conversion devices
40,140 liquid crystal panels
50,150 scanning driving devices
60,160 first order data driven units
61,161 second level data driven units
62,162 n-1 level data drive units
63,163 n level data drive units
Embodiment
Some embodiments of the present invention are described in detail as follows.Yet except describing in detail, the present invention can also implement widely in other embodiments, and scope of the present invention do not limit by the following example, and with after claim be as the criterion.
Fig. 3 shows the LCD Organization Chart that meets one embodiment of the invention.As shown in the figure, signal generation device 110, gray scale reference voltages generation device 120, direct-current voltage conversion device 130, liquid crystal panel 140, multi-stage data drive unit and multilevel scanning drive unit 150 have wherein been comprised.
In the present embodiment, gray scale reference voltages generation device 120 is given this multi-stage data drive unit in order to produce gray scale reference voltages equally, adjusts as the GTG tone of image on display.Direct-current voltage conversion device 130 is in order to provide voltage to signal generation device 110, gray scale reference voltages generation device 120, multi-stage data drive unit and multilevel scanning drive unit 150.Signal generation device 110 is in order to clocking, picture output signal and enabling signal.The multi-stage data drive unit, be first order data driven unit 160, second level data driven unit 161, n-1 level data drive unit 162 from left to right in regular turn, up to the most right-hand n level data drive unit 163, mainly in order to the store images data, and output image data to liquid crystal panel 140 shows.Multilevel scanning drive unit 150 is in order to drive liquid crystal panel 140, to accept to come from the view data of data driven unit.Liquid crystal panel 140 is then in order to display image data.
Conventional liquid crystal Organization Chart in Fig. 1, signal generation device 110 inside in the present embodiment have flip flop equipment (not shown), in order to when detecting the negative edge of picture output signal, temporarily stop clock signal and export first order data driven unit 160 to; And when the positive edge of enabling signal is detected, shifts to an earlier date a plurality of clock period and begin to export clock signal to first order data driven unit 160.In the present invention, utilize picture output signal as clock stop signal, and by detecting the output that its negative edge suspends clock signal; And utilize enabling signal as clock enable signal, and begin the output of clock signal by detecting its positive edge, will in after content in be described further.
In addition, framework compared to conventional liquid crystal, first order data driven unit 160, the second level data driven unit 161 of the embodiment of the invention in Fig. 3 up to the most right-hand n level data drive unit 163, is to connect mutually with serial connection (cascade) framework.Therefore, no matter be clock signal, picture output signal and the enabling signal of being exported by signal generation device 110, the voltage that direct-current voltage conversion device 130 is provided, the gray scale reference voltages that gray scale reference voltages generation device 120 is produced, all be to be orderly sent to first order data driven unit 160, second level data driven unit 161 is up to the most right-hand n level data drive unit 163.That is to say, every voltage and signal that first order data driven unit 160 is exported, can input to second level data driven unit 161, and every voltage and signal that second level data driven unit 161 is exported, input to the data driven unit of next stage again, till n level data drive unit 163.Save power consumption relevant for how the present invention avoids the unnecessary operations of data driven units at different levels, will in following content, explain by matching timing figure.
Fig. 4 shows the sequential chart of LCD in the embodiment of the invention.As shown in the figure, clock stop signal, first order clock enable signal, second level clock enable signal, tertiary clock enabling signal, n level clock enable signal, first order clock signal, second level clock signal, tertiary clock signal and n level clock signal have wherein been comprised.
Clock stop signal among the present invention, be picture output signal, mainly be to show in order to control data driven unit while output image data to liquid crystal panel at different levels, in the present invention owing to pass through the negative edge of detected image output signal, with the output of time-out clock signal, so the called after clock stop signal.Clock enable signals at different levels among the present invention, being enabling signal, mainly is to begin the store images data in order to start corresponding a certain level data drive unit, in the present invention because by detecting the positive edge of enabling signal, with the output of beginning clock signal, so the called after clock enable signal.
Explain hereinafter with reference to Fig. 3 and Fig. 4.At first, the clock stop signal (Fig. 4) that is produced when signal generation device 110 (Fig. 3), its negative edge is when time t1, flip flop equipment by signal generation device 110 inside detects, so clock signal stops first order clock signal (in order to offer first order data driven unit 160) and is maintained at logic-high state after process a plurality of clock period (for example 10 clock period) when time t3.Simultaneously, at time t1 during through the time t2 of (for example 7 clock period) after a plurality of clock period, stop second level clock signal (in order to offer second level data driven unit 161), n-1 level clock signal (in order to offer n-1 level data drive unit 162), up to n level clock signal (in order to offer n level data drive unit 163) and be maintained at logic-high state.
Then, the first order clock enable signal that is produced when signal generation device 110 just t5 is detected because of the time time, first order clock signal can be shifted to an earlier date a plurality of clock period (for example 5 clock period), when time t4, begin the running of recovered clock signal, therefore, first order data driven unit just can receive normal clock signal in time t4, when time t5 owing to receive first order clock enable signal (enabling signal), so can begin the store images data.
As shown in the figure, when time t5, because remaining second level clock signal, n-1 level clock signal, all be maintained at logic high up to n level clock signal, so corresponding second level data driven unit 161, the n-1 level data drive unit 162 that receives these clock signals can both be avoided causing power consumption because of the clock signal unnecessary operations up to n level data drive unit 163.
In like manner, when second level clock enable signal just t7 is detected because of the time time, second level clock signal can be shifted to an earlier date a plurality of clock period (for example 5 clock period), when time t6, begin the running of recovered clock signal, therefore, second level data driven unit just can receive normal clock signal in time t6, when time t7 owing to receive second level clock enable signal (enabling signal), so can begin the store images data.
By above explanation as can be known, data driven unit among the present invention, when some data driven units during in the store images data, remaining data driven unit can't receive normal clock signal, therefore can not cause non-essential clock operation and consumed power, reach the effect of saving power supply.
The above is preferred embodiment of the present invention only, is not in order to limit the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the described claim scope.
Claims (15)
1. LCD driving mechanism comprises:
Signal generation device, output clock stop signal, clock signal and clock enable signal;
Wherein this clock signal stops output after this clock stop signal produces, and begins output after this clock enable signal produces;
A plurality of data driven units, these a plurality of data driven units are cascade arrangement, the data driven unit of the first order can receive this clock signal and this clock enable signal, and the data driven unit that each is secondary can receive this clock signal and this clock enable signal that the data driven unit that comes from prime is exported; And
Wherein this clock stop signal is to input to each this data driven unit in regular turn, stops to export this clock signal to this secondary data driven unit in order to make each this data driven unit; And each this data driven unit at this clock enable signal of output to this secondary data driven unit, export this clock signal to this secondary data drive unit.
2. LCD driving mechanism according to claim 1 wherein also comprises the gray scale reference voltages generation device, gives these a plurality of data driven units in order to produce gray scale reference voltages.
3. LCD driving mechanism according to claim 1 wherein also comprises direct-current voltage conversion device, in order to provide voltage to this gray scale reference voltages generation device and this a plurality of data driven units.
4. LCD driving mechanism according to claim 1, wherein this signal generation device also comprises flip flop equipment, this flip flop equipment makes this signal generation device stop to export the data driven unit of this clock signal to this first order after receiving this clock stop signal.
5. LCD driving mechanism according to claim 4, wherein to the data driven unit of this first order, this flip flop equipment is exported the data driven unit of this clock signal to this first order to this signal generation device at this clock enable signal of output.
6. LCD driving mechanism according to claim 5, wherein the output time of the output time of this clock signal and this clock enable signal has the specific mistiming.
7. LCD driving mechanism according to claim 1, wherein each this data driven unit comprises flip flop equipment, and this flip flop equipment stops to export this clock signal to this secondary data driven unit after receiving this clock stop signal.
8. LCD driving mechanism according to claim 7, wherein to this secondary data driven unit, this flip flop equipment begins to export extremely this secondary data driven unit of this clock signal to each this data driven unit at this clock enable signal of output.
9. LCD driving mechanism according to claim 8, wherein the output time of the output time of this clock signal and this clock enable signal has the specific mistiming.
10. LCD driving mechanism comprises:
Signal generation device, output clock stop signal, clock signal and clock enable signal wherein comprise:
Flip flop equipment, this flip flop equipment make this signal generation device stop to export this clock signal after receiving this clock stop signal; This signal generation device is before this clock enable signal of output, and this flip flop equipment begins to export this clock signal;
A plurality of data driven units, these a plurality of data driven units are cascade arrangement, the data driven unit of the first order can receive this clock signal and this clock enable signal, and the data driven unit that each is secondary can receive this clock signal and this clock enable signal that the data driven unit that comes from prime is exported; And
Wherein this clock stop signal is to input to each this data driven unit in regular turn, stops to export this clock signal to this secondary data driven unit in order to make each this data driven unit; And each this data driven unit at this clock enable signal of output to this secondary data driven unit, export this clock signal to this secondary data drive unit.
11. LCD driving mechanism according to claim 10 wherein also comprises the gray scale reference voltages generation device, gives these a plurality of data driven units in order to produce gray scale reference voltages.
12. LCD driving mechanism according to claim 10 wherein also comprises direct-current voltage conversion device, in order to provide voltage to this gray scale reference voltages generation device and this a plurality of data driven units.
13. LCD driving mechanism according to claim 10, wherein each this data driven unit comprises flip flop equipment, and this flip flop equipment stops to export this clock signal to this secondary data driven unit after receiving this clock stop signal.
14. LCD driving mechanism according to claim 13, wherein to this secondary data driven unit, this flip flop equipment is exported extremely this secondary data driven unit of this clock signal to each this data driven unit at this clock enable signal of output.
15. LCD driving mechanism according to claim 14, wherein the output time of the output time of this clock signal and this clock enable signal has the specific mistiming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101108273A CN100517456C (en) | 2006-08-15 | 2006-08-15 | Device for driving liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101108273A CN100517456C (en) | 2006-08-15 | 2006-08-15 | Device for driving liquid crystal display |
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| Publication Number | Publication Date |
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| CN1917026A true CN1917026A (en) | 2007-02-21 |
| CN100517456C CN100517456C (en) | 2009-07-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006101108273A Expired - Fee Related CN100517456C (en) | 2006-08-15 | 2006-08-15 | Device for driving liquid crystal display |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102568404A (en) * | 2010-12-30 | 2012-07-11 | 联咏科技股份有限公司 | Time schedule controller, source electrode and panel driving device, display device and driving method |
| CN101868817B (en) * | 2007-11-20 | 2015-01-07 | 皇家飞利浦电子股份有限公司 | Power saving transmissive display |
| CN104715706A (en) * | 2013-12-11 | 2015-06-17 | 联咏科技股份有限公司 | Transmission method for display equipment |
| US9240157B2 (en) | 2010-12-17 | 2016-01-19 | Novatek Microelectronics Corp. | Timing controller, source driving device, panel driving device, display device and driving method for reducing power consumption through reducing standby durations |
| CN108806598A (en) * | 2018-08-31 | 2018-11-13 | 京东方科技集团股份有限公司 | Display device and its driver and method |
| CN109147678A (en) * | 2018-09-14 | 2019-01-04 | 联想(北京)有限公司 | Control method and electronic equipment |
-
2006
- 2006-08-15 CN CNB2006101108273A patent/CN100517456C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101868817B (en) * | 2007-11-20 | 2015-01-07 | 皇家飞利浦电子股份有限公司 | Power saving transmissive display |
| US9240157B2 (en) | 2010-12-17 | 2016-01-19 | Novatek Microelectronics Corp. | Timing controller, source driving device, panel driving device, display device and driving method for reducing power consumption through reducing standby durations |
| CN102568404A (en) * | 2010-12-30 | 2012-07-11 | 联咏科技股份有限公司 | Time schedule controller, source electrode and panel driving device, display device and driving method |
| CN102568404B (en) * | 2010-12-30 | 2014-12-17 | 联咏科技股份有限公司 | Time schedule controller, source electrode and panel driving device, display device and driving method |
| CN104715706A (en) * | 2013-12-11 | 2015-06-17 | 联咏科技股份有限公司 | Transmission method for display equipment |
| CN104715706B (en) * | 2013-12-11 | 2017-09-29 | 联咏科技股份有限公司 | Transmission method for display device |
| CN108806598A (en) * | 2018-08-31 | 2018-11-13 | 京东方科技集团股份有限公司 | Display device and its driver and method |
| CN108806598B (en) * | 2018-08-31 | 2020-04-03 | 京东方科技集团股份有限公司 | Display device and driver and method thereof |
| CN109147678A (en) * | 2018-09-14 | 2019-01-04 | 联想(北京)有限公司 | Control method and electronic equipment |
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| Publication number | Publication date |
|---|---|
| CN100517456C (en) | 2009-07-22 |
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Granted publication date: 20090722 Termination date: 20200815 |