CN1897511A - Boundary-information arrangement of just-in-circulation LDPC encoder - Google Patents

Abstract

The method comprises: the variable nodes and check nodes are separately divided into nb groups and mb groups; wherein, one of the variable groups is composed of the variable nodes corresponding to one column block in the Quasi-cyclic LDPC check matrix, and one of the check node groups is composed of the check nodes corresponding to one row block in the Quasi-cyclic LDPC check matrix; each group comprises L elements, and L is the amplification factor of the Quasi-cyclic LDPC check matrix; all positions of nodes neighboring a curtain variable node in one variable nodes group are putted together to form a row vector and a column vector, and the vectors corresponding to other variable nodes in a same column block are placed in the position parallel with the vector; its placing method is implemented by using formula [al/L]*L+(a modL+(I-1))modL in order to reduce the sizes of the memory and processor and to increase the decode speed.

Description

Side information arrangement method in the quasi-cyclic LDPC decoder

Technical field

The present invention relates to a kind of communication channel coding techniques field, refer to the side information arrangement method in a kind of quasi-cyclic LDPC decoder especially.

Background technology

Data can cause various mistakes in storage and transmission course, and the existence of these mistakes has limited the rate of information throughput and transmission quality greatly, in order to address this problem, usually adopt the method for chnnel coding, because the LDPC sign indicating number has low ERROR FLOOR and parallel decoding is subjected to great attention in modern development in science and technology.For the short code piece, A.J.Blanksby and C.J.Howland are at " A 690-mw 1-gb/s 1024-b; rate-1/2 low_density parity_check codedecoder ", IEEE J.Solid-state Circuits, vol.37, pp.404-412 has designed a complete parallel decoding implementation among the Mar.2002., but when code block was very big, the complexity between variable node and check-node made complete parallel decoding feasible hardly.

Zhongfeng Wang, Yanni Chen and Keshab K.Parhi are at " Area efficientdecoding of Quasi_Cyclic Low density parity check ", Acoustics, Speech andSignal Processing, Vol., 5, design among the May2004, and G..Al-Rawi and J.Cioffi two people are at " A highly efficient domain_programmable parallel architecture forLDPC decoding ", in Proc.ITCC, 2001, the design among the pp569-577 is to carry out parallel decoding by memory being divided into some little parts, and its shortcoming is that the processor chips area becomes greatly.

MustafaEroz, Feng-Wen Sun and Lin-Nan Lee are at " An innovativeLow_Density Parity_Check Code Design with Near-shannon_Limitperformance and simple implementation ", IEEE Trans.Communications, Vol.54, No.1, design among the Jan 2006 has proposed to have the sign indicating number design that structure read-write characteristics get final product complete parallel decoding, but the decoding to the LDPC sign indicating number is still part parallel decoding at present, promptly at ZhigangCao Jingyu Kang and Pingyi Fan.., at " An FPGA implementation ofstructured irregular LDPC Decoder ", 2005IEEE international Symposium onMicrowave, Antenna, the design among the Propagation and EMC Technologies for WirlessCommunication Proceedings is exactly this example.

Summary of the invention

The purpose of this invention is to provide the side information arrangement method in a kind of quasi-cyclic LDPC decoder, it can solve above-mentioned deficiency, makes to realize complete parallel decoding in the size that reduces memory and process chip.

To achieve these goals, technical solution of the present invention is: the side information arrangement method in a kind of quasi-cyclic LDPC decoder, and this method may further comprise the steps:

(1) at first variable node and check-node are divided into nb and mb group respectively, one of them variable node group is made up of pairing variable node of row piece in the check matrix of quasi-cyclic LDPC, in like manner, a check-node group is made up of pairing check-node of capable piece in the check matrix of quasi-cyclic LDPC, every group all contains L element, and L is the amplification factor of quasi-cyclic LDPC.

(2) next is put the adjoint point position of a certain variable node in the variable node group together and forms row vector or column vector, then be placed on the position parallel at the corresponding vector of the variable node of same row piece with it with this vector, the value of its component is provided by this vector components and formula [al/L] * L+ (amodL+ (I-1)) modL, I-1 is the poor of this variable and the first variable label, and [al/L] rounds al/L.

Side information arrangement method in the described quasi-cyclic LDPC decoder, wherein also available another of above-mentioned steps (2) put method: being put together in the position of the adjoint point of a certain check-node of a check-node group forms row vector or column vector, then the corresponding vector at the check-node of same row piece with it is placed on the position parallel with this vector, the value of its component is provided by this vector components and formula [al/L] * L+ (amodL+ (I-1)) modL, I-1 is the poor of this variable and the first variable label, and [al/L] rounds al/L.

Side information arrangement method in the described quasi-cyclic LDPC decoder, wherein above-mentioned variable node grouping is divided into groups according to row piece in the check matrix, and the check-node grouping is divided into groups according to row piece in the check matrix.

Side information arrangement method in the described quasi-cyclic LDPC decoder, wherein the node correlated components of same correspondence in the above-mentioned steps (2) provides according to formula [al/L] * L+ (amodL+ (I-1)) modL, I-1 is the poor of this variable and the first variable label, and [al/L] rounds al/L.

Side information arrangement method in the described quasi-cyclic LDPC decoder, the variable node group number n 1＜=nb of scheme wherein, check-node group number n 2＜=mb.

Side information arrangement method in the described quasi-cyclic LDPC decoder, wherein said side information is stored among the RAM by the mode of being suggested plans, and the location storage of first node in W is in ROM in the check-node group.

After adopting such scheme, the present invention is by grouping and dependence edge format to variable node and check-node, solved complexity to memory decoding, use this scheme to reduce the size of memory and processor and the complexity of realization of decoding, and can improve decoding speed greatly, use the present invention, as can be known by the emulation testing result, this scheme is feasible, and the present invention uses simply.

Embodiment

The present invention has provided the side information arrangement method in a kind of quasi-cyclic LDPC decoder, this method divides pairing check-node of capable piece in the check matrix of pairing variable node of row piece in the check matrix of quasi-cyclic LDPC and quasi-cyclic LDPC in a variable node group and a check-node group respectively, every group contains L element, L is the amplification factor of quasi-cyclic LDPC, if the basic matrix of quasi-cyclic LDPC is the mb*nb battle array, then variable node can be divided into the nb group, and check-node can be divided into the mb group; Certain variable node adjoint point position in the set of variables put together form row vector or column vector, corresponding vector at other variable node of same row piece is placed on the position parallel with this vector with it, its method of putting is that the value of each component is provided by the component and formula [al/L] * L+ (amodL+ (the I-1)) modL of primary vector, [al/L] expression rounds al/L, I-1 is the poor of this variable and the first variable label, and a mod L represents that a asks mould about L; Another method of putting is: being put together in the position of the adjoint point of a check-node in the check-node group forms row vector or column vector, corresponding vector at the check-node of same row piece is placed on the position parallel with this vector with it, and the relation of component value and primary vector is with the variable node situation.

The adjoint point of above-mentioned variable node is meant the set of the row number at non-" 0 " the element place in this variable node column.

The adjoint point of above-mentioned check-node is meant the set of the row number at this variable node non-" 0 " element place in being expert at.

Below by formula an explanation is done in the arrangement of side information:

If the adjoint point of first node during k check-node gathered is a ₁, a ₂, L, a _Dc*, have the characteristics of quasi-cyclic LDPC code to know that i adjoint point in this set is:

Cyclic matrix is L*L in the verification battle array of quasi-cyclic LDPC, and L is called amplification factor again.

Side information is arranged as follows:

$W=\left[\begin{array}{ccc}{V}_0& L& V_{L-1}\\ V_L& L& V_{2L-1}\\ M& M& M\\ V_{(n_b-1)L}& L& V_{n_{b}L-1}\end{array}\right]---\left(2\right).$

V _iBe the column vector that the adjoint point by i variable node constitutes, [V _KLV _KL+1V _KL+2L V _KL+L-1] the k row piece of corresponding hypermatrix H, V _KLBe the column vector of the adjoint point composition of first variable node in this row piece, and V _KL+iComponent then by V _KLRespective component and (3) formula: Provide.

Again in conjunction with specific embodiments, the present invention is described in further detail again below.

If the check matrix of QC-LDPC horse is as follows:

(1) have by said method:

$V_0=\left(\begin{array}{c}1\\ 2\\ 3\\ 5\end{array}\right),V_1=\left(\begin{array}{c}(1+1)\mathrm{mod}3\\ (2+1)\mathrm{mod}3\\ 3+(3\mathrm{mod}3+1)\mathrm{mod}3\\ 3+(5\mathrm{mod}3+1)\mathrm{mod}3\end{array}\right)=\left(\begin{array}{c}2\\ 0\\ 4\\ 3\end{array}\right),V_2=\left(\begin{array}{c}(1+2)\mathrm{mod}3\\ (2+2)\mathrm{mod}3\\ 3+(3\mathrm{mod}3+2)\mathrm{mod}3\\ 3+(5\mathrm{mod}3+2)\mathrm{mod}3\end{array}\right)=\left(\begin{array}{c}0\\ 1\\ 5\\ 4\end{array}\right),.$

Wherein a modb represents that a is about the b delivery.The put pairing matrix of above-mentioned node in memory is made as W

$W=\left[\begin{array}{ccc}{V}_0& V_1& V_2\\ V_3& V_4& V_5\end{array}\right].$

(2) determine the position of node in W in the check-node set

In this example, check-node collection c-groups and variable node collection v-groups respectively have 2, wherein c_groups[0]={ c ₀, c ₁, c ₂, c_groups[1]={ c ₃, c ₄, c ₅.c ₀The adjoint point collection be 1,2,3,5},

The adjoint point collection of c1 be 0,2,3,4}, i are i variable nodes.

By (1) and (2) as can be known, c ₀And c ₁Corresponding in order adjoint point on W goes together mutually, c ₁The row at adjoint point place=(c ₀The row of adjoint point+1) mod L, thereby the position that only need preserve first adjoint point in this set, also explanation is simultaneously suggested plans and is had the structure read write attribute.

Here how explanation determines the position of adjoint point in W of first point in the check-node group.As the concentrated c of second check-node ₃, its first adjoint point is v ₀, since it in H in the 0th row piece the 0th row, so it is arranged in the v of W ₀, v ₀In element be that 3 row is 2, so the position of this adjoint point in W is (2,0), wherein 3 is labels of c3, its second adjoint point is v for another example ₁, be arranged in H the 0th row piece the 1st row, so it is arranged in the 1st row and the 0th row piece, the i.e. V of W ₁, V ₁In element be that 3 row is 3, so the position of this adjoint point in W is (3,1), all the other are similar.

The above determines that the location method of node in W belongs to protection scope of the present invention in the check-node set, all any modifications of being done within the spirit and principles in the present invention, is equal to replacement, improvement etc., all is included in protection scope of the present invention.

Claims (6)

1, the side information arrangement method in a kind of quasi-cyclic LDPC decoder, it is characterized in that: this method may further comprise the steps:

(1) at first variable node and check-node are divided into nb and mb group respectively, one of them variable node group is made up of pairing variable node of row piece in the check matrix of quasi-cyclic LDPC, in like manner, a check-node group is made up of pairing check-node of capable piece in the check matrix of quasi-cyclic LDPC, every group all contains L element, and L is the amplification factor of quasi-cyclic LDPC.

(2) next is put the adjoint point position of a certain variable node in the variable node group together and forms row vector or column vector, then be placed on the position parallel at the corresponding vector of the variable node of same row piece with it with this vector, the value of its component is provided by this vector components and formula [al/L] * L+ (amodL+ (I-1)) modL, I-1 is the poor of this variable and the first variable label, and [al/L] rounds al/L.

2, the side information arrangement method in the quasi-cyclic LDPC decoder as claimed in claim 1, it is characterized in that: also available another of above-mentioned steps (2) put method: being put together in the position of the adjoint point of a certain check-node of a check-node group forms row vector or column vector, then the corresponding vector at the check-node of same row piece with it is placed on the position parallel with this vector, the value of its component is provided by this vector components and formula [al/L] * L+ (a modL+ (I-1)) modL, I-1 is the poor of this variable and the first variable label, and [al/L] rounds al/L.

3, the side information arrangement method in the quasi-cyclic LDPC decoder as claimed in claim 1 is characterized in that: above-mentioned variable node grouping is divided into groups according to row piece in the check matrix, and the check-node grouping is divided into groups according to row piece in the check matrix.

4, the side information arrangement method in the quasi-cyclic LDPC decoder as claimed in claim 1, it is characterized in that: the node correlated components of same correspondence in the above-mentioned steps (2) provides according to formula [al/L] * L+ (a modL+ (I-1)) modL, I-1 is the poor of this variable and the first variable label, and [al/L] rounds al/L.

5, the side information arrangement method in the quasi-cyclic LDPC decoder as claimed in claim 1 is characterized in that: the variable node group number n 1＜=nb of scheme, check-node group number n 2＜=mb.

6, the side information arrangement method in the quasi-cyclic LDPC decoder as claimed in claim 1, it is characterized in that: described side information is stored among the RAM by the mode of being suggested plans, and the location storage of first node in W is in ROM in the check-node group.