CN1625057A - High structural LDPC coding and decoding method and coder and decoder - Google Patents
High structural LDPC coding and decoding method and coder and decoder Download PDFInfo
- Publication number
- CN1625057A CN1625057A CN 200310118891 CN200310118891A CN1625057A CN 1625057 A CN1625057 A CN 1625057A CN 200310118891 CN200310118891 CN 200310118891 CN 200310118891 A CN200310118891 A CN 200310118891A CN 1625057 A CN1625057 A CN 1625057A
- Authority
- CN
- China
- Prior art keywords
- unit
- matrix
- check
- ldpc
- node unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
This invention discloses a highly structured LDPC coding and decoding methods. The code is through the checking matrix production unit of the encoder based on the pre-set code rate, column weight and row weight of HS-LDPC code to produce an odd-even checking matrix, and input the result into a compounding code unit of a coder, the compounding code unit calculates the input data information and the odd-even checking matrix, output the data information united by the odd-even checking information bit and input data information. The decoding method is according the need of the matrix odd-even checking code, pre-set the changeable node units, checks the number of the node units and the connecting units and the connecting structure, the changeable node units and the checking node units together complete the iterative decoding process of HS-LDPC code. This method can greatly reduce the complication of the hardware implementation of the entire decoder, compromises easily of the complicated degree and the speed of the hardware realization process.
Description
Technical field
The invention belongs to communication channel encoding and decoding technique field, particularly relate to a kind of highly structural parity check code coding method and the coding/decoding method and encoder thereof of correcting error of information channel fast and effectively of adopting.
Background technology
Data cause various mistakes through regular meeting in storage and transmission course.The reason that produces this mistake has synchronization loss, the multipath fading in the wireless transmission, the reasons such as magnetic track loss in the magnetic storage in random noise, the demodulating process.Because the existence of these mistakes, the rate of information throughput under the specific broadband and the quality of transmission have been limited greatly.Particularly in wireless multimedia transmission system, because lot of data will and be subjected at limited bandwidth keeping very high reliability in the Channel Transmission of various bursty interference, this problem becomes more outstanding.
In order to solve the integrity problem of data in transmission and storage, adopt the method for chnnel coding usually.In present existing coding method, low density parity check code (LDPC) causes very big attention because of its remarkable performance, and is widely regarded as one of up-and-coming error correction/encoding method in many telecommunications and the magnetic memory applications.The LDPC sign indicating number and the Turbo code of long code piece have similar performance, and one of their main difference is that the decoding of LDPC sign indicating number is easier, is more suitable in parallel processing in essence.This character is added its outstanding error-correcting performance makes it become coded system desirable in the high-speed wideband system applies.In addition, the interleaver that carries among the LDPC has avoided carrying out extra interleaving treatment between channel encoder and modulator.
C.Howland and A.Blanksby two people are at " Parallel decoding architectures forlow density parity check ", in Proc.of 2001 IEEE Int.Symp.On Circuits andSystems, Sydney has designed a parallel fully decoder architecture and has reached high decoding speed among the May 2001.Yet along with the increase of LDPC code length, owing to calculate and the too complexity of communicating by letter, its hardware realizes that complexity is high.Therefore, in most practical application, this parallel fully design all is not suitable for, and also is like this even only adopt under the situation of short code (code word size is less than 10000 bits).E.Boutillon, J.Castura, with people such as F.R.Kschischang at " Decoder-first code design ", in Proceedings of the 2nd InternationalSymposium on Turbo Codes and Related Topics, pp.459-462, Brest, France, the decoder architecture that has proposed a kind of part parallel among the Sept.2000 also designs has in view of the above realized decoder.But this decoder has comprised a large amount of random code generators, has caused the complexity increase in actual applications, makes that decoder global design and hardware implementation are further complicated.Recently, Tong Zhang and Keshab K.Parihi exist " Joint (3; k)-Regular LDPC Code andDecoder/Encoder Design ", among the to appear IEEE Transactions on Signal Process a kind of more structurized LDPC decoder has been proposed again, they have proposed a kind of simpler design, do not re-use randomizer (random number generator).But, utilized very complicated randomization internet (shuffle network) in this design, because higher route cost still can cause hardware to carry out (FPGA/ASIC) decreased performance.In addition, these encoding schemes are difficult to satisfy the needed high data transmission rate request of many high-speed applications eventually.
Summary of the invention
The present invention has overcome the deficiencies in the prior art part, and a purpose of the present invention is the coding method and the coding/decoding method of the LDPC sign indicating number (following table is shown the HS-LDPC sign indicating number) that proposed a kind of highly structural.This method has following several big advantage, makes it most suitable in practical application.Do not have complicated randomization network in this method, can greatly reduce the complexity that entire decoder hardware is carried out; Secondly, this method is a highly structural, is easy to trade off between hardware implementation complexity and speed according to the needs of types of applications.In addition, the potential decoding process of in a decoder core, realizing different code checks of this method.Systematized HS-LDPC encoder has lower hardware complexity in this method, can reach the data throughout up to 100Mbit/s.
The LDPC sign indicating number is a kind of linear error correction sign indicating number, and the linear error correction sign indicating number adopts a generator matrix G, the information s={s that will send
1, s
2..., s
mConvert the numeral t={t that is output to
1, t
2..., t
n, n＞m.Corresponding with generator matrix G is a check matrix H, and H satisfies Ht=0.The LDPC sign indicating number is that code length is the numeral of n, and L is 1 the very low matrix of density in its check matrix H.In check matrix H, the number of each row 1 is column weight j, and the number of each row is the heavy k of row, and (j, code check k) are (k-j)/k to the LDPC sign indicating number, and above-mentioned description is a content well known in the prior art usually.
HS-LDPC sign indicating number of the present invention is based on the code Design of the highly structural that on the basis of LDPC sign indicating number check matrix H is carried out, its coding method is: step 1, check matrix generation unit in the encoder is according to code check, the column weight of the HS-LDPC sign indicating number that sets in advance and heavily value generation one parity matrix of going, and the result that will generate imports a composite coding unit; Step 2, described composite coding unit carries out compose operation with the data message and the described parity matrix of input, obtains a data message with parity check code information; Step 3 is with the described data message output that is merged by parity information bit and the special position of input data information.
The preferred steps that described check matrix generation unit generates parity matrix is as follows:
Wherein, described composite coding unit comprises that a multiplication unit, first resolves unit, second and resolves a unit and a merge cells.Its concrete composite coding computing is, described multiplication unit carries out multiplying with the data message Xs of an input and a parity matrix information of described check matrix generation unit generation, with its as a result z be input to first and resolve the unit and resolve according to first unit solving equation Uy=z (U multiply by y and equals z), wherein y is the solving result of this unit, to resolve information y input second and resolve the unit, described second resolves the unit according to the second unit solving equation LXp=y, resolve, wherein U and L be on/lower triangular matrix, Xp is the data that have parity information, also is the solving result of this unit.At last, merge cells will have the data Xp of parity matrix information and the bit of input information Xs merges, and with its result's output.
Another object of the present invention has provided the coding/decoding method of a kind of HS-LDPC of being used for, its concrete method is as follows: according to the structure of parity matrix, preestablish the variable node unit of encoder, verification junction unit and number that is connected the variable node unit and corresponding syndeton, because decoder is in the process of carrying out decoding, the sub matrix in the same column and the work of treatment of submatrix are responsible in each variable node unit, the work of treatment of sub matrix and submatrix in being responsible for going together mutually in each check-node unit, so the variable node unit in the described encoder and the number of check-node unit are to be consistent with the structure of described parity matrix with being connected, described variable node unit heavily is worth according to the row of parity matrix and is provided with, and described check-node unit is provided with according to the column weight value of described parity check square.Described linkage unit is responsible for the interconnected of variable node unit and check-node unit, and it is that structure by parity matrix is determined, promptly is the matrix sequence of non-zero word in each row in the parity matrix.It is to be noted that these connections are also all fixed because fix when the MATRIX CHECK-UP sign indicating number.Wherein said variable node unit comprises a plurality of memory cell again, is used for storing the exchange message between variable node unit and the check-node unit.In decode procedure, what described variable node unit and check-node unit were finished the HS-LDPC sign indicating number jointly repeatedly is with decode procedure, and its processing procedure is according to the Log-BP algorithm, and this algorithm is conventional existing algorithm.
Wherein, described HS-LDPC coding/decoding method can be taked diverse ways according to following situation, when needs provide the situation of higher data transfer rate, can according to the actual needs described variable node unit and described check-node unit be divided, be divided into littler variable node unit and check-node unit, all variable node unit and check-node unit can the parallel processing data in decode procedure, increased the processing unit of more parallel running like this.When needs reduced the situation of complexity of hardware, the mode that described variable node unit and described check-node unit can be shared according to the simple time can and become a processing unit, thereby exchanges the reduction of hardware complexity for speed.According to different needs, can take all factors into consideration above-mentioned situation.
A further object of the present invention provides a kind of HS-LDPC encoder, and wherein said encoder is made up of check matrix generation unit and composite coding unit.A grow as required parity matrix and the result is input to the coding synthesis unit of described check matrix generation unit.Described composite coding unit comprises that a multiplication unit, first resolves unit, second and resolves a unit and a merge cells.The parity matrix information that the data message Xs of one input and described check matrix generation unit generate is input in the described multiplication unit, described multiplication unit carries out multiplying to above-mentioned information, and its result is input to described first resolves the unit, described first resolve the unit according to first resolve equation to the input information settle accounts, it will resolve result of information and import described second and resolve the unit, described second resolve the unit according to its second resolve equation to the input information resolve, this moment, the result that resolves of output was the data with parity check code information, described second resolves the result that will resolve the unit is input to described merge cells, described merge cells merges the bit of the data Xp that will have parity check code information and input information Xs, and with its result's output.
A further object of the present invention provides a kind of HS-LDPC decoder, and wherein said decoder is by a variable node unit, and check-node unit and the linkage unit that connects between changing cell and the verification unit are formed.Wherein said variable node unit comprises a plurality of memory cell again, is used for storing the exchange message between changing cell and the verification unit.Described linkage unit is used for variable node unit and check-node unit interconnected, and it is determined by the parity matrix structure.Described each variable node unit is used for the calculating to same column sub matrix and submatrix, and each verification unit is used for the calculating of colleague's sub matrix and submatrix mutually.The number of wherein said variable node unit is heavy relevant with the row of MATRIX CHECK-UP sign indicating number, and the number of described check-node unit is relevant with the column weight of MATRIX CHECK-UP sign indicating number.
Description of drawings
Fig. 1 is the structure chart of the parity check matrix H in the HS-LDPC coding method of the present invention;
Fig. 2 is that a code check being used for HS-LDPC coding method of the present invention is 1/2 HS-LDPC decoder;
Fig. 3 is that a code check being used for HS-LDPC coding method of the present invention is 5/8 HS-LDPC decoder;
Fig. 4 is the encoder that is used for HS-LDPC coding method of the present invention;
Fig. 5 is the matrix P displacement table of first embodiment of HS-LDPC coding method of the present invention;
Fig. 6 is the matrix S displacement table of first embodiment of HS-LDPC coding method of the present invention;
Fig. 7 is the matrix P displacement table of second embodiment of HS-LDPC coding method of the present invention;
Fig. 8 is the matrix S displacement table of second embodiment of HS-LDPC coding method of the present invention;
Fig. 9 is the table of comparisons of systematic function and simulated effect under the system of HS-LDPC coding method of the present invention and the DVB-T system;
Figure 10 is the error rate (BER) the simulation result figure of HS-LDPC sign indicating number that adopts 1/2 code check of QPSK in the HS-LDPC coding method of the present invention in different channels;
Figure 11 is the error rate BER simulation result figure of HS-LDPC sign indicating number that adopts 3/4 code check of 16QAW in the HS-LDPC coding method of the present invention in different channels;
Figure 12 is the HS-LDPC code check BER simulation result figure that adopts 8/9 code check of 64QAW in the HS-LDPC coding method of the present invention in different channels.
Embodiment
Now embodiments of the invention are described in detail in conjunction with concrete accompanying drawing.Embodiment one is to be that 1/2 long code is carried out HS-LDPC coding method of the present invention and coding/decoding method with encoding rate.
For example to be 9036 HS-LDPC (3 to code check 1/2, code length, 6) sign indicating number is encoded, the encoder of HS-LDPC of the present invention as shown in Figure 4, at first, the check matrix generation unit of described encoder is according to the HS-LDPC (3 that will encode, 6) Ma code length 9036, column weight j is 3, it is generated sub matrix is H
0, H
1, H
2Check matrix H, as shown in Figure 1, according to the heavy k of row of HS-LDPC (3,6) be 6 and its code length be 9036 so code length 9036 can be weighed 6 divided by row, with the H of the sub matrix of described check matrix
0, H
1, H
2Further generate 1506 submatrix A again
0, A
1... A
k, B
0, B
1... B
k, C
0, C
1... C
k, because 1 code length is 1, so the code length of sub matrix can be considered 1506, as shown in Figure 1, divided by the heavy k value 6 of row, and then the number of generation unit matrix I is 251 and then can obtains I by unit matrix at the code length that utilizes sub matrix
(i, j), be the unit matrix of 251X251.Unit matrix P among the H1
(i, j)Be according to corresponding I
(i, j)The unit matrix cyclic shift obtains, and represents that with T the operator of right cyclic shift is represented right cyclic shift operator with T, and Tu (i) represents circulate mobile u row, P so to the right
(i, j)=Tu (i).For example,
Here, u is 2.
Equally, H
1In unit matrix S
(i, j)Also be according to corresponding I
(i, j)The random rotation displacement of unit matrix.Provide each P that chooses as Fig. 5
(i, j)Number of shift bits.Fig. 6 has listed S
(i, j)The number of shift bits of choosing according to Performance Evaluation in the overall random number.At last, by obtaining a parity check matrix H after the cyclic shift, it is to have three sub matrixs and a parity matrix of the highly structural that is made of 1506 submatrixs that the unit matrix of 251X251 carries out forming after the cyclic shift.Described check matrix generation unit is with this information input composite coding unit.As shown in Figure 4, the multiplication unit of described composite coding unit carries out multiplying with the data message Xs and the described parity matrix information of an input, with its as a result z be input to first and resolve the unit, first resolves the unit resolves according to first unit solving equation Uy=z (U multiply by y and equals z), wherein y is the solving result of this unit, to resolve information y input second and resolve the unit, second resolves the unit according to the second unit solving equation LXp=y, resolve, wherein U and L be on/lower triangular matrix, Xp is the data that have parity information, also is the solving result of this unit.At last, merge cells will have the data Xp of parity check code information and the bit of input information Xs merges, and with its result's output.
The code check that the present invention as shown in Figure 2 is used for the HS-LDPC coding method is 1/2 HS-LDPC decoder, its structure be connected that the structure that is the parity check matrix H that generates according to above-mentioned check matrix generation unit sets, each variable node unit is to the calculating of sub matrix in the same column and submatrix, and each check-node unit is used for the calculating of colleague's sub matrix and submatrix mutually.So the variable node unit in the described encoder and the number of check-node unit are to be consistent with the structure of described parity matrix with being connected, described variable node unit heavily is worth according to the row of parity matrix and is provided with, and described check-node unit is provided with according to the column weight value of described parity matrix.Described linkage unit is responsible for the interconnected of variable node unit and check-node unit, and it is that structure by parity matrix is determined, promptly is the matrix sequence of non-zero word in each row in the MATRIX CHECK-UP sign indicating number.Here, can obtain described encoder by resulting parity check matrix H and have 36 parallel variable node VNC, the check-node unit CNU of 18 parallel runnings is connected with CNU with VNC with 3 linkage units, as shown in Figure 2.Wherein said variable node unit comprises a plurality of memory cell again, is used for storing the exchange message between variable node unit and the check-node unit.In decode procedure, what described variable node unit and check-node unit were finished the HS-LDPC sign indicating number jointly repeatedly is with decode procedure, and its processing procedure realizes according to the Log-BP algorithm.
Embodiment two is to be that 5/8 long code is carried out HS-LDPC coding method of the present invention and coding/decoding method with encoding rate.It only is that with embodiment one difference the structure of the decoder that check matrix parity check matrix H that generation unit generates in the described encoder is different and relevant with the H structure changes, other Code And Decode process and embodiment one are basic identical, just no longer repeat here.
Described check matrix generation unit according to HS-LDPC sign indicating number (3,8) as can be known its column weight j be 3, can generate sub matrix is H
0, H
1, H
2Parity check matrix H, again according to its row heavy k be 8 because and code length be 9472 thus can with code length 9472 divided by the row weigh 8, generate 1184 described verification sub matrix H
0, H
1, H
2The syndrome matrix A
0, A
1... A
k, B
0, B
1... B
k, C
0, C
1... C
k,,, be 148 divided by the number of the heavy k value of row 8 generation unit matrix I and then can obtain I by unit matrix at the code length that utilizes sub matrix so the code length of sub matrix can be considered 1184 because 1 code length is 1
(i, j), the unit matrix of 148X148.H
1In unit matrix P
(i, j)Be according to corresponding I
(i, j)The unit matrix cyclic shift obtains, and the algorithm here is identical with embodiment one, i.e. P
(i, j)=Tu (i).Unit matrix S among the H1
(i, j)Also be according to corresponding I
(i, j)The random rotation displacement of unit matrix.Provided each P as Fig. 6 and Fig. 7
(i, j)And S
(i, j)Number of shift bits u.At last, by obtaining a parity check matrix H after the cyclic shift, it is to have three sub matrixs and carry out 1148 submatrixs that form after the cyclic shift and a parity matrix of the highly structural that constitutes by the unit matrix of 148X148.Described check matrix generation unit is with this information input synthesis unit.
The code check that the present invention as shown in Figure 3 is used for the HS-LDPC coding method is 5/8 HS-LDPC decoder, its structure be connected that the structure that is the parity check matrix H that generates according to above-mentioned check matrix generation unit sets, each variable node unit is to the calculating of sub matrix in the same column and submatrix, and each check-node unit is used for the calculating of colleague's sub matrix and submatrix mutually.So the variable node unit in the described encoder and the quantity of check-node unit are to be consistent with the structure of described parity matrix with being connected, described variable node unit heavily is worth according to the row of parity matrix and is provided with, and described check-node unit is provided with according to the column weight value of described parity matrix.Described linkage unit is responsible for the interconnected of variable node unit and check-node unit, and it is that structure by parity matrix is determined.Here, described encoder has 32 parallel variable node VNC, and the check-node unit CNU of 12 parallel runnings is connected with CNU with VNC with 3 linkage units.Wherein said variable node unit comprises a plurality of memory cell again, is used for storing the exchange message between variable node unit and the check-node unit.According to the needs of parity check matrix H, realize fixedly connected between VNU and the CNU with three routers in the drawings.In order to reduce hard-wired complexity, the VNU of this decoder and CNU have adopted shared mode of time, and each VNU is responsible for facing mutually the work of treatment of submatrix in two row, and each CNU is responsible for facing mutually the evaluation work of submatrix in two row.The contrast code check be 1/2 LDPC the decoder block diagram as can be seen, the structure of two decoders is closely similar, and this structurized just H matrix is determined.In decode procedure, what described variable node unit and check-node unit were finished the HS-LDPC sign indicating number jointly repeatedly is with decode procedure, and its processing procedure realizes according to the Log-BP algorithm.
The present invention is that example describes HS-LDPC decoding method of the present invention with 1/2 code check and 5/8 code check only, and HS-LDPC coding method of the present invention is not limited only to the foregoing description also can be also to be applicable to different code checks.
Utilize HS-LDPC Code And Decode method involved in the present invention to make data when transmission, when particularly data-signal transmits on different logic channels, can adopt modulation/coding configuration flexibly, can grasp as required and flexibly on digit rate transmission rate and hardware complexity, this gives needs the bigger multi-medium data transmission in broadband to bring bigger facility.The effect of HS-LDPC Code And Decode of the present invention with and performance in whole system also have obvious superiority, as shown in Figure 9, the table of comparisons of systematic function and simulated effect under employing HS-LDPC coding method and DVB-T system, wherein under same code rate, at low data rate, under the situation of middle data transfer rate and High Data Rate, adopt the data transfer rate that transmits in the DVB-T system all to be lower than the data transfer rate that adopts the HS-LDPC system, and adopt the threshold value in the DVB-T system all to be higher than the needed threshold value of HS-LDPC system, that is to say that the needed hardware complexity of HS-LDPC system significantly is lower than the needed hardware complexity of DVB-T system.That Figure 10 is extremely shown in Figure 12 is the error rate under the different amplitude modulation is adopted in coding method of the present invention in different channels simulated effect figure, and it illustrates that clearly coding method of the present invention has superior error-correcting performance.
Those of ordinary skills can carry out multiple different modification to the present invention in spirit of the present invention and viewpoint.All equal variation and modifications of being done according to claims scope of the present invention are all the scope that the present invention protects.
Claims (19)
1. the coding method of the LDPC of a highly structural, it comprises the steps:
Step 1, the check matrix generation unit by an encoder is according to heavy value generation one parity matrix of code check, column weight and the row of the LDPC sign indicating number of the highly structural that sets in advance, and the result that will generate imports a composite coding unit of an encoder;
Step 2, described composite coding unit carries out compose operation with the data message and the described parity matrix of input, obtains a data message with parity matrix information;
Step 3 is with the described data message output that is merged by parity information bit and input data information bit.
2. the coding method of the LDPC of highly structural as claimed in claim 1, the step that wherein said check matrix generation unit becomes to give birth to parity matrix is:
Step 1, the check matrix generation unit is fixed as 3 according to the column weight of the LDPC sign indicating number of highly structural, generates the check matrix with three verification sub matrixs;
Step 2, heavy according to the row in the LDPC sign indicating number of the code length of the LDPC sign indicating number of highly structural and highly structural, divide square to generate some block check submatrixs described verification;
Step 3 heavily is worth divided by the row in the LDPC sign indicating number of described highly structural according to the code length of described syndrome matrix and obtains a verification unit matrix;
Step 4, described verification unit matrix carried out cyclic shift in all verification sub matrixs after, obtain a parity matrix;
Step 5 is input to a resulting parity matrix information composite coding unit of encoder.
3. the coding method of the LDPC of highly structural as claimed in claim 1 or 2, wherein, the column weight of described parity matrix (j) is fixed as 3, and row heavy (k) changes according to different code checks.
4. the LDPC coding method of a kind of highly structural as claimed in claim 3, wherein said parity matrix is by three syndrome matrix (H
0), (H
1), (H
2) constitute.
5. the LDPC coding method of highly structural as claimed in claim 4, wherein, described verification sub matrix H
0, be by the square I of unit
(i, j)The battle array cyclic shift constitutes described sub matrix H
1, be by the square P of unit
(i, j)The battle array cyclic shift constitutes described sub matrix H
2, be by the square S of unit
(i, j)The battle array cyclic shift constitutes.
6. the LDPC coding method of highly structural as claimed in claim 5, wherein, described cyclic shift is the displacement P that carries out according to following formula
(i, j)=Tu (i), T represent that the operator of right cyclic shift represents right cyclic shift operator with T, Tu (i) the representative mobile u row that circulate to the right.
7. the LDPC coding method of highly structural as claimed in claim 5, wherein, described cyclic shift is the displacement S that carries out according to following formula
(i, j)=Tu (i), T represent that the operator of right cyclic shift represents right cyclic shift operator with T, Tu (i) the representative mobile u row that circulate to the right.
8. the coding method of the LDPC of highly structural as claimed in claim 1, wherein, the composite coding operation method of described composite coding unit is,
Step 1, a multiplication unit carries out multiplying with the parity matrix information Hs that the data message Xs and the described check matrix generation unit of an input generates, with its as a result z be input to first and resolve the unit and resolve;
Step 2, described first resolves the unit resolves equation Uy=z (U multiply by y and equals z) according to first unit, and wherein y is the solving result of this unit, will resolve information y input second and resolve the unit and resolve;
Step 3, described second resolves the unit resolves equation L Xp=y according to Unit second, wherein U and L be on/lower triangular matrix, Xp is the data that have parity information, also is that the solving result of this unit is imported a merge cells;
Step 4, described merge cells will have the data Xp of parity matrix information and the bit of input information Xs merges, and with its result's output.
9. the LDPC encoder of a highly structural, wherein, described encoder is made up of a check matrix generation unit and a composite coding unit, wherein,
Described check matrix generation unit is according to code check, the column weight of the HS-LDPC sign indicating number that sets in advance and heavily value generation one parity matrix of going, and the result that will generate imports described composite coding unit;
It is used for described composite coding unit the data message and the described parity matrix of input are carried out compose operation, obtain a data message with parity matrix information, and with the described data message output that merges by parity information bit and the special position of input data information.
10. the LDPC encoder of highly structural as claimed in claim 9, wherein said composite coding unit resolves the unit by a multiplication method unit, first, second resolves unit and merge cells composition, and the information bit (Xs) that described multiplication unit is used for importing carries out multiplying and obtains signal (z) and the unit is resolved in this signal input first;
Described first resolves the unit is used for resolving equation according to first and resolves, and will resolve and obtain one and resolve information (Uy) input second and resolve the unit;
Described second resolves the unit is used for resolving equation according to second and will resolves once more from the information (Uy) that resolve unit output, obtains having the data of parity information and these data Xp being input to merge cells;
Described merge cells is used for merging having the data Xp of parity check code information and the bit of input information Xs, and with its result's output.
11. the LDPC coding/decoding method of a highly structural, it comprises the steps:
Step 1 according to the structure of parity matrix, preestablishes the variable node unit of encoder, the number of verification junction unit and linkage unit and corresponding syndeton;
Step 2, in the process of carrying out decoding, the sub matrix in the same column and the work of treatment of submatrix are responsible in each variable node unit, the work of treatment of sub matrix and submatrix during each check-node is responsible for going together mutually, described linkage unit is responsible for the interconnected of variable node unit and check-node unit, wherein said variable node unit comprises a plurality of memory cell again, is used for storing the exchange message between variable node unit and the check-node unit.；
What step 3, described variable node unit and check-node unit were finished the HS-LDPC sign indicating number jointly repeatedly is with decode procedure.
12. the coding/decoding method of the LDPC of highly structural as claimed in claim 11, variable node unit in the wherein said encoder and the quantity of check-node unit are to be consistent with the structure of described MATRIX CHECK-UP sign indicating number with being connected, described variable node unit heavily is worth according to the row of parity matrix check code and is provided with, described check-node unit is provided with according to the column weight value of described parity matrix verification, and described linkage unit is determined by the sequence of the word matrix of non-zero in each row in the structure of MATRIX CHECK-UP sign indicating number.
13. as the coding/decoding method of the LDPC of claim 11 or 12 described highly structurals, wherein said linkage unit is to be fixedly coupled the unit.
14. as the coding/decoding method of the LDPC of claim 11 or 12 described highly structurals, wherein said linkage unit is a router.
15. as the coding/decoding method of the LDPC of claim 11 or 12 described highly structurals, wherein said iterative decoding algorithm is to adopt the Log-BP algorithm.
16. coding/decoding method as the LDPC of claim 11 or 12 described highly structurals, wherein when the situation of higher data transfer rate need be provided, can according to the actual needs described variable node unit and described check-node unit be divided, be divided into littler variable node unit and check-node unit, variable node unit and check-node unit all in decode procedure can the parallel processing data.
17. coding/decoding method as the LDPC of claim 11 or 12 described highly structurals, wherein when the situation of the complexity that need to reduce hardware, the mode that described variable node unit and described check-node unit can be shared according to the simple time can and become a processing unit.
18. coding/decoding method as the LDPC of claim 11 or 12 described highly structurals, wherein can be according to actual conditions, the mode of taking the variable node unit that described variable node unit and described check-node dividing elements is littler and check-node unit and can and becoming a processing unit to combine the mode that described variable node unit and described check-node unit were shared according to the simple time.
19. the LDPC decoder of a highly structural, described decoder are by a variable node unit, check-node unit and the linkage unit that connects between changing cell and the verification unit are formed;
Wherein said each variable node unit is used for the calculating to same column sub matrix and submatrix, and the number of variable node unit is according to heavy setting of row of MATRIX CHECK-UP sign indicating number, and it is connected with described check-node unit by described linkage unit;
Wherein said each check-node unit is used for the calculating of colleague's sub matrix and submatrix mutually, and the number of check-node unit is provided with according to the column weight of its number MATRIX CHECK-UP sign indicating number, and it is connected with described changing cell by described linkage unit;
Wherein said variable node unit comprises a plurality of memory cell again, is used for storing the exchange message between changing cell and the verification unit;
Described linkage unit is used for variable node unit and check-node unit interconnected, and it is that structure by the MATRIX CHECK-UP sign indicating number is determined.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101188912A CN100440737C (en) | 2003-12-04 | 2003-12-04 | High structural LDPC coding and decoding method and coder and decoder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101188912A CN100440737C (en) | 2003-12-04 | 2003-12-04 | High structural LDPC coding and decoding method and coder and decoder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1625057A true CN1625057A (en) | 2005-06-08 |
| CN100440737C CN100440737C (en) | 2008-12-03 |
Family
ID=34761236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101188912A Expired - Fee Related CN100440737C (en) | 2003-12-04 | 2003-12-04 | High structural LDPC coding and decoding method and coder and decoder |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100440737C (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100423454C (en) * | 2006-06-14 | 2008-10-01 | 北京新岸线移动多媒体技术有限公司 | A method and device to realize low density parity check code |
| CN100425017C (en) * | 2005-12-08 | 2008-10-08 | 西安电子科技大学 | Encoder of parallel-convolution LDPC code based on precoding and its fast encoding method |
| CN100499378C (en) * | 2006-05-26 | 2009-06-10 | 清华大学 | Low-density odd-parity check-code decoding method adopting uniform quantizing variable range |
| CN100544212C (en) * | 2006-01-23 | 2009-09-23 | 南京大学 | The loe-density parity-check code decoder of minimizing storage demand at a high speed |
| CN101335596B (en) * | 2006-06-14 | 2011-04-06 | 北京新岸线移动通信技术有限公司 | Low density parity check code implementing apparatus |
| CN101425872B (en) * | 2007-10-30 | 2011-05-04 | 华为技术有限公司 | Power control method, power control device |
| CN101034892B (en) * | 2006-03-06 | 2011-11-23 | 西门子（中国）有限公司 | LDPC code generation method and device using the LDPC code |
| CN101567752B (en) * | 2008-04-23 | 2012-08-08 | 中国科学院微电子研究所 | Self-adaptive encoding/decoding method based on low-density parity-check code |
| CN1983861B (en) * | 2005-06-21 | 2012-09-26 | 三星电子株式会社 | Apparatus and method for transmitting/receiving data in a communication system |
| WO2013004078A1 (en) * | 2011-07-06 | 2013-01-10 | 北京新岸线无线技术有限公司 | Method and device for data transmission |
| CN104488196A (en) * | 2012-11-05 | 2015-04-01 | 三菱电机株式会社 | Error-correction coding method and error-correction coding device |
| CN106209115A (en) * | 2016-06-29 | 2016-12-07 | 联想(北京)有限公司 | A kind of data processing method and electronic equipment |
| CN107241167A (en) * | 2017-06-29 | 2017-10-10 | 东南大学 | A kind of improved method detected based on extensive mimo system BP |
| CN108268338A (en) * | 2016-12-30 | 2018-07-10 | 西部数据技术公司 | Gradually reduce the variable node memory of size |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3704358B2 (en) * | 1996-07-03 | 2005-10-12 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Transmit and receive digital information signals |
| JP2004518350A (en) * | 2001-01-17 | 2004-06-17 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method and apparatus for protecting lossless transmission of a data stream |
| EP1480346A4 (en) * | 2002-02-28 | 2006-05-10 | Mitsubishi Electric Corp | Ldpc code inspection matrix generation method and inspection matrix generation device |
-
2003
- 2003-12-04 CN CNB2003101188912A patent/CN100440737C/en not_active Expired - Fee Related
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1983861B (en) * | 2005-06-21 | 2012-09-26 | 三星电子株式会社 | Apparatus and method for transmitting/receiving data in a communication system |
| CN100425017C (en) * | 2005-12-08 | 2008-10-08 | 西安电子科技大学 | Encoder of parallel-convolution LDPC code based on precoding and its fast encoding method |
| CN100544212C (en) * | 2006-01-23 | 2009-09-23 | 南京大学 | The loe-density parity-check code decoder of minimizing storage demand at a high speed |
| CN101034892B (en) * | 2006-03-06 | 2011-11-23 | 西门子（中国）有限公司 | LDPC code generation method and device using the LDPC code |
| CN100499378C (en) * | 2006-05-26 | 2009-06-10 | 清华大学 | Low-density odd-parity check-code decoding method adopting uniform quantizing variable range |
| CN100423454C (en) * | 2006-06-14 | 2008-10-01 | 北京新岸线移动多媒体技术有限公司 | A method and device to realize low density parity check code |
| CN101335596B (en) * | 2006-06-14 | 2011-04-06 | 北京新岸线移动通信技术有限公司 | Low density parity check code implementing apparatus |
| CN101340262B (en) * | 2006-06-14 | 2012-05-30 | 北京新岸线移动通信技术有限公司 | Implementing method and device for low-density parity check code |
| CN101425872B (en) * | 2007-10-30 | 2011-05-04 | 华为技术有限公司 | Power control method, power control device |
| CN101567752B (en) * | 2008-04-23 | 2012-08-08 | 中国科学院微电子研究所 | Self-adaptive encoding/decoding method based on low-density parity-check code |
| WO2013004078A1 (en) * | 2011-07-06 | 2013-01-10 | 北京新岸线无线技术有限公司 | Method and device for data transmission |
| CN104106230A (en) * | 2011-07-06 | 2014-10-15 | 北京新岸线移动多媒体技术有限公司 | Method and device for transmitting data |
| CN104106230B (en) * | 2011-07-06 | 2017-06-16 | 北京新岸线移动多媒体技术有限公司 | A kind of method and device for data transfer |
| CN104488196A (en) * | 2012-11-05 | 2015-04-01 | 三菱电机株式会社 | Error-correction coding method and error-correction coding device |
| CN104488196B (en) * | 2012-11-05 | 2017-08-01 | 三菱电机株式会社 | Error correction/encoding method and encoder for correcting |
| CN106209115A (en) * | 2016-06-29 | 2016-12-07 | 联想(北京)有限公司 | A kind of data processing method and electronic equipment |
| CN108268338A (en) * | 2016-12-30 | 2018-07-10 | 西部数据技术公司 | Gradually reduce the variable node memory of size |
| CN108268338B (en) * | 2016-12-30 | 2021-03-23 | 西部数据技术公司 | Variable node memory of progressively reduced size |
| CN107241167A (en) * | 2017-06-29 | 2017-10-10 | 东南大学 | A kind of improved method detected based on extensive mimo system BP |
| CN107241167B (en) * | 2017-06-29 | 2020-02-18 | 东南大学 | Improved method based on large-scale MIMO system BP detection |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100440737C (en) | 2008-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101162907B (en) | Method and device for constructing low-density parity code check matrix | |
| CN101453297B (en) | Encoding method and apparatus for low density generation matrix code, and decoding method and apparatus | |
| US20190268025A1 (en) | Coding Method and Coding Device | |
| CN1836394B (en) | Apparatus and method for coding/decoding block ldpc codes in a mobile communication system | |
| CN1625057A (en) | High structural LDPC coding and decoding method and coder and decoder | |
| CN101924565A (en) | LDPC encoder, decoder, system and method | |
| CN100592639C (en) | Low density parity check coding method, device and parity check matrix generating method | |
| CN100425000C (en) | Double-turbine structure low-density odd-even check code decoder | |
| CN101388674B (en) | Decoding method, decoder and Turbo code decoder | |
| CN102394660A (en) | Coding method of block interleaving quasi-cyclic extension parallel coded LDPC (Low Density Parity Check) codes and coder | |
| CN105429646A (en) | Coding and decoding methods of ode of tail-biting staircase codes | |
| CN109391360A (en) | Data-encoding scheme and device | |
| CN101902228A (en) | Rapid cyclic redundancy check encoding method and device | |
| KR100918741B1 (en) | Apparatus and method for channel coding in mobile communication system | |
| KR100669152B1 (en) | Apparatus and method for coding of low density parity check code | |
| CN101286745B (en) | Coding method and device by interleaving | |
| CN101686104A (en) | Coding and decoding method for forward error correction, device and system thereof | |
| CN1973440A (en) | LDPC encoders, decoders, systems and methods | |
| CN102725964B (en) | Encoding method, decoding method, encoding device, and decoding device | |
| CN105391455A (en) | Return-to-zero Turbo code starting point and depth blind identification method | |
| KR20150040244A (en) | transmitting apparatus and signal processing method thereof | |
| KR20150034668A (en) | transmitting apparatus and signal processing method thereof | |
| CN1614898B (en) | Turbo code encoder and encoding method | |
| CN108900463B (en) | APSK constellation mapping-based coding modulation system | |
| CN102611465B (en) | Coder of structured q-ary irregular repeat-accumulate code and coding method of coder |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081203 Termination date: 20131204 |