CN1897277A - Semiconductor device - Google Patents
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- CN1897277A CN1897277A CNA2006100773749A CN200610077374A CN1897277A CN 1897277 A CN1897277 A CN 1897277A CN A2006100773749 A CNA2006100773749 A CN A2006100773749A CN 200610077374 A CN200610077374 A CN 200610077374A CN 1897277 A CN1897277 A CN 1897277A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- Computer Hardware Design (AREA)
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- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provided a semiconductor device. The invention is characterized in that a large scale buffer circuit 65 is constructed by connecting a plurality of CMOS circuits 60 with drain connecting wiring 50. The CMOS circuit 60 is constructed of a pair of pMOS 61 and nMOS 62, common wiring 50-0 is formed on the side further from the nMOS 62 and on the region 501 which does not overlap the drain contact 104 of the pMOS 61, for connecting comb teeth wiring 50-1, ..., 50-2 which interconnect a pair of drain contacts 104 and 204 of the pMOS 61 and nMOS 62. Thereout, it can provide a large scale buffer capable of suppressing the local concentration of an electrostatic surge current and enhancing the electrostatic tolerance.
Description
Technical field
The present invention relates to semiconductor device, particularly have static surge (surge) countermeasure in the semiconductor device of cmos circuit.
Background technology
In semiconductor integrated circuit (below be called semiconductor device), CMOS (complementary metal oxide semiconductors (CMOS)) circuit application is very wide.Cmos circuit is the circuit that pMOS that will be connected with power line VDD side and the nMOS circuit that is connected with earth connection GND side are driven by shared grid current potential, general because grid current potential is at the occasion nMOS of VDD conducting (pMOS by), and the grid current potential is in the occasion pMOS of GND conducting (nMOS ends), so adopt shared line by the leakage that makes pMOS and nMOS, have the current potential opposite with the grid current potential is delivered to secondary inverter function.The logical circuit that is made of CMOS serves as to constitute substantially with the action of this inverter circuit.Below will be called the CMOS logical circuit by the logical circuit that CMOS constitutes.
On the other hand, semiconductor device has by on shallow impurity diffusion zone, clips thin dielectric film and piles up gate electrode and realize high integration, the architectural feature that the static surge that is subjected to invading from the outside easily destroys.Occasion at cmos circuit, when between VDD and GND, applying the static surge, to leakage, the leakage connecting wiring of each leakage of surge current through connecting pMOS and nMOS flows to the leakage of nMOS to surge current from the source and course of the pMOS that is connected with VDD, and surge current flow into earth connection GND again from the source.
In order to protect the CMOS logical circuit not to be subjected to the influence of static surge, general and CMOS logical circuit is arranged in parallel special-purpose protection component.It is represented as leakage is connected to VDD, source, grid and substrate (or trap) is connected to the nMOS protective transistor (being called protection TR) of GND.Protection component has by flow through CMOS logical circuit side at surge current to be made before it is damaged; (for example make predetermined surge current; with be 1.33A as the suitable surge current of the general tolerance guarantee value 2kV in the known HBM of public test method (manikin) test) flow through itself, protection is not subjected to the effect of the infringement of static surge as the CMOS logical circuit of object of protection.In other words, the static tolerance of guaranteeing semiconductor device can only be to suppress the fragility of CMOS logical circuit side, makes protection component side performance protective value.
The CMOS logical circuit is generally said, even small-scale circuit also is made of dozens of or more gate.Constitute the pMOS and the nMOS of CMOS logical circuit, preferably when guaranteeing the necessary current driving ability of circuit working bottom line, get its each size design as much as possible little.Because this point is to suppress circuit area, dwindle chip size and realize that low-cost institute is indispensable.At it on the other hand; the protection component side itself can not be subjected to the destruction of stress in order itself to bear predetermined static surge, in several design sizes of the shape of stipulating TR; for guaranteeing the size of the necessary part of static tolerance, must be bigger than the design size of CMOS logical circuit.One of the representational project of arranging the design object of this static tolerance is the grid and the interval of leaking upper contact.With minimum dimension (for example, the 0.4 μ m) difference of in pMOS that constitutes the CMOS logical circuit and nMOS, using on making, protection component is not used minimum dimension, but use the size (for example, 2.0 μ m) of several times.By the interval of widening grid and leaking upper contact, predetermined tolerance is given in the damage that protection component bears when relaxing the intrusion of static surge.Herein, what should be noted that is CMOS logical circuit side, and any among pMOS and the nMOS all exposes original fragility for the static surge.
The CMOS logical circuit, as previously mentioned, even small-scale circuit also is made of general dozens of or more gate.Although constituting the pMOS and the nMOS of CMOS logical circuit still is set to very fragile; but can not be subjected to the static surge destroys; be to absorb, but the part of the surge current that can not flow through in protection component also flow into the cmos circuit side because of the major part of protection component side with the static surge.Particularly; protection component conducting when applying the static surge and before absorbing enough surge currents during; the surge current that can not flow through in protection component flow into CMOS logical circuit side; be damaged in order not make fragile CMOS logical circuit this moment, importantly circuit scale big, surge current is evenly dispersed on the whole C mos logic circuit.
For example, even each can only tolerate the cmos circuit of the surge current about 1mA, if with 500 such circuit in parallel logical circuit between same VDD and GND, then in the whole C mos logic circuit, can tolerate the surge current of 500 times the 0.5A of 1mA.In this occasion, the protection component side is as long as absorb the surge current of 0.83A, and total can tolerate the electric current of 1.33A, just can guarantee HBM tolerance: 2kV-1.33A.In order to make the CMOS logical circuit not be subjected to the destruction of static surge; the surge absorbability excellence of protection component side; be that the protection component side flows through than the easier static surge that makes of CMOS logical circuit; the scale of CMOS logical circuit side has size to a certain degree, and have make surge current evenly the characteristic of shunting be indispensable.
Yet, in recent years, to improve transistorized current driving ability is purpose, on the impurity diffusion layer of source and leakage, form be called difficulty melt metal silicide (サ イ サ イ De) with compound metal, the transistor arrangement that the dead resistance of source and leakage is descended is popularized rapidly.Melt in the metal silicide technology in this difficulty, in order to ensure the electrostatic breakdown tolerance of protection component, the leakage of protection component is provided with a part and does not form the zone that difficulty is melted metal silicide.Because form on the whole surface in the leakage of protection component when difficulty is melted metal silicide and can not guarantee enough electrostatic breakdown tolerances.But, do not form the zone that difficulty is melted metal silicide, owing to have than forming difficult regional high or the high resistance of multidigit more that melts metal silicide, do not form difficulty to melt the protection component in zone of metal silicide very difficult with surge current introducing itself so be provided with.On the other hand; the CMOS logical circuit; because difficult pMOS and the nMOS that melts metal silicide of formation can improve driving force on whole surface by using, the advantage that can dwindle circuit area is opposite with having, and relatively compares with protection component to be easy to surge current introducing itself.
Therefore, melt the occasion of metal suicide structure technology, compare, must overcome this a pair of disadvantageous essential condition of electrostatic breakdown that prevents that the protection component side is difficult to introduce surge current with existing processes in difficulty.
As one of means of the static surge characteristic of improving the difficult cmos circuit that melts metal suicide structure, a kind of method that increases the grid width of protection component is arranged.Because can make the static surge be easy to flow through the protection component side, so, also can be protected the destruction that is not subjected to the static surge even melt the pMOS of metal silicide and the CMOS logical circuit that nMOS constitutes by forming difficulty by widening grid width.Yet; as mentioned above; the electrostatic breakdown tolerance of CMOS logical circuit not only depends on the absorbability of the static surge of protection component side, and the tolerance that CMOS logical circuit side has a kind of like this weakness of the static surge that can tolerate to a certain degree also is indispensable.This point means, melts in the metal suicide structure technology in difficulty, and the scale of CMOS logical circuit side and the characteristic that surge is evenly shunted are compared more important with existing structure technology.Among these two important elements, as the transistorized number of circuit scale, can great changes have taken place when function is identical.Relative therewith, for uniformity, in certain circuit, change very big sometimes.
The CMOS logical circuit, corresponding to the secondary circuit scale that itself drives, the grid width that changes pMOS and nMOS is guaranteed optimum driving force.The change of grid width uses transistor fabrication with basic size on semiconductor device chip, utilizes wiring layer to constitute the SOG (Sea of Gate, sea of gates) of desired circuit; Prepare the basic circuit of buffer circuits, inverter circuit, NAND circuit etc. in advance, these are combined to form the such circuit formation technology of CB (Cell Base) of desired circuit.In SOG, at secondary circuit scale hour, constitute buffer circuits by driving essential a pair of pMOS that minimal grid width constituted and nMOS, and when the secondary circuit scale is big, in order to ensure essential grid width, constitute buffer circuits by a plurality of pMOS and nMOS.Usually, the size of this buffer circuits is by the integral multiple regulation of the grid width of least unit.On semiconductor device chip, make a pair of pMOS and the nMOS of least unit in advance, constitute logical circuit, adjust circuit operation corresponding to using several among these.Exist sweeping buffer circuits to be subjected to the problem of the destruction of static surge easily than the buffer circuits of small scale herein.
Consider the internal circuit that buffer circuits and prime inverter circuit by smallest size constitute is applied the occasion of static surge below.Suppose that the buffer circuits of smallest size and inverter circuit are that each is made of a CMOS herein.The static surge that is applied on the power line VDD can be by being discharged to the path of earth connection GND and being discharged to earth connection GND from the pMOS of the buffer circuits of smallest size through these two kinds of paths, path that nMOS is discharged to earth connection GND through nMOS from the pMOS of the inverter of prime.Because the grid width of pMOS and nMOS is identical in the buffer circuits of the inverter circuit of prime and smallest size, the surge current that flows through both is identical.Because the inverter circuit and the buffer circuits of this kind smallest size, exist a plurality of in the whole C MOS internal circuit that in semiconductor device, loads, surge current disperses on these inverter circuit groups and buffer circuits group, and the possibility that specific inverter circuit and buffer circuits are damaged is very little.
On the other hand, for example consider the large-scale buffer circuits that constitutes by 16 CMOS logical circuits and the internal circuit that constitutes by the inverter of the prime of smallest size.In the inverter circuit of prime, flow through the surge current equal, and in the buffer circuits that constitutes by 16 CMOS logical circuits, in whole buffer circuits, flow through 16 times surge current with smallest size.
Large-scale buffer circuits, normally a plurality of pMOS and nMOS are connected up by shared grid, both structures of being connected by shared leakage connecting wiring of the leakage of pMOS and nMOS.Leak connecting wiring, usually, in the leakage of pMOS when the arrangement of a plurality of pMOS forms, the arrangement along a plurality of nMOS in the leakage of nMOS forms, and is connected by some ends with the wiring that forms on nMOS in the wiring that forms on the pMOS.In sort buffer device circuit, when the static surge is invaded power line VDD, surge current from the source and course of a plurality of pMOS to leaking, leak connecting wiring, from the leakage current of a plurality of nMOS to source, earth connection GND.As mentioned above, in extensive buffer circuits, with the cmos circuit monomer relatively, what flow through is the surge current of individual several times that constitutes the CMOS of buffer circuits.So, in extensive CMOS logical circuit, reasons such as deviation owing to the characteristic on making, surge current is concentrated when flowing through on specific pMOS or nMOS, just might concentrate the electric current with the proportional size of scale of CMOS logical circuit on specific transistor, transistorized pn has and may be destroyed.
Particularly, nMOS has because thermal runaway is compared with pMOS, and surge current concentrates on the feature of locality leak easily.The surge current that flows into from a plurality of pMOS, owing to concentrate in the leakage arbitrarily among the nMOS that exists with the number identical with pMOS, the pn of nMOS has and may be destroyed.
The concentration of local problem of surge current is in recent years in that to use the difficulty of popularizing rapidly to melt in the transistorized manufacturing process of metal suicide structure influence deep day by day.Difficulty is melted the large scale integrated circuit that metal suicide structure technology is applicable to that also system LSI is such, is impossible construction system LSI but do not use extensive buffer circuits.Change in various functional circuit blocks (block), be configured in the system LSI on the entire chip, in order to make each piece in predetermined timing (timing) switching signal operate as normal, just must be with a synchronizing signal, promptly fundamental clock is supplied with each piece.In order to make this fundamental clock spread all over entire chip, can not lack extensive buffer circuits, therefore for system LSI, the static surge destruction that overcomes extensive buffer circuits is pressing issues.
In patent documentation 1, record the buffer circuits of a nMOS who has a plurality of pMOS and constitute by leakage, grid, the source of extending along the arrangement of these a plurality of pMOS.The grid width of the nMOS that forms is bigger than the grid width of each pMOS.In this buffer circuits, the number of the nMOS of formation is different with the number of pMOS, and a plurality of pMOS are formed the nMOS that grid width is big.The purpose of utilizing this structure is to flow through a big nMOS of grid width at the surge current from a plurality of pMOS, can not occur in the occasion that forms a plurality of nMOS, surge current concentration of local in specific nMOS and make the situation of nMOS deterioration or destruction.
Patent documentation 1: Japanese Patent Application Laid-Open 2002-141416 communique
Summary of the invention
The purpose of buffer circuits of record is to improve the destruction that the concentration of local owing to surge current in nMOS causes in above-mentioned patent documentation 1, original and the same number of nMOS of pMOS are set to have only one and grid width increasing, the problem that exists is to be difficult to be fit to above-mentioned SOG and CB, and circuit working is adjusted difficulty.In addition, even strengthen grid width in a nMOS, deterioration or the destruction of nMOS among the part of concentration of local, might take place in the possible concentration of local of surge current in the wide source of width, leakage.
The present invention can solve the problems referred to above in the semiconductor device.
Semiconductor device according to first invention has: the 1st wiring, the 2nd wiring along above-mentioned the 1st wiring configuration, a plurality of the 1st MOS transistor, a plurality of the 2nd MOS transistor and the 3rd wiring.
The 1MOS transistor, above-mentioned the 1st the wiring and above-mentioned the 2nd the wiring between be configured in above-mentioned the 1st the wiring side, comprise: with above-mentioned the 1st the wiring be connected the 1st contact, the 2nd contact, be configured in the 1st control electrode between above-mentioned the 1st contact and above-mentioned the 2nd contact.
The 2MOS transistor is configured in above-mentioned the 2nd wiring side between above-mentioned the 1st wiring and above-mentioned the 2nd wiring, comprise: the 3rd contact, with the above-mentioned the 2nd connect up the 4th contact be connected, be configured in the 2nd control electrode between above-mentioned the 3rd contact and above-mentioned the 4th contact.
Each 1MOS transistor and Ge Di 2MOS transistor constitute a plurality of cmos circuits in pairs.
The 3rd wiring is to make interconnected the 3rd wiring in above-mentioned a plurality of the 2nd contact and above-mentioned a plurality of the 3rd contact.The 3rd wiring comprises makes the 2nd paired mutually contact and the 3rd contact a plurality of the 4th wirings that connect respectively and a plurality of the 5th wirings that are connected between the 4th wiring.At least one the 5th wiring is to be formed in the 1st zone of above-mentioned the 1st wiring side definition by above-mentioned the 2nd contact.Herein, the 1st zone is by the zone of the 2nd contact towards the 1st wiring side broadening, comprises and the 2nd contact overlapping areas.
Semiconductor device according to second invention has: the 1st wiring, the 2nd wiring along above-mentioned the 1st wiring configuration, a plurality of 1MOS transistor, a plurality of 2MOS transistor and the 3rd wiring.
The 1MOS transistor, above-mentioned the 1st the wiring and above-mentioned the 2nd the wiring between be configured in above-mentioned the 1st the wiring side, comprise: with above-mentioned the 1st the wiring be connected the 1st contact, the 2nd contact, be configured in the 1st control electrode between above-mentioned the 1st contact and the 2nd contact.
The 2MOS transistor is configured in above-mentioned the 2nd wiring side between above-mentioned the 1st wiring and above-mentioned the 2nd wiring, comprise: the 3rd contact, with the above-mentioned the 2nd connect up the 4th contact be connected, be configured in the 2nd control electrode between above-mentioned the 3rd contact and the 4th contact.
Each 1MOS transistor and Ge Di 2MOS transistor constitute a plurality of cmos circuits in pairs.
The 3rd wiring is to make interconnected the 3rd wiring in above-mentioned a plurality of the 2nd contact and above-mentioned a plurality of the 3rd contact.The 3rd wiring comprises: make a plurality of the 4th wirings that the 2nd mutually paired contact and the 3rd contact connect respectively, connect one or more the 5th wirings between the 4th wiring, connect one or more the 6th wirings between the 4th wiring in above-mentioned the 3rd contact side in above-mentioned the 2nd contact side.
Semiconductor device according to the 3rd invention has: the 1st wiring, the 2nd wiring along above-mentioned the 1st wiring configuration, a plurality of 1MOS transistor, a plurality of 2MOS transistor and the 3rd wiring.
The 1MOS transistor, above-mentioned the 1st the wiring and above-mentioned the 2nd the wiring between be configured in above-mentioned the 1st the wiring side, comprise: with above-mentioned the 1st the wiring be connected the 1st contact, the 2nd contact, be configured in the 1st control electrode between above-mentioned the 1st contact and the 2nd contact.
The 2MOS transistor is configured in above-mentioned the 2nd wiring side between above-mentioned the 1st wiring and above-mentioned the 2nd wiring, comprise: the 3rd contact, with the above-mentioned the 2nd connect up the 4th contact be connected, be configured in the 2nd control electrode between above-mentioned the 3rd contact and the 4th contact.
Each 1MOS transistor and Ge Di 2MOS transistor constitute a plurality of cmos circuits in pairs.
The 3rd wiring is to make interconnected the 3rd wiring in above-mentioned a plurality of the 2nd contact and above-mentioned a plurality of the 3rd contact, comprises: make a plurality of the 4th wirings that the 2nd paired mutually contact and the 3rd contact connect respectively, connect a plurality of the 5th of the 3rd adjacent contact of the 3rd paired contact of the 2nd contact and the 2nd contact and connect up.
According to the semiconductor device of first invention, forms in the 1st zone of the 1st wiring side definition by the 2nd contact a plurality of the 4th wirings the interconnected the 5th that connect between a pair of 1MOS transistor and transistorized the 2nd contact of 2MOS and the 3rd contact are connected up.
Apply the occasion of static surge in the 1st wiring, surge current flow into the 2nd contact from transistorized the 1st contact of a plurality of 1MOS, and the 4th wiring through being connected with each the 2nd contact flow into the 3rd paired contact.Thereafter, surge current is discharged to the 2nd from each the 3rd contact through each the 4th contact and connects up.At this moment, on the direction of the 1st contact, the 2nd contact, the 4th wiring, the 3rd contact, the 4th contact, produce electric field.So, flowing through between the 2nd contact that connects with each the 5th wiring for making surge current, surge current must not have this electric current and flow through against the electric field towards the 3rd contact flows from the 2nd contact.
According to this semiconductor device, because can prevent the flowing of surge current between each the 2nd contact, can make surge current from each the 2nd contact to the 3rd paired contact diffluence, so the electric current that is caused by the static surge is evenly disperseed on whole C MOS circuit, can prevent that surge current from specific cmos circuit concentration of local taking place and making cmos circuit deterioration or destruction.In addition, because only utilize the method for attachment between the 2nd contact and the 3rd contact that the static tolerance of semiconductor device is improved, so do not need to change simultaneously manufacturing process.
According to the semiconductor device of second invention, a plurality of the 4th wirings in the 2nd contact that connects each cmos circuit and the 3rd contact when being routed in the 2nd contact side and connecting by the 5th, are also connected in the 3rd contact side by the 6th wiring.
Apply the occasion of static surge in the 1st wiring, surge current flow into the 2nd contact from transistorized the 1st contact of a plurality of 1MOS, and the 4th wiring through being connected with each the 2nd contact flow into the 3rd paired contact.Thereafter, surge current is discharged to the 2nd from each the 3rd contact through each the 4th contact and connects up.At this moment, on the direction of the 1st contact, the 2nd contact, the 4th wiring, the 3rd contact, the 4th contact, produce electric field.In addition, at this moment, surge current might flow into the 3rd specific contact from a plurality of the 2nd contact the 5th wirings and the 6th wiring, but is subjected to following restriction from the surge current of the 3rd specific contact of a plurality of the 2nd contacts inflow.
In other words, in the 2nd contact and the 3rd contact to according to the 6th the wiring, the 5th the wiring, the 6th the wiring the occasion that is linked in sequence, in order to make one-sided 2nd contact of surge current from the 5th wiring, flow to the 3rd contact of the opposition side that clips the 5th wiring, must flow to the 3rd contact of opposition side by the 4th wiring, the 3rd contact, the 6th wiring, the 3rd contact, the 4th wiring, the 2nd contact, the 5th wiring, the 2nd contact, the 4th wiring from the 2nd one-sided contact.On this path, among the part that flows through the 3rd contact, the 4th wiring, the 2nd contact, surge current must not have this electric current and flow through against the electric field towards the 3rd contact flows from the 2nd contact.Its result, electric current is separated mutually between the 3rd contact that clips the 5th wiring, can be suppressed the concentration of local of the surge current of the 3rd contact.
According to this semiconductor device, connect a pair of the 2nd contact and the 3rd contact by utilizing the 4th wiring, make respectively and the 4th be routed in the 2nd contact side and the 3rd contact side connection, can suppress the concentration of local of surge current, can prevent cmos circuit deterioration or destruction.In addition, because only utilize the method for attachment between the 2nd contact and the 3rd contact that the static tolerance of semiconductor device is improved, so do not need to change simultaneously manufacturing process.
In semiconductor device, when utilizing the 4th wiring to connect into a pair of the 2nd contact and the 3rd contact, the 3rd right contact of the 2nd contact and adjacency is connected according to the 3rd invention.
Apply the occasion of static surge in the 1st wiring, surge current flow into the 2nd contact from transistorized the 1st contact of a plurality of 1MOS, and the 4th wiring through being connected with each the 2nd contact flow into the 3rd paired contact.Thereafter, surge current is discharged to the 2nd from each the 3rd contact through each the 4th contact and connects up.At this moment, on the direction of the 1st contact, the 2nd contact, the 4th wiring, the 3rd contact, the 4th contact, produce electric field.In addition, at this moment, surge current might flow into the 3rd specific contact from the 4th wiring and the 5th wiring that connects the 3rd contact, but the 2nd contact beyond these does not have the surge current inflow.
For example, with specific a pair of the 2nd contact and the 3rd contact is benchmark, consideration before two to play one after to till occasion, connect up in the 2nd right contact before the 3rd right contact before the 2nd right contacts before having two, the 5th wiring,, the 4th wiring,, the 5th wiring, the 3rd contact, the 4th wiring, paired the 2nd contact, the 5th wiring, the 3rd right contact, the 4th after, the right such annexation in the 2nd contact afterwards.
In this occasion, the 3rd contact only from utilizing the 2nd right contact before that the 5th wiring connects and utilizing two the 2nd contacts of total of the 2nd paired contact that the 4th wiring is connected to flow into surge current, is not had the surge current inflow from these the 2nd contacts in addition.
In order to make surge current flow into the 3rd contact from two the 2nd right contacts before, surge current must connect up and flow into the 3rd contact through two the 2nd right contacts, the 5th wiring, the 3rd right contact, the 4th wiring, the 2nd right contacts, the 5th before before before.On this path, among the 3rd right contact before, the 4th wiring, the part of the 2nd right contact before one, surge current must not have electric current and flow through against the electric field towards the 3rd contact flows from the 2nd contact in this part.
In addition, in order to make right 2nd contact of surge current after one flow into the 3rd contact, surge current must the 2nd right contact, the 4th wiring, the 3rd right contact, the 5th wiring, paired the 2nd contact, the 4th wiring afterwards after one flow into above-mentioned the 3rd contact.On this path, among the part of the 3rd right contact after, the 5th wiring, paired the 2nd contact, surge current must not have electric current and flow through against the electric field towards the 3rd contact flows from the 2nd contact in this part.
Therefore, the inrush current limitation that flows into the 3rd specific contact is for from utilizing the 2nd right contact before that the 5th wiring connects and utilizing the 4th surge current of two the 2nd contacts of total that connects up the 2nd paired contact that is connected.
According to this semiconductor device, by connecting the 2nd right contact and the 3rd contact of adjacency, can suppress concentration of local to the surge current of the 3rd specific contact, can prevent cmos circuit deterioration or destruction.In addition, because only utilize the method for attachment between the 2nd contact and the 3rd contact that the static tolerance of semiconductor device is improved, so do not need to change simultaneously manufacturing process.
Description of drawings
Figure 1A is the schematic plan view of layout that the semiconductor device 1001 of embodiments of the present invention 1 is shown.
Figure 1B is each regional key diagram of the semiconductor device 1001 of explanation in the plane graph of Figure 1A.
Fig. 1 C is the key diagram in the path of the surge current of the semiconductor device 1001 of explanation in the plane graph of Figure 1A.
Fig. 1 D is used for the leakage connecting wiring 50 of execution mode 1 being described and leaking the key diagram of the position relation of contact 104.
Fig. 1 E be used for illustrating execution mode 1 variation semiconductor device 1001 leakage connecting wiring 50 and leak the key diagram of the position relation of contact 104.
Fig. 2 A is the schematic plan view of layout that the semiconductor device 1002 of embodiments of the present invention 2 is shown.
Fig. 2 B is each regional key diagram of the semiconductor device 1002 of explanation in the plane graph of Fig. 2 A.
Fig. 2 C is the key diagram in the path of the surge current of the semiconductor device 1002 of explanation in the plane graph of Fig. 2 A.
Fig. 3 A is the schematic plan view of layout that the semiconductor device 1003 of embodiments of the present invention 3 is shown.
Fig. 3 B is the schematic plan view of the right structure of each zone, p and nMOS transistor that the semiconductor device 1003 of embodiments of the present invention 3 is shown.
Fig. 3 C is the key diagram in path of surge current that is used for illustrating the semiconductor device 1003 of embodiments of the present invention 3.
Fig. 4 A is the schematic plan view of layout that the semiconductor device 1004 of embodiments of the present invention 4 is shown.
Fig. 4 B is the schematic plan view of the right structure of each zone, p and nMOS transistor that the semiconductor device 1004 of embodiments of the present invention 4 is shown.
Fig. 4 C is the key diagram in path of surge current that is used for illustrating the semiconductor device 1004 of embodiments of the present invention 4.
Description of reference numerals
10 power line connecting wirings
20 earth connection connecting wirings
40 grid connecting wirings
50 leak connecting wiring
The 60CMOS circuit
65 extensive cmos circuits
70p N-type semiconductor N substrate
The 80n trap
The 101pMOS source region
The 102pMOS drain region
Contact, 103pMOS source
104pMOS leaks the contact
105 trap potential fixed areas
106 traps are fixedly used the contact
The 201nMOS source region
The 202nMOS drain region
Contact, 203nMOS source
204nMOS leaks the contact
205 substrate potential fixed areas
206 substrate potentials are fixedly used the contact
401 gate electrodes
402 grid contacts
501pMOS leaks the zone of contact side
502nMOS leaks the zone of contact side
510pMOS, nMOS leak the zone between the contact
Embodiment
(1) execution mode 1
(1-1) structure
Figure 1A is the plane graph of the semiconductor device 1001 of embodiments of the present invention 1.Figure 1B is each regional key diagram of the semiconductor device 1001 of explanation in the plane graph of Figure 1A.Fig. 1 C is for illustrating the key diagram of ESD (static surge) path of current that flows through in the semiconductor device 1001 in the plane graph of Figure 1A.
Shown in Figure 1A, semiconductor device 1001 has a plurality of MOS transistor 61 and the cmos circuit 60 that constitutes of the MOS transistor 62 of n raceway groove and extensive cmos circuit 65 of constituting by a pair of p raceway groove that forms in parallel on p N-type semiconductor N substrate 70.Below the MOS transistor of p raceway groove is called pMOS, the MOS transistor of n raceway groove is called nMOS.
P N-type semiconductor N substrate 70 has: p type impurity range 100 that forms at the n trap 80 that forms on the element formation face, in n trap 80 and trap potential fixed area 105, the n type impurity range 200 and the substrate potential fixed area 205 that form on the element formation face of the p N-type semiconductor N substrate 70 beyond the zone that forms n trap 80.
P type impurity range 100 is the zones that form a plurality of pMOS 61.P type impurity range 100 is to inject p type impurity such as boron, diffusion and the impurity diffusion zone that forms in n trap 80.P type impurity range 100 by a plurality of gate electrodes 401 described later be divided into the source region 101 of pMOS 61 and drain region 102, below the gate electrode 401 forming between source region 101 and the drain region 102 in work the time become the zone of channel layer.Source region 101 and drain region 102 are configured in the both sides of each gate electrode 401, alternately repeat configuration.
On each source region 101, shown in Figure 1B, in power line connecting wiring 10 1 sides formation contact, source 103 (103-1～103-9).On each drain region 102, form to leak contact 104 (104-1～104-8) in earth connection connecting wiring 20 1 sides.
In the present embodiment, in p type impurity range 100, source region 101, the drain region 102 divided by gate electrode 401 from left to right on the paper of Figure 1A alternately repeat to form, and source region 101 adds up to 9 of formation, and drain region 102 adds up to 8 of formation.Each source region 101 and drain region 102 are shared by the drain region 102 or the source region 101 of both sides, form to add up to 16 pMOS transistors.For example, form the drain region 102 of leaking contact 104-1, shared by the source region 101 that forms contact, source 103-1 with the source region 101 that forms contact, source 103-2.The source region 101 of formation source contact 103-2 is by the drain region 102 that forms contact 104-1 Lou with to form the drain region 102 of contact 104-2 Lou shared.The drain region 102 that contact 104-1 is leaked in the source region 101 of formation source contact 103-1 and formation constitutes a pMOS 61.Form the drain region 102 of leaking contact 104-1 and pMOS 61 of the source region that forms contact, source 103-2 101 formations.The drain region 102 that contact 104-2 is leaked in the source region 101 of formation source contact 103-2 and formation constitutes a pMOS 61.So, in p type impurity range 100, be to form by 9 source regions 101 and 8 drain regions 102 to add up to 16 pMOS 61.P type impurity range 100 extends along the direction that a plurality of pMOS 61 arrange.
Trap potential fixed area 105 is to inject n type impurity such as arsenic As, phosphorus P, diffusion with high concentration and the impurity diffusion zone that forms, is to be used for power line connecting wiring 10 is fixed on the zone of the current potential of n trap 80.Trap potential fixed area 105, the direction of extending along p type impurity range 100 forms band shape.In other words, trap potential fixed area 105, the direction of arranging along a plurality of pMOS 61 forms.On trap potential fixed area 105, form a plurality of trap potential fixed contacts 106 along the orientation of pMOS 61.In the present embodiment, the number of trap potential fixed contact 106 forms with contact, source 103, leaks the number of number same degree of the total of contact 104 and gate electrode 401, gets final product so long as be enough to be used for power line connecting wiring 10 is fixed on the number of trap potential.
N type impurity range 200 is the zones that form a plurality of nMOS 62.N type impurity range 200 is to inject n type impurity such as arsenic As, phosphorus P, diffusion on the element formation face of p N-type semiconductor N substrate 70 in the zone beyond n trap 80 and the impurity diffusion zone that forms.N type impurity range 200, by a plurality of gate electrodes 401 be divided into the transistorized source region 201 of nMOS and drain region 202, below the gate electrode 401 forming between source region 201 and the drain region 202 in work the time become the zone of channel layer.Source region 201 and drain region 202 are configured in the both sides of each gate electrode 401, alternately repeat configuration.
On each source region 201, shown in Figure 1B, in earth connection connecting wiring 20 1 sides formation contact, source 203 (203-1～203-2).On each drain region 202, form to leak contact 204 (204-1～204-2) in power line connecting wiring 10 1 sides.
In the present embodiment, in n type impurity range 200, source region 201, the drain region 202 divided by gate electrode 401 from left to right on the paper of Figure 1A alternately repeat to form, and source region 201 adds up to 9 of formation, and drain region 202 adds up to 8 of formation.Each source region 201 and drain region 202 are shared by the drain region 202 or the source region 201 of both sides, form to add up to 16 nMOS transistors.
From left to right, establish each contact, source 203 and be 203-1～203-9 on the paper of Figure 1A, each leaks contact 204 and is 204-1～204-8.For example, form the drain region 202 of leaking contact 204-1, shared by the source region 201 that forms contact, source 203-1 with the source region 201 that forms contact, source 203-2.The source region 201 of formation source contact 203-2 is by the drain region 202 that forms contact 204-1 Lou with to form the drain region 202 of contact 204-2 Lou shared.The drain region 202 that contact 204-1 is leaked in the source region 201 of formation source contact 203-1 and formation constitutes a pMOS 61.Form the drain region 202 of leaking contact 204-1 and pMOS 61 of the source region that forms contact, source 203-2 201 formations.The drain region 202 that contact 204-2 is leaked in the source region 201 of formation source contact 203-2 and formation constitutes a pMOS61.So, in n type impurity range 200, be to form by 9 source regions 201 and 8 drain regions 202 to add up to 16 nMOS 62.N type impurity range 200 extends along the direction that a plurality of nMOS 62 arrange.
Substrate potential fixed area 205 is zones of injecting p type impurity such as boron with high concentration, is to be used for earth connection connecting wiring 20 is fixed on the zone of the current potential (substrate potential) of p N-type semiconductor N substrate 70.Substrate potential fixed area 205, the direction of extending along n type impurity range 200 forms band shape.In other words, substrate potential fixed area 205, the direction of arranging along a plurality of nMOS 62 forms.On substrate potential fixed area 205, form a plurality of substrate potential fixed contacts 206 along the orientation of nMOS 62.In the present embodiment, the number of substrate potential fixed contact 206 forms with contact, source 203, leaks the number of number same degree of the total of contact 204 and gate electrode 401, gets final product so long as be enough to be used for earth connection connecting wiring 20 is fixed on the number of substrate potential.
Shown in Figure 1B, be zone 501, zone 510 and zone 502 with the area dividing of the semiconductor device 1001 of present embodiment.
In the present embodiment, in p type impurity range 100, form 16 pMOS 61, form 16 nMOS 62 in n type impurity range 200, a pair of pMOS 61 and nMOS 62 constitute 60,16 cmos circuits 60 of cmos circuit and constitute extensive cmos circuit 65 by leaking connecting wiring 50 connections.Extensive cmos circuit 65 for example, constitutes the buffer circuits in the back level that is configured in not shown inverter circuit.In fact, the semiconductor device 1001 of present embodiment has inverter circuit and other a plurality of cmos circuits and the esd protection circuit in the prime that is configured in buffer circuits.
On p type impurity range 100 and n type impurity range 200, in p type impurity range 100 and n type impurity range 200 scopes, forming a plurality of gate electrodes 401 on p type impurity range 100 and n type impurity range 200 bearing of trends across.Be to form 16 gate electrodes 401 in the present embodiment.Gate electrode 401 is to clip not shown gate insulating film to form on p N-type semiconductor N substrate 70.In addition, in the present embodiment, gate electrode 401 is integrally formed to pMOS 61 and nMOS 62 common lands, but also can be to make gate electrode for for example, constitutes the 2nd gate electrode of the 1st gate electrode of pMOS 61 and nMOS 62 respectively and structure that the 1st and the 2nd gate electrode is electrically connected.
On the element formation face of p N-type semiconductor N substrate 70, form the 1st not shown interlayer dielectric.The 1st interlayer dielectric covers p type impurity range 100, n type impurity range 200, trap potential fixed area 105, substrate potential fixed area 205 and gate electrode 401.
On the 1st interlayer dielectric, form the 1st layer of metal wiring layer.The 1st layer of metal wiring layer comprises power line connecting wiring 10, earth connection connecting wiring 20, grid connecting wiring 40 and leaks connecting wiring 50.The 1st layer of metal wiring layer is made of wiring multilayer film of aluminium Al, aluminium Al and titanium nitride TiN etc.
Power line connecting wiring 10 is the wirings that apply supply voltage VDD when semiconductor device 1001 work.Apply supply voltage VDD when semiconductor device 1001 work on trap potential fixed area 105, power line connecting wiring 10 is fixed as supply voltage VDD from trap potential fixed area 105 through a plurality of contacts 106.Power line connecting wiring 10 has along the bearing of trend of trap potential fixed area 105 in a plurality of broach wirings that clip the film formed shared wiring of the 1st layer insulation above the trap potential fixed area 105 and extend respectively above a plurality of source regions 101 of pMOS 61 from shared wiring.Shared wiring is electrically connected with trap potential fixed area 105 by a plurality of trap potential fixed contacts 106.Trap potential fixed contact 106 forms in the contact hole that forms on the 1st interlayer dielectric.Each exterior region of a plurality of broach wirings clips the 1st interlayer dielectric and forms above each source region 101.Each exterior region of a plurality of broach wiring extends to trap potential fixed area 105 sides in source region 101 always, in other words, and promptly apart from 101 ends, source region of nMOS 62 side far away.The exterior region of each broach wiring is by contact, source 103 (103-1～103-9) be electrically connected with each source region 101.Contact, source 103 (forms in the contact hole of 103-1～103-9) form on the 1st interlayer dielectric.
Earth connection connecting wiring 20 is the wirings that apply earthing potential GND when semiconductor device 1001 work.Apply earthing potential GND when semiconductor device 1001 work on substrate potential fixed area 205, earth connection connecting wiring 20 is fixed as earthing potential GND from substrate potential fixed area 205 through a plurality of substrate potential fixed contacts 206.Earth connection connecting wiring 20 has along the bearing of trend of substrate potential fixed area 205 in a plurality of broach wirings that clip the film formed shared wiring of the 1st layer insulation above the substrate potential fixed area 205 and extend respectively above a plurality of source regions 201 of nMOS 62 from shared wiring.Shared wiring is electrically connected with substrate potential fixed area 205 by a plurality of substrate potential fixed contacts 206.Substrate potential fixed contact 206 forms in the contact hole that forms on the 1st interlayer dielectric.Each exterior region of a plurality of broach wirings clips the 1st interlayer dielectric and forms above each source region 201.Each exterior region of a plurality of broach wiring extends to substrate potential fixed area 205 sides in source region 201 always, in other words, and promptly apart from 201 ends, source region of pMOS 61 side far away.The exterior region of each broach wiring is by contact, source 203 (203-1～203-9) be electrically connected with each source region 201.Contact, source 203 (forms in the contact hole of 203-1～203-9) form on the 1st interlayer dielectric.
Leak connecting wiring 50, shown in Fig. 1 C, have: be transverse on the p type impurity range 100 a plurality of broach wiring 50-1～50-8 that extend in shared wiring 50-0 that the top of a plurality of gate electrodes 401 that form forms and a plurality of drain regions 202 from shared wiring 50-0 towards n type impurity range 200 on the 1st interlayer dielectric.Each broach wiring 50-1～50-8 extends to the zone of pMOS 61 sides in the drain region 202 of nMOS 62 always.Leak the efferent that connecting wiring 50 is configured to the voltage from each cmos circuit 60 output is outputed to the circuit of back level.
Each broach wiring 50-1～50-8, (204-1～204-8) passes through leakage contact 104 (104-1～104-8) be electrically connected with the drain region 102 of pMOS 61 with when each drain region 202 of nMOS 62 is electrically connected at root by leaking contact 204 in exterior region.Leak in contact 104 and 204 contact holes that in the 1st interlayer dielectric, form and form.
Below the exterior region of each broach wiring 50-1～50-8, promptly the below of earth connection connecting wiring 20 sides of the exterior region of each broach wiring 50-1～50-8 forms a plurality of contact holes that lead to each drain region 202 in the 1st interlayer dielectric.By the leakage contact 204 that forms in each contact hole, the exterior region of each broach wiring 50-1～50-8 is electrically connected with corresponding drain region 202.
Below the root of each broach wiring 50-1～50-8, promptly the below of power line connecting wiring 10 sides of each broach wiring 50-1～50-8 forms the contact hole that leads to each drain region 102 in the 1st interlayer dielectric.Leakage contact 104 by in each contact hole, forming (104-1～104-8), the exterior region of each broach wiring 50-1～50-8 and corresponding drain region 102 electrical connections.
In other words, each broach wiring 50-1～50-8 makes between the leakage contact 104,204 of a pair of pMOS and nMOS and is electrically connected respectively.
Shared wiring 50-0 is configured in the zone 501, and (the 1st wiring 10 sides of 104-1～104-8) and each broach 50-1～50-8 that connects up is connected in the leakage contact 104 of pMOS 61.In other words, leak connecting wiring 50, when the leakage contact 204 of leakage contact 104 that makes each pMOS 61 by each broach wiring 50-1～50-8 and nMOS 62 is connected one to one, in the zone 501 in the outside of the leakage contact 104 of pMOS 61, each broach wiring 50-1～50-8 is connected to each other by shared wiring 50-0.Can think that shared wiring 50-0 is 7 wirings that connect between each broach wiring 50-1～50-8,7 wirings are from nMOS 62 side far away and do not forming with leaking in 104 overlapping areas of contact.
Therefore, flow into and respectively leak contact 104 (surge current of 104-1～104-8) is not a concentration of local (among 204-1～204-8) some, but leaks contact 204 (204-1～204-8) be distributed on each nMOS 62 in specific leakage contact 204 through each.
This is because of the occasion that flows into power line connecting wiring 10 at surge current, generates from each and leaks the electric field of contact 104-1～104-8 towards paired leakage contact 204-1～204-8.In other words, in leaking connecting wiring 50, produce electric field, produce electric field in this wise towards leaking contact 204-2 towards leaking contact 204-1 from leaking contact 104-1, in leaking connecting wiring 50, leak contact 104 and 204 produce electric fields towards paired leakage contact from each from leaking contact 104-2.In this case, make surge current flow to the leakage contact 104 of adjacency through shared wiring 50-0 from specific leakage contact 104, electric current must flow against direction of an electric field, does not have surge current to flow through through shared wiring 50-0 between leakage contact 104-1～104-8.
For example, make surge current flow to Lou contact 204-2 through leaking contact 104-2 from leaking contact 104-1, will be against the electric field that in broach wiring 50-1, produces from leakage contact 104-1 towards leakage contact 204-1, so do not have surge current to flow through from leaking contact 104-1 to leaking contact 104-2, do not have surge current to flow through to leaking contact 204-2 from leaking contact 104-1.
Therefore, flow into the surge current that respectively leaks contact 104-1～104-8 and necessarily flow into paired leakage contact 204-1～204-8.In other words, the surge current that flow into each pMOS 61 necessarily flow into paired nMOS 62.Its result can prevent that the surge current that flow into each pMOS 61 from concentration of local occurring in specific nMOS 62, and surge current is distributed to 62 couples of each pMOS61 and nMOS.
(1-2) action effect
When semiconductor device 1001 work, leakage connecting wiring 50 in the extensive cmos circuit that is made of 16 cmos circuits 60 is connected with the leakage of the inverter circuit of prime, is input to each cmos circuit 60 from the output signal of the leakage of inverter circuit through leaking connecting wiring 50.Each cmos circuit 60 of the output signal of input inverter circuit is corresponding to the logic of the output signal of inverter circuit, to the output signal of leaking connecting wiring 50 output High (height) or Low (low).
This semiconductor device 1001, when transporting or the like among, power line connecting wiring 10, earth connection connecting wiring 20 open circuits, the circuit that is included in the semiconductor device 1001 becomes electric quick condition.Under this state, for example, when applying the static surge of positive polarity on power line connecting wiring 10, (103-1～103-9) flow into and respectively leaks contact 104 (104-1～104-8) surge current from the contact, source 103 of pMOS 61.Flow into the surge current that respectively leaks contact 104-1～104-8 of pMOS 61, shown in Fig. 1 C, flow into paired leakage contact 204-1～204-8 by each the broach wiring 50-1～50-8 that leaks connecting wiring 50 respectively.In other words, surge current flows through between paired pMOS 61 and nMOS 62 by each broach wiring 50-1～50-8.Thereafter, surge current, flow into contact, source 203-1～203-9 from the contact 204-1～204-8 that respectively leaks of nMOS 62, be discharged to p N-type semiconductor N substrate 70 through earth connection connecting wiring 20, a plurality of substrate potential fixed contact 206, substrate potential fixed area 205 from contact, source 203-1～203-9.
Flow into the occasion of power line connecting wiring 10 at the surge current of positive polarity, produce electric fields from the leakage contact 204 of the leakage contact 104 towards nMOS 62 of pMOS 61, in leaking each broach wiring 50-1～50-8 of connecting wiring 50, produce and respectively leak the electric field that respectively leak contact 204-1～204-8 of contact 104-1～104-8 towards paired nMOS 62 from pMOS 61.Leak each broach wiring 50-1～50-8 of connecting wiring 50, owing in the zone 501 in the outside of the leakage contact of pMOS 61 104-1～104-8, be connected to each other with shared wiring 50-0, make surge current leak broach wiring 50-1～50-8 that contact 104-1～104-8 flow into the leakage contact 104 of adjacency from each, surge current must flow against the connect up electric field of 50-1～50-8 of broach, does not have this surge current and flows through.In other words, leaking respectively the leaking in the path between the 104-1～104-8 of contact of connecting wiring 50, owing to become the direction against electric field, leak between the 104-1～104-8 of contact does not have surge current to flow through at each.Its result, surge current only between paired leakage contact 101-1201-1 ..., flow among the 101-8201-8.
Like this, flow into the surge current in the power line connecting wiring 10,, flow to paired nMOS 62 from each pMOS 61 by flowing into each pMOS 61, surge current just can be in specific nMOS 62 concentration of local, but be distributed to each cmos circuit 60.Thus, flow into the occasion of semiconductor device 1001 at surge current, can make each cmos circuit 60 that constitutes extensive cmos circuit 65 have relatively poor surge current tolerance, can prevent surge current concentration of local and make cmos circuit 60 deteriorations or be damaged in specific nMOS 62.
According to this present embodiment, even in semiconductor device, load large-scale cmos circuit, each cmos circuit that constitutes extensive cmos circuit also can keep least unit or with the easy fluidity of the equal static surge of the cmos circuit of smallest size, and prevent because the concentration of local of surge current causes deterioration or damages.Thus, can utilize a plurality of inverter circuit groups and the buffer circuit bank that in semiconductor device, exist to keep the effect of guaranteeing static surge tolerance.Particularly; adopting difficult melting in the semiconductor device of metal suicide structure; in the source region of the cmos circuit that constitutes internal circuit and drain region, form difficulty and melt metal silicide; but do not form difficulty sometimes in the source region of esd protection element and drain region and melt metal silicide, present embodiment is effective in this occasion for the concentration of local that prevents surge current.
In the present embodiment, because in existing C MOS manufacturing process, only change the method for attachment of leaking connecting wiring 50, so the manufacturing process that does not need to change CMOS simultaneously just can implement.In addition, because can use the wiring join domain of preparing in original cmos circuit, do not worry that the area of cmos circuit increases.If, even connecting wiring increases the zone in order to draw Lou, because just by a thin shared wiring 50-0, the influence that area increases is slight.
(1-3) variation
(A) Fig. 1 D is the leakage contact 104 that is used for describing in detail the semiconductor device 1001 of embodiments of the present invention 1 (104-1～104-8) and the key diagram of the position in zone 501 relation.In the figure, for convenience of description, shared wiring 50-0 is omitted.
Fig. 1 E be used for illustrating embodiments of the present invention 1 variation semiconductor device 1001 leakage connecting wiring 50 and leak the key diagram of the position relation of contact 104.
Shown in Fig. 1 D (a), in semiconductor device 1001, zone 501 is the zones from the 104a-1～104a-8 of edge portion of nMOS 62 sides of leakage contact 104-1～104-8 of pMOS61 towards power line connecting wiring 10 side broadenings.Herein, the boundary line of the 104a-1～104a-8 of edge portion of supposing connect to leak nMOS 62 sides of contact 104-1～104-8 is 5011, for the surge current that prevents to flow into contact 104-1～104-8 Lou flows into the leakage contact of adjacency through shared wiring 50-0, the 50a-0 of edge portion of nMOS 62 sides that must make shared wiring 50-0 is on boundary line 5011 or forming near power line connecting wiring 10 sides than boundary line 5011.
Fig. 1 D (b) for the 50a-0 of edge portion that the shared wiring of hypothesis 50-0 is shown the occasion that forms than boundary line 5011 more close nMOS 62 sides, leak connecting wiring 50 and leak the diagrammatic sketch of the relation of contact 104-1～104-8.As shown in the drawing, shared wiring 50-0 has than the zone of leaking more close nMOS 62 sides of contact 104-1～104-8.In this zone, for example, because produce from leaking contact 104-1 towards the electric field that leaks contact 204-1 and 204-2, surge current may flow to any of leaking contact 204-1 and the 204-2 from leaking contact 104-1.Comparing and be connected to the occasion that the nMOS 62 of contact 204-2 Lou relatively easily makes electric current flow with being connected to the nMOS 62 of contact 204-1 Lou, surge current will flow into Lou contact 204-2 from leaking contact 104-1.In this occasion, surge current also might be except paired leakage contact 104-1～104-8 flow into through shared wiring 50-0 and respectively leaks contact 204-1～204-8, surge current might be in some leakages contact 204-1～204-8 concentration of local and make the pn knot deterioration of nMOS 62 or destroyed.
In a variation of execution mode 1, shown in Fig. 1 E (a), make the 50a-0 of edge portion of shared wiring 50-0 consistent with boundary line 5011.In other words, make the 104a-1～104a-8 of edge portion of the 50a-0 of edge portion of shared wiring 50-0 of connecting wiring 50 Lou and leakage contact 104-1～104-8 consistent, in pMOS 61 sides, promptly power line connecting wiring 10 sides form shared wiring 50-0 from the 104a-1～104a-8 of edge portion.
In another variation of execution mode 1, shown in Fig. 1 E (b), the 50a-0 of edge portion of shared wiring 50-0 is configured as more overlapping with leakage contact 104-1～104-8 than boundary line 5011 more close power line connecting wiring 10 sides.In other words, the 50a-0 of edge portion with shared wiring 50-0 is configured in than more close power line connecting wiring 10 sides of the 104a-1～104a-8 of edge portion of leaking contact 104-1～104-8.
Constitute to leak in the semiconductor device 1001 of connecting wiring 50 shown in (b) as Fig. 1 E (a), flow into the Lou surge current of contact 104-1～104-8, along leak the electric field of contact 104-1～104-8 from each, only do not leak between the 104-1～104-8 of contact and flow through shared wiring 50 at each flowing between the paired leakage contact towards 204-1～204-8.Its reason is because shared wiring 50 has than the zone of leaking the more close leakage of contact 104-1～104-8 contact 204-1～204-8 side, surge current is flowed respectively leaking between the 104-1～104-8 of contact of shared wiring 50, must not have this surge current and flow through against flowing from the electric field that leaks contact 104 towards 204.
For example, leaking between contact 104-1 and the 204-1, producing, flowing towards 104-2 from leaking contact 104-1, surge current is flowed against this electric field, do not having this surge current and flow through in order to make surge current from leaking the electric field of contact 104-1 towards 204-1.
(B) in above-mentioned, what describe for example is the occasion of surge current concentration of local in specific nMOS 62, when the leakage contact of nMOS 62 204 sides are configured in the zone 502, can suppress the concentration of local of surge current among specific pMOS 61 at the shared wiring 50-0 that will leak connecting wiring 50 from earth connection connecting wiring 20 side inflows.
(C) in above-mentioned, be that shared wiring 50-0 only is configured in pMOS 61 sides, with shared wiring 50-0 the leakage contact of nMOS 62 204 sides also be configured in the zone 502 in the time, among nMOS 62, in the concentration of local, can also suppress the concentration of local of surge current among pMOS 61 at the surge current that can suppress from earth connection connecting wiring 20 side inflows from power line connecting wiring 10 side inflows.In the occasion that shared wiring 50-0 is configured in pMOS and nMOS both sides, preferably in different wiring layers, form grid connecting wiring 40 and leak connecting wiring 50, perhaps form broach wiring 50-1～50-8 by the 1st layer of metal wiring layer, form shared wiring 50-0 and grid connecting wiring 40 by the 2nd layer of metal wiring layer, perhaps form broach wiring 50-1～50-8 and grid connecting wiring 40, form shared wiring 50-0 by the 2nd layer of metal wiring layer by the 1st layer of metal wiring layer.
(D) in the occasion of surge current concentration of local in nMOS 62, shared wiring 50-0 is configured in the zone 501 of pMOS 61 sides, in the occasion of surge current concentration of local in pMOS 61, also shared wiring 50-0 can be configured in the zone 502 of nMOS 62 sides.
(E) in above-mentioned, be on the 1st interlayer dielectric, to form the Lou shared wiring 50-0 and the broach wiring 50-1～50-8 of connecting wiring 50 by the 1st layer of metal wiring layer, but also can form broach wiring 50-1～50-8 by the 1st layer of metal wiring layer, by than the 1st layer of metal wiring layer more the 2nd wiring layer etc. on upper strata form shared wiring 50-0.For example, in the occasion that forms shared wiring 50-0 by the 2nd layer of metal wiring layer, also can on the 2nd interlayer dielectric that covers the 1st layer of metal wiring layer, form shared wiring 50-0, shared wiring 50-0 and broach wiring 50-1～50-8 are electrically connected by the contact that connects the 2nd interlayer dielectric as the 2nd layer of metal wiring layer.Like this, in the occasion that forms shared wiring 50-0,, can increase the degree of freedom of the layout of grid connecting wiring 40 because shared wiring 50-0 is configured in the layer different with grid connecting wiring 40.
(F) in above-mentioned, be on the 1st interlayer dielectric, to form Lou connecting wiring 50 and grid connecting wiring 40 by the 1st layer of metal wiring layer, but also can form Lou connecting wiring 50 by the 1st layer of metal wiring layer, by than the 1st layer of metal wiring layer more the 2nd wiring layer etc. on upper strata form grid connecting wiring 40.For example, in the occasion that forms grid connecting wiring 40 by the 2nd layer of metal wiring layer, also can on the 2nd interlayer dielectric that covers the 1st layer of metal wiring layer, form grid connecting wiring 40, be electrically connected by the 402 pairs of grid connecting wirings 40 in grid contact and the gate electrode 401 that connect the 1st and the 2nd interlayer dielectric as the 2nd layer of metal wiring layer.Like this, in the occasion that forms grid connecting wiring 40 because grid connecting wiring 40 be configured in leak connecting wiring 50 different layer in, can increase the degree of freedom of the layout of grid connecting wiring 40.
(2) execution mode 2
(2-1) structure
Fig. 2 A is the plane graph of the semiconductor device 1002 of embodiments of the present invention 2.Fig. 2 B is each regional key diagram of the semiconductor device 1002 of explanation in the plane graph of Fig. 2 A.Fig. 2 C is for illustrating the key diagram of the ESD path of current that flows through in the semiconductor device 1002 in the plane graph of Fig. 2 A.
The semiconductor device 1002 of present embodiment is compared with the semiconductor device 1001 of execution mode 1, leaks the structure difference of connecting wiring 50, and other structures are the same.In the present embodiment, for giving same symbol, then omit with the explanation that execution mode 1 repeats with the structure of the corresponding present embodiment of structure of execution mode 1.
In the present embodiment, connect the shared wiring of each the broach wiring 50-1～50-8 that leaks connecting wiring 50, shown in Fig. 2 C, have 50-A that in zone 501, forms and the 50-B that in zone 510, forms.In other words, shared wiring, when a plurality of shared wiring portion of considering to connect respectively between broach wiring 50-1～50-8, at least one is shared wiring 50-A in a plurality of shared wiring portion.
Shown in Fig. 2 B, leak connecting wiring 50 and have: connect into broach wiring 50-1～50-8 of right leakage contact 104-1～104-8 and leakage contact 204-1～204-8 respectively and make the interconnected shared wiring 50-A of broach wiring 50-1～50-8,50-B.
Shared wiring 50-A is connected to each other broach wiring 50-4 and 50-5.Shared wiring 50-A forms in zone 501, more detailed speech it, be in distance nMOS 62 side far away and do not forming with leaking in contact 104-4 and the 104-5 overlapping areas.
Shared wiring 50-B makes the broach wiring interconnected while of 50-1～50-4, and broach wiring 50-5～50-8 is connected to each other.Shared wiring 50-B forms in zone 510, is forming than more close nMOS 62 sides of leakage contact 104-1～104-4 of pMOS 61.
(2-2) action effect
Flow into the surge current that respectively leaks contact 104-1～104-4, respectively leak contact 204-1～204-4 by what each broach wiring 50-1～50-4 that leaks connecting wiring 50 flow into nMOS 62.In addition, flow into the surge current that respectively leaks contact 104-5～104-8, each the broach wiring 50-5～50-8 through leaking connecting wiring 50 flow into the transistorized contact 204-5～204-8 that respectively leaks of nMOS.
Herein, because broach wiring 50-4 is being connected by shared wiring 50-A than leaking contact 104-4 and more close power line connecting wiring 10 sides of 104-5 with 50-5, surge current is flowed between leakage contact 104-4 side and 104-5 side by shared wiring 50-A, must flow against electric field respectively, not have this surge current and flow through from leakage contact 104-4 towards 204-4, from 104-5 towards 204-5.Its result, can not flow into mutually with 104-5 side surge current and separates leaking contact 104-4 side as benchmark with shared wiring 50-A.In the present embodiment, shared wiring 50-A is set to one and the surge current that will flow into each broach wiring 50-1～50-8 is separated into two zones, and is set to can be separated into more zone when a plurality of in the shared number that connects up 50-A.
Broach wiring 50-1～50-4, owing to be connected by shared wiring 50-B than leaking more close nMOS 62 sides of contact 104-1～104-4, surge current might flow into specific leakage contact 204-1～204-4 concentration of local from leaking contact 104-1～104-4.In addition, broach wiring 50-5～50-8, owing to utilizing shared wiring 50-B to be connected than leaking more close nMOS 62 sides of contact 104-5～104-8, surge current might flow into specific leakage contact 204-5～204-8 concentration of local from leaking contact 104-5～104-8.But, separate in the both sides of shared wiring 50-A owing to flow into the surge current of contact 104-1～104-8, be to come half the surge current of natural leak contact 104-1～104-8 so flow into a surge current maximum constraints in the leakage contact 204 with Louing.So, be configured in than leaking contact 104 by utilization apart from the nMOS 62 shared wiring 50-A in distally more, with the both sides of the shared 50-A that connects up respectively leak current separation between the contact 104, can suppress the concentration of local of the surge current among the nMOS 62.
(2-3) variation
(A) in the present embodiment, for shared wiring 50-B, this distortion shown in Fig. 1 E (a) reaches (b) also is possible.
(B) in addition, in the present embodiment, what describe for example also is the occasion of surge current concentration of local in specific nMOS 62, in the occasion of surge current concentration of local in specific pMOS 61, shared wiring 50-A, the 50-B that leaks connecting wiring 50 can be configured in leakage contact 204 sides of nMOS 62.
(C) in above-mentioned, be that shared wiring 50-A, 50-B only are configured in pMOS 61 sides, but when the leakage contact of nMOS 62 204 sides also dispose shared wiring 50-A, 50-B, among nMOS 62, in the concentration of local, can also suppress the concentration of local of surge current among pMOS 61 at the surge current that can suppress from earth connection connecting wiring 20 side inflows from power line connecting wiring 10 side inflows.In the occasion that shared wiring 50-A, 50-B is configured in pMOS and nMOS both sides, preferably in different wiring layers, form grid connecting wiring 40 and leak connecting wiring 50, perhaps form broach wiring 50-1～50-8 by the 1st layer of metal wiring layer, form shared wiring 50-A, 50-B and grid connecting wiring 40 by the 2nd layer of metal wiring layer, perhaps form broach wiring 50-1～50-8 and grid connecting wiring 40, form shared wiring 50-A, 50-B by the 2nd layer of metal wiring layer by the 1st layer of metal wiring layer.
(D) in the occasion of surge current concentration of local in nMOS 62, shared wiring 50-A, 50-B are configured in pMOS 61 sides,, also shared wiring 50-A, 50-B can be configured in nMOS 62 sides in the occasion of surge current concentration of local in pMOS 61.
(E) in addition, in above-mentioned, leakage contact 104-4 in substantial middle portion among the 104-1～104-8 of the leakage contact of pMOS 61 is connected by shared wiring 50-A in zone 501 with 104-5, but also can be connected by shared wiring 50-A in zone 501 by at least two leakage contact 104-1～104-8 in other leakage contact 104-1～104-8.
For example, when leaking contact 104-2 and 104-3 is connected by shared wiring 50-A, also can connect 104-5 and 104-6 by shared wiring 50-A.Like this, when using a plurality of shared wiring 50-A to connect leakage contact 104, because be separated, so can more effectively suppress the concentration of local of surge current at both sides surge current of each shared wiring 50-A.In the occasion of this example, can utilize the shared wiring 50-A of two positions that surge current is separated to 3 positions reliably.
(F) in addition, also can in zone 501, connect more than equaling 3 and leak the contact by shared wiring 50-A, for example, 104-3,104-4,104-5.At this moment, can separate surge current in the both sides of shared wiring 50-A.
(G) in above-mentioned, be on the 1st interlayer dielectric, to form Lou shared wiring 50-A and the 50-B and the broach wiring 50-1～50-8 of connecting wiring 50 by the 1st layer of metal wiring layer, but also can form broach wiring 50-1～50-8 by the 1st layer of metal wiring layer, by than the 1st layer of metal wiring layer more the 2nd wiring layer etc. on upper strata form shared wiring 50-A and 50-B.For example, in the occasion that forms shared wiring 50-A and 50-B by the 2nd layer of metal wiring layer, can cover shared wiring 50-A and the 50-B that forms on the 2nd interlayer dielectric of the 1st layer of metal wiring layer as the 2nd layer of metal wiring layer, shared wiring 50-A and 50-B and the broach 50-1～50-8 that connects up is being electrically connected by the contact that on the 2nd interlayer dielectric, forms.Like this, in the occasion that forms shared wiring 50-A and 50-B,, can increase the degree of freedom of the layout of grid connecting wiring 40 because shared wiring 50-A and 50-B are configured in the layer different with grid connecting wiring 40.In addition, also can only form at least one or the part of shared wiring 50-A and 50-B by the 2nd layer of metal wiring layer.
(H) in above-mentioned, be on the 1st interlayer dielectric, to form Lou connecting wiring 50 and grid connecting wiring 40 by the 1st layer of metal wiring layer, but also can form Lou connecting wiring 50 by the 1st layer of metal wiring layer, by than the 1st layer of metal wiring layer more the 2nd wiring layer etc. on upper strata form grid connecting wiring 40.For example, in the occasion that forms grid connecting wiring 40 by the 2nd layer of metal wiring layer, also can on the 2nd interlayer dielectric that covers the 1st layer of metal wiring layer, form grid connecting wiring 40, be electrically connected by the 402 pairs of grid connecting wirings 40 in grid contact and the gate electrode 401 that connect the 1st and the 2nd interlayer dielectric as the 2nd layer of metal wiring layer.Like this, in the occasion that forms grid connecting wiring 40 because grid connecting wiring 40 be configured in leak connecting wiring 50 different layer in, can increase the degree of freedom of the layout of grid connecting wiring 40.
(3) execution mode 3
(3-1) structure
Fig. 3 A is the plane graph of the semiconductor device 1003 of embodiments of the present invention 3.Fig. 3 B is each regional key diagram of the semiconductor device 1003 of explanation in the plane graph of Fig. 3 A.Fig. 3 C is for illustrating the key diagram of the ESD path of current that flows through in the semiconductor device 1003 in the plane graph of Fig. 3 A.
The semiconductor device 1003 of present embodiment is compared with the semiconductor device 1001 of execution mode 1, leaks the structure difference of connecting wiring 50 and grid connecting wiring 40, and other structures are the same.In the present embodiment, for giving same symbol, then omit with the explanation that execution mode 1 repeats with the structure of the corresponding present embodiment of structure of execution mode 1.
In the present embodiment, leak connecting wiring 50, shown in Fig. 3 A to Fig. 3 C, have and connect a pair of leakage contact 104 (104-1～104-8) and leak contact 204 (broach wiring 50-1～50-8 of 204-1～204-8) and be connected broach connect up shared wiring 50-C and the 50-D of 50-1～50-8.
Shown in Fig. 3 C, shared wiring 50-C connects leakage contact 104-1 and 104-2,104-3 and 104-4,104-5 and 104-6,104-7 and the 104-8 of pMOS 61 respectively.In other words, shared wiring 50-C connects broach wiring 50-1 and 50-2,50-3 and 50-4,50-5 and 50-6,50-7 and 50-8 respectively in the leakage contact of pMOS 61 104 sides.
Shown in Fig. 3 C, shared wiring 50-D connects leakage contact 204-2 and 204-3,204-4 and 204-5,204-6 and the 204-7 of nMOS 62 respectively.In other words, shared wiring 50-D connects broach wiring 50-2 and 50-3,50-4 and 50-5,50-6 and 50-7 respectively in the leakage contact of nMOS 62 204 sides.
In Fig. 3 C, 50-1 is connected by shared wiring 50-C with 50-2 by the broach wiring, broach wiring 50-2 is connected by shared wiring 50-D with 50-3, broach wiring 50-3 is connected such connected mode with 50-4 by shared wiring 50-C, makes two broach of adjacency be routed in pMOS 61 sides and nMOS 62 top-cross and replaces and be connected and constitute.Shared wiring 50-C forms along the arrangement of leaking contact 104-1～104-8 on leakage contact 104-1～104-8, is configured on the boundary line 5011 in zone 510 and zone 501.Shared wiring 50-D forms along the arrangement of leaking contact 204-1～204-8 on leakage contact 204-1～204-8, is configured on the boundary line 5021 in zone 510 and zone 502.
In execution mode 1 and execution mode 2, the shared wiring of leaking connecting wiring 50 is to form in the outside of leaking the zone between the contact 104 and 204, but in the present embodiment the configuring area that leaks connecting wiring 50 is not limited.In other words, because also can connect whole leak routing 50-C, the 50-D of configuration on the metal line zone 510 of leakage contact 204-1～204-8 of the leakage contact 104-1～104-8 of pMOS 61 and nMOS 62, the degree of freedom height of layout at straight line.
(3-2) action effect
Flow into the surge current that respectively leaks contact 104-1～104-8 of pMOS 61, flow into leakage contact 204-1～204-8 of nMOS 62 through each broach wiring 50-1～50-8 of correspondence.At this moment,, flow into the surge current of specific leakage contact 204, suppress to become the surge current that is to the maximum from 4 leakage contacts 104 even come the surge current of natural leak contact 104-1～104-8 to concentrate among leakage contact 204-1～204-8 of specific nMOS62.
Below with reference to Fig. 3 C its reason is described.
In the figure, surge current is from the leakage contact 204-5 of the inflow nMOS 62 of the leakage contact 104-5 of paired pMOS 61.In addition, surge current also might flow into and leaks contact 204-5 through connect up 50-4, shared wiring 50-D of broach from leaking contact 104-4.In addition, surge current might flow into and leak contact 204-5 through shared wiring 50-C, broach wiring 50-4, shared wiring 50-D from leaking contact 104-3.In addition, also might flow into Lou contact 204-5 through shared wiring 50-C, broach wiring 50-5 from leaking contact 104-6.Therefore, surge current might leak contact 104-3,104-4,104-5,104-6 inflow leakage contact 204-5 from adding up to 4.
On the other hand, surge current can be from not flowing into leakage contact 204-5 than leaking contact 104-3,104-4,104-5,104-6 leakage contact 104 a long way off.For example, make surge current flow into and leak contact 204-5 from leaking contact 104-2, surge current must according to leak contact 104-2, broach wiring 50-2, leak contact 204-2, shared wiring 50-D, leak contact 204-3, broach wiring 50-3, leak contact 104-3, shared wiring 50-C, leak contact 104-4, broach wiring 50-4, the sequential flow of leaking contact 204-4, shared wiring 50-D and leaking contact 204-5 cross leakage connecting wiring 50.Yet, in above-mentioned path, towards the part of leaking contact 204-3, broach wiring 50-3, leaking contact 104-3, it is the direction of in broach wiring 50-3, pMOS 61 sides from nMOS 62 side direction, owing to be, do not flow through so do not have this surge current against direction from the electric field of pMOS 61 towards nMOS 62.In addition, make surge current flow into and leak contact 204-5 from leaking contact 104-7, surge current must according to leak contact 104-7, broach wiring 50-7, leak contact 204-7, shared wiring 50-D, leak contact 204-6, broach wiring 50-6, leak contact 104-6, shared wiring 50-C, leak contact 104-5, broach wiring 50-5, the sequential flow of leaking contact 204-5 cross leakage connecting wiring 50.Yet, in above-mentioned path, towards the part of leaking contact 204-6, broach wiring 50-6, leaking contact 104-6, it is the direction of in broach wiring 50-6, pMOS 61 sides from nMOS 62 side direction, owing to be, do not flow through so do not have this surge current against direction from the electric field of pMOS 61 towards nMOS 62.More than, as illustrational,, flowing into the surge current that respectively leaks contact 204 of nMOS 62 according to the structure of the leakage connecting wiring 50 of present embodiment to leak contact 204-5, maximum constraints be the surge currents from 4 leakage contacts 104 of pMOS 61.
Structure according to the leakage connecting wiring 50 of present embodiment, because the surge current that respectively leaks contact 204-1～204-8 of stream nMOS 62, maximum constraints is 4 inflow currents that leak contact 104-1～104-8 from pMOS 61, can prevent reliably because deterioration or the destruction that the surge current of nMOS 62 causes.Therefore, even in semiconductor device 1003, load the occasion of extensive cmos circuit 65, because constitute each cmos circuit 60 of extensive cmos circuit 65 also can keep least unit or with the easy fluidity of the equal static surge current of the cmos circuit of smallest size, and can solve and prevent to make a plurality of inverter group and the group of buffers that in semiconductor device 1003, exist integrally keep the effect of guaranteeing the static tolerance because the concentration of local of surge current causes nMOS 62 deteriorations or the problem that damages.
In addition, in the present embodiment, shown in enforcement mode 1 and execution mode 2, do not have the shared wiring of leaking connecting wiring 50 must to be configured in than the restriction in this configuration in the zone 501,502 of more lateral between the leakage contact of pMOS 61 and nMOS 62.Therefore, the major part of leaking the shared wiring of connecting wiring 50 can be configured in the zone 510 degree of freedom height of layout.
In the present embodiment, because in existing C MOS manufacturing process, only change the method for attachment of leaking connecting wiring 50, so the manufacturing process that does not need to change CMOS simultaneously just can implement.In addition, because can use the wiring join domain of preparing in original cmos circuit, do not worry that the area of cmos circuit increases.If, even connecting wiring increases the zone in order to draw Lou, because just respectively by very thin shared wiring 50-C, a 50-D, the influence that area increases is slight.
In addition, in above-mentioned, illustrational is the occasion of surge current concentration of local in specific nMOS 62, even but from the occasion of surge current concentration of local among specific pMOS 61 of earth connection connecting wiring 20 side inflows, the formation of present embodiment also has same effect and effect.
(3-3) variation
(A) structure of present embodiment is the shared wiring 50-C that forms leakage connecting wiring 50 on the 104-1～104-8 of contact leaking, the part of shared wiring 50-C is configured in than leaking contact 104-1～104-8 more near earth connection connecting wiring 20 sides, the same with execution mode 1 or execution mode 2, also can be that the shared wiring 50-C that will leak connecting wiring 50 is configured in regional 501 interior structures.
Constitute when leaking connecting wiring 50 like this, by shared wiring 50-C being configured in against from the path of the electric field of pMOS 61 towards nMOS 62, can limit flowing of surge current between the broach wiring 50-1～50-8 of adjacency more reliably, more can limit flowing into the electric current that leaks contact 204.So, can make a plurality of inverter group and the group of buffers that in semiconductor device 1003, exist further improve the static tolerance on the whole.
(B) in addition, also can be that shared wiring 50-D is configured in regional 502 interior structures.In this occasion, at surge current during from earth connection connecting wiring 20 side inflows, by shared wiring 50-D being configured in against from the path of the electric field of nMOS 61 towards pMOS 62, can limit flowing of surge current between the broach wiring 50-1～50-8 of adjacency more reliably, more can limit flowing into the electric current that leaks contact 104, can prevent the concentration of local of surge current in pMOS 61.So, can utilize a plurality of inverter group and the group of buffers that in semiconductor device 1003, exist further to improve the static tolerance on the whole.
(C) also can when shared wiring 50-C being configured in regional 501, shared wiring 50-D be configured in the zone 502.In this occasion, in the occasion of surge current from power line connecting wiring 10 side inflows, in can being suppressed at nMOS 62 in the concentration of local of surge current, also can suppress the concentration of local of surge current among pMOS 61 from the occasion of earth connection connecting wiring 20 side inflows at surge current.
(D) in the occasion of surge current concentration of local in nMOS 62, the shared wiring 50-C of leakage contact 104-1～104-8 side of pMOS 61 is configured in the zone 501, in the occasion of surge current concentration of local in pMOS 61, also the shared wiring 50-D of leakage contact 204-1～204-8 side of nMOS 62 can be configured in the zone 502.
(E) in above-mentioned, be on the 1st interlayer dielectric, to form Lou shared wiring 50-C and the 50-D and the broach wiring 50-1～50-8 of connecting wiring 50 by the 1st layer of metal wiring layer, but also can form broach wiring 50-1～50-8 by the 1st layer of metal wiring layer, by than the 1st layer of metal wiring layer more the 2nd wiring layer etc. on upper strata form shared wiring 50-C and 50-D.For example, in the occasion that forms shared wiring 50-C and 50-D by the 2nd layer of metal wiring layer, covering shared wiring 50-C and the 50-D that forms on the 2nd interlayer dielectric of the 1st layer of metal wiring layer as the 2nd layer of metal wiring layer, shared wiring 50-C and 50-D and the broach 50-1～50-8 that connects up is being electrically connected by the contact that on the 2nd interlayer dielectric, forms.Like this, in the occasion that forms shared wiring 50-C and 50-D,, can increase the degree of freedom of the layout of grid connecting wiring 40 because shared wiring 50-C and 50D are configured in the layer different with grid connecting wiring 40.In addition, also can only form at least one or the part of shared wiring 50-C and 50-D by the 2nd layer of metal wiring layer.
(F) in above-mentioned, be on the 1st interlayer dielectric, to form Lou connecting wiring 50 and grid connecting wiring 40 by the 1st layer of metal wiring layer, but also can form Lou connecting wiring 50 by the 1st layer of metal wiring layer, by than the 1st layer of metal wiring layer more the 2nd wiring layer etc. on upper strata form grid connecting wiring 40.For example, in the occasion that forms grid connecting wiring 40 by the 2nd layer of metal wiring layer, also can on the 2nd interlayer dielectric that covers the 1st layer of metal wiring layer, form grid connecting wiring 40, be electrically connected by the 402 pairs of grid connecting wirings 40 in grid contact and the gate electrode 401 that connect the 1st and the 2nd interlayer dielectric as the 2nd layer of metal wiring layer.Like this, in the occasion that forms grid connecting wiring 40 because grid connecting wiring 40 be configured in leak connecting wiring 50 different layer in, can increase the degree of freedom of the layout of grid connecting wiring 40.
(4) execution mode 4
(4-1) structure
Fig. 4 A is the plane graph of the semiconductor device 1004 of embodiments of the present invention 4.Fig. 4 B is each regional key diagram of the semiconductor device 1004 of explanation in the plane graph of Fig. 4 A.Fig. 4 C is for illustrating the key diagram of the ESD path of current that flows through in the semiconductor device 1004 in the plane graph of Fig. 4 A.
The semiconductor device 1004 of present embodiment is compared with the semiconductor device 1001 of execution mode 1, leaks the structure difference of connecting wiring 50 and grid connecting wiring 40, and other structures are the same.In the present embodiment, for giving same symbol, then omit with the explanation that execution mode 1 repeats with the structure of the corresponding present embodiment of structure of execution mode 1.
In the present embodiment, leak connecting wiring 50, shown in Fig. 4 A to Fig. 4 C, (104-1～104-8) and nMOS's 62 respectively leaks contact 204 (broach wiring 50-1～50-8 and the connecting wiring 50-d1～50-d7 of 204-1～204-8) to have the contact 104 of respectively leaking that connects pMOS 61.
Connecting wiring 50-d1～50-d7, connect pMOS 61 leakage contact 104 and with the leakage contact 204 of leakage contact 204 adjacency of paired nMOS 62.In other words, leaking connecting wiring 50 is each leakage contact to be made with the such mode of 204-2,204-2 and 104-2 with 104-1,104-1 with 204-1 respectively leak the structure that is connected with nMOS side warpage in the pMOS side between the contact on each interval.In specific words, each connecting wiring 50-d1～50-d7 connects leakage contact 104-1 and 204-2,104-2 and 204-3,104-3 and 204-4,104-4 and 204-5,104-5 and 204-6,104-6 and 204-7,104-7 and 204-8 respectively.
Each connecting wiring 50-d1～50-d7 with respect to two straight lines that the leakage contact is connected and obtains that will connect at the place, two ends of each connecting wiring, lays particular stress on and is leaking contact 204 sides.For example, connecting wiring 50-d1 lays particular stress in leakage contact 204 sides with respect to linking the straight line that leaks contact 104-1 and 204-2.Each connecting wiring 50-d1～50-d7 is leaking contact 204 sides owing to lay particular stress on, and walks around grid contact 402 in earth connection connecting wiring 20 sides and connects leakage contact 104-1 and 204-2.Connecting wiring 50-d1～50-d7, in order to walk around grid contact 402 in earth connection connecting wiring 20 sides, its structure is that a plurality of parts of the bearing of trend of earth connection connecting wiring 20 reach along alternately connection of a plurality of parts from leakage contact 104 towards the direction of leaking contact 204.
In addition, each connecting wiring 50-d1～50-d7 also can be to leak the straight line that the contact is connected and obtains with respect to two that will connect at the two ends of each connecting wiring, lays particular stress on and is leaking contact 104 sides, walks around the structure of grid contact 402 in power line connecting wiring 10 sides.
(4-2) action effect
According to the leakage connecting wiring 50 of this structure, when power line connecting wiring 10 flowed into, (103-1～103-9), source region 101, drain region 102 flowed into and leak contacts 104 (104-1～104-8) surge current through the contact, source 103 of pMOS 61 at surge current.
Flow into pMOS 61 respectively leak contact 104 (for example, surge current 104-5) flow into paired leakage contact 204 (for example, 204-5) or with this leakage contact of leaking contact 204 adjacency (for example, 204-6).Therefore, flow into specific leakage contact 204 (for example, inrush current limitation 204-5) be from paired leakage contact 104 (104-5) or with leakage contact 104 (for example, surge current 104-4) of paired leakage contact 104 adjacency.So, even suppose surge current concentration of local in the specific leakage contact 204 of nMOS 62, in the specific leakage contact 204 of nMOS 62 inrush current limitation be from paired leakage contact 104 and with the surge current of the leakage contact 104 of these leakage contact 104 adjacency.
Below with reference to Fig. 4 C its reason is described.
In the figure, the surge current that flows into the leakage contact 204-5 of nMOS 62 is that leakage contact 104-5 from paired pMOS 61 flows into.In addition, surge current also might leak contact 204-5 from flowing into through connecting wiring 50-d4 with the leakage contact 104-4 that leaks contact 104-5 adjacency.Therefore, surge current might leak contact 104--4,104-5 inflow leakage contact 204-2 from adding up to 2.
On the other hand, surge current can be from not flowing into leakage contact 204-5 than leaking contact 104-4,104-5 leakage contact 104 a long way off.For example, make surge current from leaking contact 104-3 inflow leakage contact 204-5, surge current must be crossed leakage connecting wiring 50 according to the sequential flow of leaking contact 104-3, connecting wiring 50-d3, leakage contact 204-4, broach wiring 50-4, leakage contact 104-4, connecting wiring 50-d4, leakage contact 204-5.Yet, in this path, the part of leak contact 204-4, broach wiring 50-4, leaking contact 104-4, it is the direction of in broach wiring 50-4, pMOS 61 sides from the nMOS62 side direction, owing to be, do not flow through so do not have this surge current against direction from the electric field of pMOS 61 towards nMOS 62.
In addition, make surge current leak contact 204-5 from leakage contact 104-6 inflow, surge current must be crossed leakage connecting wiring 50 according to the sequential flow of leakage contact 104-6, broach wiring 50-6, leakage contact 204-6, connecting wiring 50-d5, leakage contact 104-5, broach wiring 50-5, leakage contact 204-5.Yet, in above-mentioned path, the part of leak contact 204-6, connecting wiring 50-d5, leaking contact 104-5, it is the direction of in broach wiring 50-d5, pMOS 61 sides from nMOS 62 side direction, owing to be, do not flow through so do not have this surge current against direction from the electric field of pMOS 61 towards nMOS 62.
As mentioned above, as being the example explanation to leak contact 204-5, in the leakage connecting wiring 50 of present embodiment, leaking contact 204 is to be connected to two by broach wiring and connecting wiring to leak contact 104, and flexes into Lou contact 204 sides in the outside by connecting wiring from two leakage contacts 104 that connect the destination.Therefore, make surge current flow into above-mentioned leakage contact 204, must generate, can not flow into from leaking contact 204 to the path of leaking contact 104 sides from two leakage contacts 104 of leaking the outside of contact 104 that connect the destination.According to the structure of the leakage connecting wiring 50 of present embodiment, flow into the surge current that respectively leaks contact 204 of nMOS 62, maximum constraints be the surge currents from 2 leakage contacts 104 of pMOS 61.
Structure according to the leakage connecting wiring 50 of present embodiment, because flow into the surge current that respectively leaks contact 204 of nMOS 62, maximum constraints is 2 inflow currents that leak contact 104 from pMOS 61, can prevent reliably because deterioration or the destruction that the surge current of nMOS 62 causes.Therefore, even in semiconductor device 1004, load the occasion of extensive cmos circuit 65, because constitute each cmos circuit 60 of extensive cmos circuit 65 also can keep least unit or with the easy fluidity of the equal static surge current of the cmos circuit of smallest size, and can solve and prevent to make a plurality of inverter group and the group of buffers that in semiconductor device 1004, exist keep the effect of guaranteeing the static tolerance universally because the concentration of local of surge current causes nMOS62 deterioration or the problem that damages.
In addition, in the present embodiment, shown in enforcement mode 1 and execution mode 2, there is not the shared wiring of leaking connecting wiring 50 must to be configured in the restriction in this configuration in zone 501 of power line connecting wiring 10 sides.Therefore, the major part of leaking connecting wiring 50 can be configured in the zone 510 degree of freedom height of layout.
In the present embodiment, because in existing C MOS manufacturing process, only change the method for attachment of leaking connecting wiring 50, so the manufacturing process that does not need to change CMOS simultaneously just can implement.In addition, because can use the wiring join domain of preparing in original cmos circuit, do not worry that the area of cmos circuit increases.
In addition, in above-mentioned, illustrational is the occasion of surge current concentration of local in specific nMOS 62, even but from the occasion of surge current concentration of local among specific pMOS 61 of earth connection connecting wiring 20 side inflows, the formation of present embodiment also has same effect and effect.
(4-3) variation
(A) in above-mentioned, be on the 1st interlayer dielectric, to form Lou the connecting wiring 50-d1～50-d7 and the broach wiring 50-1～50-8 of connecting wiring 50 by the 1st layer of metal wiring layer, but also can form broach wiring 50-1～50-8 by the 1st layer of metal wiring layer, by than the 1st layer of metal wiring layer more the 2nd wiring layer etc. on upper strata form connecting wiring 50-d1～50-d7.For example, in the occasion that forms connecting wiring 50-d1～50-d7 by the 2nd layer of metal wiring layer, also can on the 2nd interlayer dielectric that covers the 1st layer of metal wiring layer, form connecting wiring 50-d1～50-d7, connecting wiring 50-d1～50-d7 and broach wiring 50-1～50-8 are electrically connected by the contact that on the 2nd interlayer dielectric, forms as the 2nd layer of metal wiring layer.Like this, in the occasion that forms connecting wiring 50-d1～50-d7,, can increase the degree of freedom of the layout of grid connecting wiring 40 because connecting wiring 50-d1～50-d7 is configured in the layer different with grid connecting wiring 40.In addition, also can only form at least one or the part of connecting wiring 50-d1～50-d7 by the 2nd layer of metal wiring layer.
(B) in above-mentioned, be on the 1st interlayer dielectric, to form Lou connecting wiring 50 and grid connecting wiring 40 by the 1st layer of metal wiring layer, but also can form Lou connecting wiring 50 by the 1st layer of metal wiring layer, by than the 1st layer of metal wiring layer more the 2nd wiring layer etc. on upper strata form grid connecting wiring 40.For example, in the occasion that forms grid connecting wiring 40 by the 2nd layer of metal wiring layer, also can on the 2nd interlayer dielectric that covers the 1st layer of metal wiring layer, form grid connecting wiring 40, be electrically connected by the 402 pairs of grid connecting wirings 40 in grid contact and the gate electrode 401 that connect the 1st and the 2nd interlayer dielectric as the 2nd layer of metal wiring layer.Like this, in the occasion that forms grid connecting wiring 40 because grid connecting wiring 40 be configured in leak connecting wiring 50 different layer in, can increase the degree of freedom of the layout of grid connecting wiring 40.
Claims (26)
1. semiconductor device is characterized in that having:
The 1st wiring;
The 2nd wiring along above-mentioned the 1st wiring configuration;
Be configured in the 1MOS transistor of a plurality of the 1st conduction types of above-mentioned the 1st wiring side between above-mentioned the 1st wiring and above-mentioned the 2nd wiring, this 1MOS transistor comprises the 1st contact, the 2nd contact that is connected with above-mentioned the 1st wiring and is configured in the 1st control electrode between above-mentioned the 1st contact and the 2nd contact;
Between above-mentioned the 1st wiring and above-mentioned the 2nd wiring, be configured in above-mentioned the 2nd wiring side, constitute in pairs the 2MOS transistor of a plurality of the 2nd conduction types of a plurality of cmos circuits with each 1MOS transistor, this 2MOS transistor comprise the 3rd contact, with the above-mentioned the 2nd connect up the 4th contact that is connected and be configured in above-mentioned the 3rd contact and above-mentioned the 4th contact between the 2nd control electrode;
Make interconnected the 3rd wiring in above-mentioned a plurality of the 2nd contact and above-mentioned a plurality of the 3rd contact, the 3rd wiring comprises makes the 2nd paired mutually contact and the 3rd contact a plurality of the 4th wirings that connect respectively and a plurality of the 5th wirings that are connected between the 4th wiring, and at least one the 5th wiring is to form in the 1st zone of above-mentioned the 1st wiring side that is defined in above-mentioned the 2nd contact.
2. semiconductor device as claimed in claim 1 is characterized in that: in above-mentioned the 1st zone, form the 5th the wiring with nonoverlapping zone, the 2nd contact in form.
3. semiconductor device as claimed in claim 1 or 2 is characterized in that: at least one the 5th is routed in the 2nd zone that is defined as than more close above-mentioned the 2nd wiring side in above-mentioned the 2nd contact and forms a part at least.
4. semiconductor device as claimed in claim 3 is characterized in that: the both sides of the 5th wiring that forms in above-mentioned the 1st zone, dispose the 5th wiring that forms a part in above-mentioned the 2nd zone at least.
5. as each the described semiconductor device in the claim 1 to 4, it is characterized in that: the part of above-mentioned the 5th wiring is that the metal wiring layer on upper strata forms by connecting up more than the 4th.
6. as each the described semiconductor device in the claim 1 to 5, it is characterized in that: also have a plurality of the 6th wirings that are electrically connected, form roughly " コ " word shape of above-mentioned the 2nd wiring side of surrounding above-mentioned the 4th wiring with above-mentioned the 1st control electrode and above-mentioned the 2nd control electrode.
7. semiconductor device as claimed in claim 1 is characterized in that: above-mentioned the 1st control electrode and above-mentioned the 2nd control electrode are integrally formed.
8. as each the described semiconductor device in the claim 1 to 7, it is characterized in that: above-mentioned a plurality of 1MOS transistors, above-mentioned a plurality of 2MOS transistors and the 3rd wiring constitute CMOS inverter circuit or cmos buffer device circuit.
9. semiconductor device as claimed in claim 1 or 2 is characterized in that:
Above-mentioned a plurality of 1MOS transistor, above-mentioned a plurality of 2MOS transistors and the 3rd wiring constitute CMOS inverter circuit or cmos buffer device circuit;
Above-mentioned a plurality of the 5th wirings all form in above-mentioned the 1st zone in above-mentioned cmos buffer device circuit.
10. semiconductor device is characterized in that having:
The 1st wiring;
The 2nd wiring along above-mentioned the 1st wiring configuration;
Be configured in the 1MOS transistor of a plurality of the 1st conduction types of above-mentioned the 1st wiring side between above-mentioned the 1st wiring and above-mentioned the 2nd wiring, this 1MOS transistor has the 1st contact, the 2nd contact that is connected with above-mentioned the 1st wiring and is configured in the 1st control electrode between above-mentioned the 1st contact and the 2nd contact;
Between above-mentioned the 1st wiring and above-mentioned the 2nd wiring, be configured in above-mentioned the 2nd wiring side, constitute in pairs the 2MOS transistor of a plurality of the 2nd conduction types of a plurality of cmos circuits with each 1MOS transistor, this 2MOS transistor comprise the 3rd contact, with the above-mentioned the 2nd connect up the 4th contact that is connected and be configured in above-mentioned the 3rd contact and above-mentioned the 4th contact between the 2nd control electrode;
Make interconnected the 3rd wiring in above-mentioned a plurality of the 2nd contact and above-mentioned a plurality of the 3rd contact, the 3rd wiring comprises a plurality of the 4th wirings that the 2nd mutually paired contact and the 3rd contact are connected respectively, connects one or more the 5th wirings between the 4th wiring and connect one or more the 6th wirings between the 4th wiring in above-mentioned the 3rd contact side in above-mentioned the 2nd contact side.
11. semiconductor device as claimed in claim 10 is characterized in that: above-mentioned the 5th wiring and the 6th wiring alternately connect between the 4th wiring.
12. semiconductor device as claimed in claim 10 is characterized in that:
Above-mentioned the 5th wiring connects the 4th wiring and next the 4th wiring of odd indexed, and above-mentioned the 6th wiring connects the 4th wiring and next the 4th wiring of even number sequence number, or
Above-mentioned the 5th wiring connects the 4th wiring and next the 4th wiring of even number sequence number, and above-mentioned the 6th wiring connects the 4th wiring and next the 4th wiring of odd indexed.
13. each the described semiconductor device as in the claim 10 to 11 is characterized in that: at least one the 5th wiring is to form in the 1st zone of above-mentioned the 1st wiring side that is defined in above-mentioned the 2nd contact.
14. each the described semiconductor device as in the claim 10 to 11 is characterized in that: at least one the 6th wiring is to form in the 2nd zone of above-mentioned the 1st wiring side that is defined in above-mentioned the 3rd contact.
15. as each the described semiconductor device in the claim 10 to 14, it is characterized in that: also have between above-mentioned the 4th wiring a plurality of the 7th wirings that the opposition side of a side that connects from being connected up by above-mentioned the 5th wiring or the above-mentioned the 6th extends and is electrically connected with above-mentioned the 1st control electrode and above-mentioned the 2nd control electrode towards a side of above-mentioned connection.
16. each the described semiconductor device as in the claim 10 to 15 is characterized in that: the part of above-mentioned the 5th wiring is that the metal wiring layer on upper strata forms by connecting up more than the 4th.
17. each the described semiconductor device as in the claim 11 to 16 is characterized in that: above-mentioned a plurality of 1MOS transistors, above-mentioned a plurality of 2MOS transistors and the 3rd wiring constitute CMOS inverter circuit or cmos buffer device circuit.
18. semiconductor device as claimed in claim 17 is characterized in that: above-mentioned a plurality of the 5th wirings all are to be defined as in the 1st zone of above-mentioned the 1st wiring side of above-mentioned the 2nd contact to form in above-mentioned CMOS inverter circuit or above-mentioned cmos buffer device circuit.
19. semiconductor device as claimed in claim 17 is characterized in that: above-mentioned a plurality of the 6th wirings all are to be defined as in the 2nd zone of above-mentioned the 1st wiring side of above-mentioned the 3rd contact to form in above-mentioned CMOS inverter circuit or above-mentioned cmos buffer device circuit.
20. semiconductor device as claimed in claim 17, it is characterized in that: in above-mentioned CMOS inverter circuit or above-mentioned cmos buffer device circuit, above-mentioned a plurality of the 5th wiring all is to form in the 1st zone of above-mentioned the 1st wiring side that is defined in above-mentioned the 2nd contact, and above-mentioned a plurality of the 6th wiring all is to form in the 2nd zone of above-mentioned the 1st wiring side that is defined in above-mentioned the 3rd contact.
21. a semiconductor device is characterized in that having:
The 1st wiring;
The 2nd wiring along above-mentioned the 1st wiring configuration;
Be configured in the 1MOS transistor of a plurality of the 1st conduction types of above-mentioned the 1st wiring side between above-mentioned the 1st wiring and above-mentioned the 2nd wiring, this 1MOS transistor has the 1st contact, the 2nd contact that is connected with above-mentioned the 1st wiring and is configured in the 1st control electrode between above-mentioned the 1st contact and the 2nd contact;
Between above-mentioned the 1st wiring and above-mentioned the 2nd wiring, be configured in above-mentioned the 2nd wiring side, constitute in pairs the 2MOS transistor of a plurality of the 2nd conduction types of a plurality of cmos circuits with each 1MOS transistor, this 2MOS transistor comprise the 3rd contact, with the above-mentioned the 2nd connect up the 4th contact that is connected and be configured in above-mentioned the 3rd contact and above-mentioned the 4th contact between the 2nd control electrode;
Make interconnected the 3rd wiring in above-mentioned a plurality of the 2nd contact and above-mentioned a plurality of the 3rd contact, the 3rd wiring comprise make a plurality of the 4th wirings that the 2nd mutually paired contact and the 3rd contact connect respectively be connected the 2nd contact and with a plurality of the 5th wirings of the 3rd contact of paired the 3rd contact adjacency in the 2nd contact.
22. semiconductor device as claimed in claim 21 is characterized in that: each the 5th wiring, the straight line that obtains with respect to linking the 2nd contact that connected by the 5th wiring and the 3rd contact is laid particular stress in the 2nd contact side or the 3rd contact side.
23. semiconductor device as claimed in claim 22 is characterized in that: also have between the 4th wiring, lay particular stress on the 6th connecting up that side extends and is electrically connected with above-mentioned the 1st control electrode and above-mentioned the 2nd control electrode to above-mentioned from above-mentioned opposition side of laying particular stress on side.
24. each the described semiconductor device as in the claim 21 to 23 is characterized in that: the part of above-mentioned the 5th wiring is to be formed by the metal wiring layer than the 4th more upper strata of connecting up.
25. each the described semiconductor device as in the claim 21 to 24 is characterized in that: above-mentioned a plurality of 1MOS transistors, above-mentioned a plurality of 2MOS transistors and the 3rd wiring constitute cmos buffer device circuit.
26. a semiconductor device is characterized in that comprising:
Semiconductor substrate, comprise have the 1st zone, with the 2nd zone of above-mentioned the 1st regional adjacency, with the 3rd zone of above-mentioned the 2nd regional adjacency, with the 4th zone of above-mentioned the 3rd regional adjacency, with the surface in the 5th zone of above-mentioned the 4th regional adjacency;
The 1st impurity range that in above-mentioned the 2nd zone, forms, constitute by the 1st conduction type;
The 2nd impurity range that in above-mentioned the 4th zone, forms, constitute by the 2nd conduction type different with above-mentioned the 1st conduction type;
By the 1st trunk wiring portion that in above-mentioned the 1st zone, forms with spreading all over the 1st wiring that the wiring portion of the 1st branch that forms on the above-mentioned the 1st and the 2nd zone constitutes;
The 1st contact that on above-mentioned the 2nd zone, forms, wiring portion of above-mentioned the 1st branch and above-mentioned the 1st impurity range are electrically connected;
By the 2nd connecting up that the 2nd trunk wiring portion that forms on above-mentioned the 5th zone and the above-mentioned the 4th and the 5th wiring portion of the 2nd branch that forms of zone that spreads all over constitute;
The 2nd contact that on above-mentioned the 4th zone, forms, wiring portion of above-mentioned the 2nd branch and above-mentioned the 2nd impurity range are electrically connected;
By the 3rd trunk wiring portion that on above-mentioned the 2nd zone, forms with the 3rd connecting up of spreading all over that above-mentioned the 2nd, the 3rd and the 4th wiring portion of the 3rd branch that forms of zone constitutes;
The 3rd contact that on above-mentioned the 2nd zone, forms, wiring portion of above-mentioned the 3rd branch and above-mentioned the 1st impurity range are electrically connected; And
The 4th contact that on above-mentioned the 4th zone, forms, wiring portion of above-mentioned the 3rd branch and above-mentioned the 2nd impurity range are electrically connected.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005207296A JP4845177B2 (en) | 2005-07-15 | 2005-07-15 | Semiconductor device |
| JP2005207296 | 2005-07-15 | ||
| JP2005-207296 | 2005-07-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1897277A true CN1897277A (en) | 2007-01-17 |
| CN1897277B CN1897277B (en) | 2010-07-14 |
Family
ID=37609728
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006100773749A Expired - Fee Related CN1897277B (en) | 2005-07-15 | 2006-04-29 | Semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20070012951A1 (en) |
| JP (1) | JP4845177B2 (en) |
| KR (1) | KR101311117B1 (en) |
| CN (1) | CN1897277B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9508507B2 (en) | 2012-12-21 | 2016-11-29 | Mitsubishi Electric Corporation | Gas insulated electrical equipment |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0475371A (en) | 1990-07-18 | 1992-03-10 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit |
| JP3286470B2 (en) * | 1994-08-09 | 2002-05-27 | 三菱電機株式会社 | Semiconductor integrated circuit, method of manufacturing semiconductor integrated circuit, and method of arranging cells |
| JP2912174B2 (en) * | 1994-12-27 | 1999-06-28 | 日本電気株式会社 | Library group and semiconductor integrated circuit using the same |
| US5789791A (en) * | 1996-08-27 | 1998-08-04 | National Semiconductor Corporation | Multi-finger MOS transistor with reduced gate resistance |
| JP2953416B2 (en) * | 1996-12-27 | 1999-09-27 | 日本電気株式会社 | Semiconductor device |
| JPH11214662A (en) * | 1998-01-29 | 1999-08-06 | Mitsubishi Electric Corp | Semiconductor device |
| JP2001007293A (en) * | 1999-06-25 | 2001-01-12 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JP2001127173A (en) * | 1999-11-01 | 2001-05-11 | Ricoh Co Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
| JP2001339046A (en) * | 2000-05-29 | 2001-12-07 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| DE10041139A1 (en) * | 2000-08-21 | 2002-03-14 | Philips Corp Intellectual Pty | Arrangement to improve ESD protection in a CMOS buffer |
-
2005
- 2005-07-15 JP JP2005207296A patent/JP4845177B2/en active Active
-
2006
- 2006-04-29 CN CN2006100773749A patent/CN1897277B/en not_active Expired - Fee Related
- 2006-05-01 KR KR1020060039315A patent/KR101311117B1/en active IP Right Grant
- 2006-06-22 US US11/425,706 patent/US20070012951A1/en not_active Abandoned
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9508507B2 (en) | 2012-12-21 | 2016-11-29 | Mitsubishi Electric Corporation | Gas insulated electrical equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007027407A (en) | 2007-02-01 |
| CN1897277B (en) | 2010-07-14 |
| KR20070009379A (en) | 2007-01-18 |
| JP4845177B2 (en) | 2011-12-28 |
| KR101311117B1 (en) | 2013-09-25 |
| US20070012951A1 (en) | 2007-01-18 |
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