CN1892991A - Method for fabricating semiconductor device with deep opening - Google Patents

Method for fabricating semiconductor device with deep opening Download PDF

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Publication number
CN1892991A
CN1892991A CNA2005100975337A CN200510097533A CN1892991A CN 1892991 A CN1892991 A CN 1892991A CN A2005100975337 A CNA2005100975337 A CN A2005100975337A CN 200510097533 A CN200510097533 A CN 200510097533A CN 1892991 A CN1892991 A CN 1892991A
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perforate
insulating barrier
gas
bending resistance
layer
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CN100472732C (en
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赵瑢泰
李海朾
曹祥薰
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method for fabricating a semiconductor device with a deep opening is provided. The method includes: forming an insulation layer on a substrate; selectively etching the insulation layer to form first openings; enlarging areas of the first openings; forming anti-bowing spacers on sidewalls of the enlarged first openings; and etching portions of the insulation layer remaining beneath the enlarged first openings to form second openings.

Description

Manufacture method with semiconductor device of deep opening
The application requires all to submit on June 30th, 2005 priority of the korean patent application KR2005-58886 and the KR 2005-58893 of Korean Patent office, and its full content is incorporated this paper by reference into.
Technical field
The present invention relates to the manufacture method of semiconductor device, more specifically relate to the manufacture method of semiconductor device with dark contact hole.
Background technology
Because the drawingdimension of dynamic random access memory (DRAM) reduces, therefore the thickness that forms the photoresist pattern of contact hole as mask also reduces.Thereby, if the photoresist pattern is used for forming contact hole, then the edge thickness deficiency of photoresist pattern separately.Adopt hard mask when for this reason, forming contact hole at present.Yet, if after contact hole forms, keep hard mask, because the stress level difference makes the existence of hard mask often cause that boundary layer raises between hard mask and the boundary layer.Therefore, remove hard mask and also become important.
In the capacitor process in nearest DRAM, the hard mask that is used for forming storage node contact hole is formed by polysilicon or nitride.Storage node contact hole provides the contact hole of three-dimensional structure, wherein will form memory node and connect memory node and storage node contact plug.
Figure 1A and 1B are the sectional views that capacitor manufacture method in the conventional semiconductor devices is shown.
With reference to Figure 1A, first insulating barrier 12 is formed on the substrate 11, and substrate 11 also comprises transistor and the bit line that is formed on wherein.Storage node contact hole forms by etching first insulating barrier 12, and the storage node contact plug material is filled in the storage node contact hole, thereby forms storage node contact plug 13.Although do not illustrate, because bit line, transistor and word line just prepared before forming first insulating barrier 12, therefore first insulating barrier 12 forms with sandwich construction.
Be described in further detail the formation of storage node contact plug 13, on first insulating barrier 12 He in the storage node contact hole, form polysilicon layer.Then, carry out etch-back process or chemico-mechanical polishing (CMP) process, removing the polysilicon layer on first insulating barrier 12, thereby form storage node contact plug 13.
On the storage node contact plug 13 and first insulating barrier 12, form etching stopping layer 14.On etching stopping layer 14, form second insulating barrier 15 and the 3rd insulating barrier 16 successively, to form capacitor arrangement.Etching stopping layer 14 is formed by silicon nitride and serve as etch stop layer when etching second insulating barrier 15 and the 3rd insulating barrier 16.Second insulating barrier 15 and the 3rd insulating barrier 16 are provided at the three-dimensional structure that wherein forms memory node.Second insulating barrier 15 is phosphosilicate glass (PSG) layers, and the 3rd insulating barrier 16 is tetraethyl orthosilicate (TEOS) layers.
Hard mask 17 is formed on the 3rd insulating barrier 16.Form in the process of hard mask 17, although not shown, hard mask layer is formed on the 3rd insulating barrier 16 and has formed photoresist layer thereon.Utilize mask, photoresist layer forms pattern by exposure and developing process.Subsequently, utilize the photoresist pattern to come the etch hard mask layer, thereby obtain hard mask 17 as etching mask.
Utilize hard mask 17 the 3rd insulating barrier 16 and second insulating barrier 15 to be etched into and have high depth-width ratio as etching mask.The contact hole that Reference numeral 18 expressions form by above-mentioned etching process.Adopt wet etch process to make the area maximization of each contact hole 18.Afterwards, remove hard mask 17, and the described etching stopping layer 14 of etching is to expose storage node contact plug 13.
With reference to Figure 1B, in contact hole 18, form bottom electrode 19, and remove the 3rd insulating barrier 16 and second insulating barrier 15 by wet (dip-out) process that drains out.
As implied above, because pattern dimension has been scaled, thereby the size of contact that is used for the cylindrical capacitor (for example metal-insulator-metal type (MIM) type capacitor) of high length-diameter ratio also reduces.Therefore, shown in Figure 1A and 1B, increase the area of contact hole 18 and the height of capacitor.
Yet the area that increases contact hole 18 often causes producing bridge between neighboring capacitors owing to the distance between the capacitor is not enough.The generation of this bridge " X " is shown in Fig. 2 A.And the height that increases capacitor often causes unsuitable contact hole perforate.This unsuitable contact hole perforate " Y " is shown in Fig. 2 B.
In addition, above-mentioned restriction can bring dibit fault, unit fault or direct current (DC) fault, causes yield of semiconductor devices to descend.
Summary of the invention
According to embodiment of the present invention, the method that provides a kind of manufacturing to have the semiconductor device of dark contact hole, wherein said method can prevent to produce bridge and unsuitable contact hole perforate between capacitor.
According to embodiment of the present invention, provide a kind of method of making semiconductor device equally, comprising: on substrate, form insulating barrier; The selective etch insulating barrier is to form first perforate; Enlarge the area of first perforate; On the sidewall of first perforate that enlarges, form the bending resistance spacer; And the partial insulative layer of etch residue below first perforate that enlarges is to form second perforate.
According to embodiment of the present invention, provide a kind of method of making semiconductor device again, comprising: on substrate, form insulating barrier; The selective etch insulating barrier is to form first perforate; Enlarge the area of first perforate; On the sidewall of first perforate that enlarges, form the bending resistance spacer; The partial insulative layer of etch residue below first perforate that enlarges is to form second perforate; On the bottom of opening area and sidewall, form bottom electrode; Each opening area comprises first perforate and second perforate of expansion; And on bottom electrode, form dielectric layer and top electrode successively.
Description of drawings
The following description of the preferred embodiment that provides in conjunction with the accompanying drawings will make above-mentioned and further feature of the present invention be better understood, wherein:
Figure 1A and 1B are the sectional views of classical production process that the capacitor of semiconductor device is shown;
Fig. 2 A illustrates the figure that the bridge between the capacitor produces;
Fig. 2 B is the figure that unsuitable contact hole perforate is shown;
Fig. 3 A-3F illustrates the sectional view of method of making the capacitor of semiconductor device according to specific embodiments according to the invention.
Embodiment
The following detailed description in detail with reference to accompanying drawing has the method for the semiconductor device of dark contact hole according to the manufacturing of exemplary according to the invention.
Fig. 3 A-3F illustrates the sectional view of method of making the capacitor of semiconductor device according to specific embodiments according to the invention.
With reference to Fig. 3 A, on substrate 21, form first insulating barrier 22.Substrate 21 comprises word line, transistor and the bit line that is formed on wherein.Although not shown, etching first insulating barrier 22 is to form storage node contact hole.On first insulating barrier 22, form the storage node contact plug material subsequently, fill storage node contact hole.The storage node contact plug material can be a polysilicon.Carry out etch-back process or chemico-mechanical polishing (CMP) process on the storage node contact plug material, the result forms storage node contact plug 23.Equally, although not shown, because word line, transistor and bit line are formed on before 22 formation of first insulating barrier, therefore first insulating barrier 22 has sandwich construction.
On first insulating barrier 22 and storage node contact plug 23, form etching stopping layer 24.On etching stopping layer 24, be formed for second insulating barrier 25 of capacitor.Etching stopping layer 24 serves as etch stop layer and can comprise silicon nitride when etching second insulating barrier.Second insulating barrier 25 is provided at the three-dimensional structure that wherein forms memory node.Second insulating barrier 25 forms with the stacked structure that comprises ground floor 25A and second layer 25B.Ground floor 25A and second layer 25B comprise phosphosilicate glass (PSG) and tetraethyl orthosilicate (TEOS) respectively.
On second insulating barrier 25, form hard mask 26 subsequently.In the process that forms hard mask 26, on hard mask layer 26, form photoresist layer and form pattern by exposure and developing process.Utilize photoresist layer as etching mask, the etch hard mask layer is to form hard mask 26.Hard mask 26 is used to form the dark contact hole with high depth-width ratio.Hard mask 26 can comprise polysilicon.And the etching process that forms hard mask 26 can be active-ion-etch (RIE) process, this process about 20mTorr pressure and the source power of about 450W is provided and about 50W bias power under carry out.And this etching process uses by the hydrogen bromide (HBr) that mixes about 350sccm, the chlorine (Cl of about 10sccm 2) and the oxygen (O of about 3sccm 2) admixture of gas that obtains.
The stripping photoresist pattern, and utilize hard mask 26 to come etching part second insulating barrier 25 as etching mask, thus form the first perforate 27A with vertical configuration.More specifically, carrying out this etching process (hereinafter being called " first etching process ") makes second layer 25B by partially-etched and keep the part second layer 25B with predetermined thickness on ground floor 25A.
In first etching process, C xF yGas and O 2The admixture of gas of gas can be supplied in magnetic intensified response ion(ic) etching (MERIE) plasma source, and forming high-density plasma (HDP), thereby the sidewall of the first perforate 27A can be etched into and has vertical configuration.C xF yGas and O 2The flow-rate ratio of gas is about 1: 1.Particularly, C xF yThe flow of gas is higher than O 2The flow of gas.C xF yGas bag is drawn together and is selected from CF 4, C 4F 8, C 4F 6, C 5F 8And the combination in a kind of.For example, utilize admixture of gas about 15mTorr pressure and the source power of about 1300W is provided and about 1800W bias power under carry out first etching process, described admixture of gas is by the C of the about 34sccm of mixing 4F 6The O of gas, about 35sccm 2The CF of the about 14sccm of gas [FHFGD1] 4The Ar gas of gas and about 550sccm and obtaining.
With reference to Fig. 3 B, use wet etching equipment, utilize the wet-chemical reagent that is selected from buffer oxide etch agent (BOE) or hydrogen fluoride (HF) to carry out the isotropic etching process.As a result, the area of the first perforate 27A is extended.The first perforate 27A that enlarges is called " the second perforate 27B " hereinafter.The first perforate 27A is extended until size " W " [FHFGD2], and this makes and does not produce bridge between the capacitor.Particularly, size " W " can be equal to or greater than 10nm, and this size is the size that allows electric insulation.
Following table 1 illustrates the condition that is used to enlarge the various exemplary isotropic etchings of the first perforate 27A according to of the present invention.
Table 1
Chemical reagent PE-TEOS E/R 10nm TG 20nm TG 30nm TG 40nm TG 50nm TG 60nm TG
BOE with about 20: 1 dilution proportion 20A/s 10 seconds 20 seconds 30 seconds 40 seconds 50 seconds 60 seconds
BOE with about 300: 1 dilution proportion 1.25A/s 160 seconds 320 seconds 480 seconds 640 seconds 800 seconds 960 seconds
HF with about 100: 1 dilution proportion 4.5A/s 44 seconds 89 seconds 133 seconds 178 seconds 222 seconds 267 seconds
At this, " TG " and " PE-TEOS E/R " represents the etch-rate of the tetraethyl orthosilicate layer of target and plasma enhancing respectively.
For example, can utilize about 1 part of HF that the HF solution of the ratio dilution of about 100 parts of diluents was carried out the isotropic etching process about 170 seconds.According to this isotropic etching condition, the area of first perforate can increase about 40nm.
With reference to Fig. 3 C, on the hard mask 26 and the second perforate 27B, form bending resistance layer 28.Bending resistance layer 28 prevents bending and forms the thickness of about 100 -Yue 200 .Bending resistance layer 28 comprises and the lower electrode material identical materials, so bending resistance layer 28 can be used as bottom electrode.For example, bending resistance layer 28 comprises the material that is selected from titanium nitride (TiN), tungsten (W), ruthenium (Ru) and iridium (Ir).In the present embodiment, suppose that bending resistance layer 28 comprises TiN.
With reference to Fig. 3 D, etching bending resistance layer 28, thus on the sidewall of the second perforate 27B, form bending resistance spacer 28A.Utilize and pass through Cl 2The mixture of gas and Ar gas sprays into the high-density plasma that obtains in the plasma source of transformer coupled plasma (TCP)/inductively coupled plasma (ICP) and carries out the etching of bending resistance layer 28.Cl 2The mixing ratio of gas and Ar gas is about 1: about 1: 20 of 10-.And, under the bias power of about 10mTorr pressure, about 300W source power and about 100W, utilize to comprise the Ar gas of about 190sccm and the Cl of about 10sccm 2The admixture of gas of gas carries out the etching of bending resistance layer 28.To be higher than Cl 2The directivity that the ratio of gas provides Ar gas will improve high-density plasma makes that the part bending resistance layer 28 (being the TiN layer) in the bottom and the outside be positioned at the second perforate 27B is etched with the speed higher than the part bending resistance layer on the sidewall that is positioned at the second perforate 27B 28.
With reference to Fig. 3 E, utilize bending resistance spacer 28A and hard mask 26 as etching mask etching second insulating barrier 25 once more.Stop etching (hereinafter being called " second etching process ") to second insulating barrier 25 at etching stopping layer 24 places.Etching is positioned at the etching stopping layer 24 of second perforate 27B below to form the 3rd perforate 27C that exposes storage node contact plug 23.The 3rd perforate 27C is provided at the final three-dimensional structure that wherein forms bottom electrode.
Utilize and pass through C xF yGas and O 2The high-density plasma that the admixture of gas injection MERIE plasma source of gas obtains carries out second etching process.At this moment, owing to the high etch-selectivity of second insulating barrier 25 with respect to bending resistance spacer 28A, bending resistance spacer 28A is as the bending resistance layer.For example, described etching selectivity can be greater than about 200: 1.Therefore, can obtain having the vertical etching configuration of the 3rd perforate 27C of maximum verge of opening, this can prevent that perforate from forming inadequately.
C xF yGas can comprise and is selected from CF 4, C 4F 8, C 5F 8, CHF 3And CH 2F 2In a kind of, and induce and produce a large amount of CH xBase, thereby C xF yGas provides the high etch-selectivity with respect to second insulating barrier 25 of bending resistance spacer 28A, and for second insulating barrier 25 etch-rate faster.
Use C xF yThe etching of second insulating barrier 25 of gas utilizes following chemism.
CF：
CF2：
CF3：
For example, under the bias power of the source power of about 15mTorr, about 1700W and about 2300W, utilize the nubbin of admixture of gas etching second insulating barrier 25.This admixture of gas is by mixing the C of about 34sccm 4F 6The O of gas, about 31sccm 2The CF of gas, about 16sccm 4The Ar gas of gas and about 400sccm and obtaining.
With reference to Fig. 3 F, on the bottom of the second and the 3rd perforate 27B and 27C and sidewall, form aforementioned bottom electrode.Although not shown, also form dielectric layer and upper electrode layer.
Because bending resistance spacer 28A is formed on the sidewall of bottom electrode 29, therefore the nitride half spacer scheme that enlarges according to capacitor utilization of the present invention obtains.Following table 2 illustrates the comparing result of the characteristic of the characteristic of the capacitor that contrast made by the present embodiment and traditional capacitor.
Table 2
Conventional method The present embodiment
Distance (top view) between smallest capacitor 50nm 25nm
Distance (sectional view) between smallest capacitor 20nm 18nm
Flexibility The 13nm/ side The 1nm/ side
Capacitance raising degree AfF (A+10)fF
At this, the capacitance of " A " expression certain level.
As shown in table 2, for the capacitor top view of making according to the present embodiment, the minimum spacing between the capacitor can be decreased to about 25nm from 50nm.For the sectional view of described capacitor, the minimum spacing between the capacitor can be decreased to about 18nm from 20nm.And according to the present embodiment, flexibility can be decreased to about 1nm from 13nm, and capacitance can improve about 10fF.
According to another embodiment according to the invention, bending resistance layer 28 can comprise nitride based materials and can form the thickness of about 100 -Yue 200  on the second perforate 27B and hard mask 26.
When bending resistance layer 28 comprises nitride based materials, utilize and pass through C xF yGas, CH xF yGas and O 2The high-density plasma that the admixture of gas injection MERIE plasma source of gas obtains carries out the etching of bending resistance layer 28.For example, can under the source power of about 50mTorr pressure and about 500W, utilize by the Ar gas that mixes about 100sccm, the CHF of about 20sccm 3The O of gas and about 8sccm 2The admixture of gas of gas carries out the etching of bending resistance layer 28.As the result of this etching process, on the sidewall of the second perforate 27B, form the bending resistance spacer, and open the base section of the second perforate 27B.
According to exemplary of the present invention, when the dark contact hole that is used for the capacitor contact forms, form the bending resistance spacer.Except the capacitor contact, method according to the invention also can be applicable to form the dark contact hole of size greater than about 30,000 .For example, in the metal wire process, perforate is exactly a contact hole.
According to exemplary according to the invention, before finishing contact hole perforate or perforate, utilize wet etch process to enlarge contact hole or perforate.Because the bending resistance spacer is formed on the sidewall of described contact hole or perforate, therefore can realize the perforate configuration that maximum is opened.
Though described the present invention with respect to particular preferred embodiment, clearly those skilled in the art can carry out various changes and replacement to the present invention under the situation of the spirit and scope of the invention as defined by the appended claims.

Claims (44)

1. a method of making semiconductor device comprises;
On substrate, form insulating barrier;
The selective etch insulating barrier is to form first perforate;
Enlarge the area of first perforate;
On the sidewall of first perforate that enlarges, form the bending resistance spacer; And
The partial insulative layer of etch residue below first perforate that enlarges is to form second perforate.
2. the process of claim 1 wherein that forming insulating barrier comprises:
On substrate, form first insulating barrier;
On first insulating barrier, form etching stopping layer; With
Be formed for second insulating barrier of capacitor on etching stopping layer, described second insulating barrier comprises the 3rd insulating barrier and the 4th insulating barrier.
3. the method for claim 2 wherein forms first perforate and comprises:
On the 4th insulating barrier, form hard mask; With
Utilize hard mask as etching mask selective etch the 4th insulating barrier, make to keep part the 4th insulating barrier with predetermined thickness in the bottom of first perforate.
4. the method for claim 3 wherein forms first insulating barrier and comprises that formation has first insulating barrier of sandwich construction.
5. the method for claim 3 wherein forms the 3rd insulating barrier and comprises forming phosphosilicate glass (PSG) layer and forming the 4th insulating barrier and comprise and form tetraethyl orthosilicate (TEOS) layer.
6. the process of claim 1 wherein that forming first perforate comprises C xF y/ O 2Admixture of gas inject magnetic intensified response ion(ic) etching (MERIE) plasma source.
7. the method for claim 6, wherein C xF yGas and O 2The flow-rate ratio of gas is about 40: about 100: 1 of 1-.
8. the method for claim 7, wherein C xF yGas is selected from CF 4, C 4F 8, C 4F 6And C 5F 8
9. the process of claim 1 wherein that the area that enlarges first perforate comprises the isotropic etching method of using wet-chemical reagent that adopts.
10. the method for claim 9, wherein said wet-chemical reagent is one of buffer oxide etch agent (BOE) and hydrogen fluoride (HF).
11. the method for claim 9, the area that wherein enlarges first perforate comprise described enlarged areas to the width between adjacent first perforate is 10nm at least.
12. the process of claim 1 wherein that forming the bending resistance spacer comprises:
Forming the bending resistance layer in first perforate that enlarges and on the hard mask; With
Selective etch is positioned on the hard mask and the part bending resistance layer on the bottom of first perforate that enlarges, to form the bending resistance spacer on the sidewall of first perforate that enlarges.
13. the method for claim 12 wherein forms the bending resistance layer and comprises and form the layer comprise the same material that is used to form bottom electrode, so that the bending resistance layer prevents bending and plays the effect of bottom electrode.
14. the method for claim 13, wherein the bending resistance layer comprises and is selected from a kind of in titanium nitride (TiN), tungsten (W), ruthenium (Ru) and the iridium (Ir).
15. the method for claim 14, wherein selective etch bending resistance layer comprises and utilizing by with Cl 2/ Ar admixture of gas is with resulting high-density plasma in the plasma source of estimated rate injection transformer coupled plasma (TCP)/inductively coupled plasma (ICP).
16. the method for claim 15, wherein Cl 2Gas is about 1 with the predetermined mix of Ar gas than scope: about 1: 20 of 10-.
17. the method for claim 12, wherein the bending resistance layer comprises nitride based materials.
18. the method for claim 17, wherein etching bending resistance layer comprises and utilizing by with C xF y/ CH xF y/ O 2The admixture of gas of gas injects the resulting high-density plasma of MERIE plasma source.
19. the method for claim 12 wherein forms the bending resistance layer and comprises the bending resistance layer that forms about 100  of thickness-Yue 200 .
20. the method for claim 3 wherein forms second perforate and comprises:
Utilize bending resistance spacer and hard mask to come second insulating barrier of etching residue, to form the 3rd perforate as etching mask; With
Etching is positioned at the etching stopping layer of the 3rd perforate below, to form the 4th perforate that exposes predetermined part substrate.
21. the method for claim 20 wherein forms second perforate and comprises and utilize C xF y/ O 2The admixture of gas of gas and MERIE plasma source.
22. the method for claim 21, wherein C xF yGas is selected from CF 4, C 4F 8, C 5F 8, CHF 3And CH 2F 2
23. a method of making semiconductor device comprises:
On substrate, form insulating barrier;
The selective etch insulating barrier is to form first perforate;
Enlarge the area of first perforate;
On the sidewall of first perforate that enlarges, form the bending resistance spacer;
The partial insulative layer of etch residue below first perforate that enlarges is to form second perforate;
Form bottom electrode on the bottom of opening area and sidewall, each opening area comprises first perforate and second perforate of expansion; And
On bottom electrode, form dielectric layer and top electrode successively.
24. the method for claim 23, the method that wherein forms insulating barrier comprises:
On substrate, form first insulating barrier;
On first insulating barrier, form etching stopping layer; With
Be formed for second insulating barrier of capacitor on etching stopping layer, described second insulating barrier also comprises the 3rd insulating barrier and the 4th insulating barrier.
25. the method for claim 24 wherein forms first perforate and comprises:
On the 4th insulating barrier, form hard mask; With
Utilize hard mask as etching mask selective etch the 4th insulating barrier, make to keep part the 4th insulating barrier with predetermined thickness in the bottom of first perforate.
26. the method for claim 25 wherein forms first insulating barrier and comprises the formation sandwich construction.
27. the method for claim 25, wherein the 3rd insulating barrier comprises that phosphosilicate glass (PSG) and the 4th insulating barrier comprise tetraethyl orthosilicate (TEOS).
28. the method for claim 23 wherein forms first perforate and comprises C xF y/ O 2Admixture of gas inject magnetic intensified response ion(ic) etching (MERIE) plasma source.
29. the method for claim 28, wherein C xF yGas and O 2The flow-rate ratio of gas is about 40: about 100: 1 of 1-.
30. the method for claim 29, wherein C xF yGas is selected from CF 4, C 4F 8, C 4F 6And C 5F 8
31. the method for claim 23, the area that wherein enlarges first perforate comprises the isotropic etching process of using wet-chemical reagent that adopts.
32. the method for claim 31, wherein said wet-chemical reagent are one of buffer oxide etch agent (BOE) and hydrogen fluoride (HF).
33. the method for claim 31, the area that wherein enlarges first perforate comprise described enlarged areas to the width between adjacent first perforate is 10nm at least.
34. the method for claim 24 wherein forms the bending resistance spacer and comprises:
On first perforate that enlarges and hard mask, form the bending resistance layer; With
Selective etch is positioned at the part bending resistance layer on the bottom of first perforate of hard mask and expansion, to form the bending resistance spacer on the sidewall of first perforate that enlarges.
35. the method for claim 34 wherein forms the bending resistance layer and comprises and form the layer comprise the same material that is used to form bottom electrode, thereby the bending resistance layer prevents bending and plays the effect of bottom electrode.
36. the method for claim 35, wherein the bending resistance layer comprises the layer of the material that is selected from titanium nitride (TiN), tungsten (W), ruthenium (Ru) and iridium (Ir).
37. the method for claim 36, wherein selective etch bending resistance layer is to utilize to pass through Cl 2The admixture of gas of/Ar gas carries out with resulting high-density plasma in the plasma source of predetermined ratio injection transformer coupled plasma (TCP)/inductively coupled plasma (ICP).
38. the method for claim 37, wherein Cl 2Gas is about 1 with the predetermined mix of Ar gas than scope: about 1: 20 of 10-.
39. the method for claim 34, wherein the bending resistance layer comprises nitride based materials.
40. the method for claim 39, wherein selective etch bending resistance layer comprises and utilizing by with C xF y/ CH xF y/ O 2The admixture of gas of gas injects the resulting high-density plasma of MERLE plasma source.
41. the method for claim 34 wherein forms the bending resistance layer and comprises the layer that forms about 100  of thickness-Yue 200 .
42. the method for claim 25 wherein forms second perforate and comprises:
Utilize bending resistance spacer and hard mask to come second insulating barrier of etching residue, to form the 3rd perforate as etching mask; With
Etching is positioned at the etching stopping layer of the 3rd perforate below, to form the 4th perforate that exposes predetermined part substrate.
43. the method for claim 42, wherein forming second perforate is to utilize the C that is positioned at MERIE plasma source place xF y/ O 2The admixture of gas of gas carries out.
44. the method for claim 43, wherein C xF yGas is selected from CF 4, C 4F 8, C 5F 8, CHF 3And CH 2F 2
CNB2005100975337A 2005-06-30 2005-12-30 Method for fabricating semiconductor device with deep opening Expired - Fee Related CN100472732C (en)

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
CN103094091A (en) * 2011-11-02 2013-05-08 中芯国际集成电路制造(上海)有限公司 Etching method of semi-conductor device
CN113053805A (en) * 2021-03-11 2021-06-29 长鑫存储技术有限公司 Semiconductor structure forming method and semiconductor structure

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CN116403970B (en) * 2023-06-09 2023-08-25 合肥晶合集成电路股份有限公司 Semiconductor device and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094091A (en) * 2011-11-02 2013-05-08 中芯国际集成电路制造(上海)有限公司 Etching method of semi-conductor device
CN103094091B (en) * 2011-11-02 2016-03-30 中芯国际集成电路制造(上海)有限公司 The lithographic method of semiconductor device
CN113053805A (en) * 2021-03-11 2021-06-29 长鑫存储技术有限公司 Semiconductor structure forming method and semiconductor structure
CN113053805B (en) * 2021-03-11 2022-06-10 长鑫存储技术有限公司 Semiconductor structure forming method and semiconductor structure

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