CN1794455A - Method for forming storage node of capacitor in semiconductor device - Google Patents

Method for forming storage node of capacitor in semiconductor device Download PDF

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Publication number
CN1794455A
CN1794455A CN200510117259.5A CN200510117259A CN1794455A CN 1794455 A CN1794455 A CN 1794455A CN 200510117259 A CN200510117259 A CN 200510117259A CN 1794455 A CN1794455 A CN 1794455A
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Prior art keywords
insulating barrier
storage node
layer
contact hole
etching
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CN200510117259.5A
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CN100423269C (en
Inventor
宣俊劦
李圣权
赵诚允
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Covenson wisdom N.B.868 company
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact plugs filled into the first contact holes; forming a second insulation layer with a different etch rate from the first insulation layer over the storage-node contact plugs; forming a third insulation layer on the second insulation layer; sequentially etching the third insulation layer and the second insulation layer to form a plurality of second contact holes exposing the storage-node contact plugs; and forming the storage node on each of the second contact holes.

Description

In semiconductor device, form the method for storage node of capacitor
Technical field
The present invention relates to a kind of method that is used for forming storage node of capacitor at semiconductor device; And more specifically say, relate to a kind of method that is used for forming capacitor storage node in dynamic random access memory means.
Background technology
Along with the height of semiconductor device is integrated, unit cell (unit cell) size reduces gradually.Especially in dynamic random access memory (DRAM) device, unit cell comprises a transistor and a capacitor.Therefore, along with the increase of the integrated scale of semiconductor device, the control correlated process is much more difficult.
Hereinafter describe and be used for forming the method for storage node of capacitor and storing the relevant possible problem of formation method therewith at the DRAM device with reference to 1A figure to the 1C figure.
With reference to 1A figure, interlayer insulating film 11 forms on the substrate 10 that provides various device elements, follow, by photoetching process in addition patterning to form a plurality of contact holes (not shown).In contact hole, sequentially form insulating barrier and polysilicon layer, then, polysilicon layer and insulating barrier are carried out chemico-mechanical polishing (CMP) process, a storage node contact plug (storage node contact plug) 13 more than forming the sept 12 on the sidewall of contact hole thus and being filled in the contact hole.Then, on the above board structure that obtains, sequentially form nitride layer 14, oxide skin(coating) 15 and hard mask layer 16.
With reference to 1B figure, although not shown, photoresist layer forms on hard mask layer 16, then utilizes mask to expose and developing process, forms the photoresist pattern thus.Then, utilize the photoresist pattern hard mask layer 16 to be carried out etching as etching mask.After to hard mask layer 16 etchings, form hard mask pattern 16A.Utilize hard mask pattern 16A to come etching oxide layer 15 then, and this etching stop at nitride layer 14 as etching barrier (etchbarrier).In other words, nitride layer 14 serves as etching stopping layer.After this etching, form 14 more than first contact holes 17 of exposure nitride layer to oxide skin(coating) 15.
With reference to 1C figure, nitride etching layer 14 exposes 13 more than second contact hole 17A of storage node contact plug to form.Although not shown, storage node layer, dielectric layer (dielectric layer) and upper electrode layer sequentially form on the second contact hole 17A, carry out the CMP process then thereon, form capacitor thus.
But, shown in 1C figure, may have the generation of misalignment between the second contact hole 17A and the storage node contact plug 13.Therefore, when nitride etching layer 14, sept 12 is also etched, and the sidewall at interlayer insulating film 11 produces crack (crevice) A thus.After, when forming described storage node layer, dielectric layer and upper electrode layer, the ladder coverage property of storage node layer (stepcoverage characteristic) is in the regional variation that produces crack A.Therefore, the leakage current of capacitor increases, thereby causes the defective in the semiconductor device.
Summary of the invention
Therefore, the present invention's purpose provides a kind of method that is used for forming at semiconductor device storage node of capacitor, it can prevent the degradation of equipment energy characteristic by the ladder coverage property that improves memory node, and described ladder coverage property worsens when the sept of the barrier that is used as storage node contact plug damages usually.
According to one of the present invention aspect, a kind of method that is used for forming at semiconductor device storage node of capacitor is provided, comprise the steps: on substrate, to form interlayer insulating film; This interlayer insulating film of etching is to form a plurality of first contact holes; On the sidewall of first contact hole, form first insulating barrier; A storage node contact plug more than formation is filled in aforementioned first contact hole; On storage node contact plug, form second insulating barrier with the rate of etch different (etch rate) with first insulating barrier; On second insulating barrier, form the 3rd insulating barrier; The 3rd insulating barrier of etching sequentially and second insulating barrier be second contact hole more than formation exposure storage node contact plug; And on each second contact hole, form memory node.
According to another aspect of the present invention, a kind of method that is used for forming at semiconductor device storage node of capacitor is provided, comprise the steps: that each sequentially forms first insulating barrier and second insulating barrier with different etch on substrate; Formation runs through first contact hole more than first and second insulating barrier; Same etch rate with second insulating barrier on the sidewall of first contact hole forms sept; A storage node contact plug more than formation is filled in first contact hole; Same etch rate with second insulating barrier on storage node contact plug forms etching stopping layer; On etching stopping layer, form sacrificial oxide layer; Sequentially etch sacrificial oxide skin(coating) and etching stopping layer are form to expose second contact hole more than the storage node contact plug; And on each second contact hole, form memory node.
According to another aspect of the present invention, a kind of method that is used for forming at semiconductor device storage node of capacitor is provided, comprise the steps: on substrate, to form first insulating barrier; Formation runs through first contact hole more than first insulating barrier; On the sidewall of first contact hole, form sept with the rate of etch different with first insulating barrier; A storage node contact plug more than formation is filled in first contact hole; Identical rate of etch with sept on storage node contact plug forms etching stopping layer; On etching stopping layer, form sacrificial oxide layer; Etching prescription (etchrecipe) by oxide etching is etch sacrificial oxide skin(coating) and etching stopping layer sequentially, exposes second contact hole more than the storage node contact plug thereby form; And on each second contact hole, form memory node.
According to another aspect of the present invention, a kind of method that is used for forming at semiconductor device storage node of capacitor is provided, comprise the steps: on substrate, to form first insulating barrier; Formation runs through first contact hole more than first insulating barrier; On the sidewall of first contact hole, form sept with the rate of etch different with first insulating barrier; Form a plurality of storage node contact plug, make described storage node contact plug be filled in first contact hole, and it highly is higher than sept; Same etch rate with first insulating barrier on storage node contact plug forms second insulating barrier; Second insulating barrier is planarized to the par of storage node contact plug; Same etch rate with sept on storage node contact plug forms etching stopping layer; On etching stopping layer, form sacrificial oxide layer; Carry out etching process, it provides the low etching selectivity (etchselectivity) with respect to the sept of storage node contact plug, second contact hole more than formation exposure storage node contact plug; And on each second contact hole, form memory node.
According to the present invention's other aspect, a kind of method that is used for forming at semiconductor device storage node of capacitor is provided, comprise the steps: on substrate, to form interlayer insulating film; The etching interlayer insulating film is to form a plurality of first contact holes; On the sidewall of first contact hole, form sept; Formation is filled in the interior storage node contact plug of first contact hole; On storage node contact plug, form etching stopping layer; On etching stopping layer, form nitride layer; Nitride etching layer and etching stopping layer be second contact hole more than formation exposure storage node contact plug; By utilizing different etching selectivities between interlayer insulating film and the sept optionally to cave in through the predetermined portions of the interlayer insulating film of second contact holes exposing; And on each second contact hole, form memory node.
Description of drawings
According to the following description that provides in conjunction with the accompanying drawings to preferred embodiment, address other purpose and feature on the present invention and will be understood preferably, in these accompanying drawings:
1A figure to the 1C figure is for illustrating the sectional drawing that is used for forming at semiconductor device the conventional method of storage node of capacitor;
2A figure to the 2E figure is for illustrating the sectional drawing that is used for forming at semiconductor device the method for storage node of capacitor according to first embodiment of the invention;
3A figure to the 3G figure is for illustrating the sectional drawing that is used for forming at semiconductor device the method for storage node of capacitor according to second embodiment of the invention;
4A figure to the 4G figure is for illustrating the sectional drawing that is used for forming at semiconductor device the method for storage node of capacitor according to third embodiment of the invention;
5A figure to the 5D figure is for illustrating the sectional drawing that is used for forming at semiconductor device the method for storage node of capacitor according to fourth embodiment of the invention;
6A figure to the 6B figure is for illustrating the sectional drawing that is used for forming at semiconductor device the method for storage node of capacitor according to fifth embodiment of the invention.
Embodiment
Hereinafter describe the method that is used for forming storage node of capacitor of preferred embodiment with reference to the accompanying drawings in detail according to the present invention at semiconductor device.
2A figure to the 2E figure is for illustrating the sectional drawing that is used for forming at semiconductor device the method for capacitor storage node according to first embodiment of the invention.
With reference to 2A figure, sequentially form first interlayer insulating film 111 and second interlayer insulating film 112 on the substrate 110 partly finishing.First interlayer insulating film 111 and second interlayer insulating film 112 have the rate of etch of difference.First interlayer insulating film 111 and second interlayer insulating film 112 use oxide and nitride to form respectively.Although not shown, partly finish substrate 110 and comprise device isolated area, word line and bit line.
Etching first interlayer insulating film 111 and second interlayer insulating film 112 are to form first contact hole (not shown) that exposes the reservations branch of partly finishing substrate 110, and then, based on material with rate of etch identical with second interlayer insulating film 112, for example the spacer layer of nitride forms on the second etched interlayer insulating film 112 and first contact hole, then, etched on the sidewall of first contact hole, to form sept 113.
Next, on the above board structure that obtains, form polysilicon layer, in this polysilicon layer is embedded in first contact hole, then polysilicon layer is carried out planarization process, form a plurality of contact plugs 114 thus.Here, contact plug 114 serves as storage node contact plug.
With reference to 2B figure, on contact plug 114, form etching stopping layer 115.Etching stopping layer 115 stops to be used to form the etching process of storage node contact hole by the etching selectivity (etchselectivity) of control sacrificial oxide layer 116 (with reference to 2C figure).At this moment, etching stopping layer 115 forms by utilizing the nitride layer that obtains via using plasma enhancing chemical vapour deposition (CVD) (PECVD) method or Low Pressure Chemical Vapor Deposition (LPCVD) method.
With reference to 2C figure, aforementioned sacrificial oxide layer 116 is formed on the etching stopping layer 115.Sacrificial oxide layer 116 highly determine capacitor the height.Also may with comprise phosphosilicate glass (phosphosilicate glass) (PSG) and tetraethyl orthosilicate (tetraethylorthosilicate) stacked structure (TEOS) form sacrificial oxide layer 116.
With reference to 2D figure, utilize photoresist pattern 117 to come etch sacrificial oxide skin(coating) 116 as etching mask, form a plurality of second contact holes 118 with top at etching stopping layer 115, open the zone that will form memory node thus.Second contact hole 118 serves as storage node contact hole.
With reference to 2E figure, use etched sacrificial oxide layer 116 etching stopping layer 115 to be carried out etching then as etching mask, form 114 more than the 3rd contact hole 118A of exposure contact plug thus.Because second interlayer insulating film 112 particularly is a nitride based on the material that the rate of etch identical with sept 113 is provided, might prevent that sept 113 is by over etching.Therefore, the 3rd contact hole 118A can comparatively stably form, and can improve the ladder coverage property of the storage node materials that will form subsequently thus.
In other words, first embodiment according to the present invention, the insulating barrier that comprises contact plug forms with the stacked structure that comprises first interlayer insulating film and second interlayer insulating film, described first and second interlayer insulating film respectively has the rate of etch of difference, and the sidewall spacer of contact plug forms by the same material that use has the rate of etch identical with second interlayer insulating film.As a result, forming second contact hole, might prevent during the storage node contact hole that promptly sidewall spacer is by over etching.Therefore, the generation that produces the crack in the typical observed sept can't occur, thereby has improved the ladder coverage property of storage node materials.
3A figure to the 3G figure is for illustrating the sectional drawing that is used for forming at semiconductor device the method for capacitor storage node according to second embodiment of the invention.
With reference to 3A figure, first interlayer insulating film 211 is formed on partly to be finished on the substrate 210, etchedly then exposes first contact hole (not shown) more than the presumptive area of partly finishing substrate 210 to form.Although not shown, partly finish substrate 210 and comprise device isolated area, word line and bit line.First interlayer insulating film 211 is an oxide skin(coating).
Next, based on the material with rate of etch different with first interlayer insulating film 211, for example the spacer layer of nitride is formed on etched first interlayer insulating film 211 and first contact hole.Then, the spacer etch layer is to form sept 212 on the sidewall of first contact hole.
Afterwards, on the whole surface of the above board structure that obtains, form the contact plug material, be filled the contact plug material, then, the contact plug material is carried out planarization process to form contact plug 213 up to first contact hole.Here, contact plug 213 is by using polysilicon layer and form and serving as storage node contact plug.
With reference to 3B figure, on the contact plug 213 and first interlayer insulating film 211, form second interlayer insulating film 214.Second interlayer insulating film 214 forms by using oxide.
With reference to 3C figure, on second interlayer insulating film 214, form etching stopping layer 215.Etching stopping layer 215 is based on the material with rate of etch identical with sept 212, and particularly, etching stopping layer 215 etching selectivity that is used for the sacrificial oxide layer 216 (scheming with reference to 3D) that will form subsequently by control stops to be used to form the etching process of storage node contact hole subsequently.More specifically, etching stopping layer 215 forms by using via the nitride layer that adopts PECVD method or LPCVD method to obtain.
With reference to 3D figure, aforementioned sacrificial oxide layer 216 is formed on the etching stopping layer 215.Sacrificial oxide layer 216 highly determine capacitor the height.Also might form sacrificial oxide layer 216 with the stacked structure that comprises PSG and TEOS.
With reference to 3E figure, on sacrificial oxide layer 216, form photoresist pattern 217.Utilize photoresist pattern 217 sacrificial oxide layer 216 to be carried out etching, form a plurality of second contact holes 218 thus at the top of etching stopping layer 215 as etching mask.Second contact hole 218 is opened the zone that will form memory node.
With reference to 3F figure, utilization is etched with formation a plurality of three contact hole 218As etching mask to etching stopping layer 215 through the sacrificial oxide layer 216 of etching, it exposes the part of second interlayer insulating film 214, more specifically, will form the zone of memory node.
With reference to 3G figure, etching second interlayer insulating film 214 is to expose contact plug 213, so that connect memory node and contact plug 213.After to 214 etchings of second interlayer insulating film, form a plurality of the 4th contact hole 218B.Therefore the target that is used to form the etching process of the 4th contact hole 218B is the etching oxide layer, and might prevent that sept 212 based on nitride is by over etching.Therefore, might more stably form the 4th contact hole 218B, and therefore might improve the ladder coverage property of the storage node materials that will form subsequently.
In other words, according to the present invention's second embodiment, be used to form the contact hole that connects contact plug and memory node, promptly the etching process of the 4th contact hole is applied to the oxide skin(coating) of etching as second interlayer insulating film.Therefore, the sidewall spacer of contact plug does not have the generation of over etching.Therefore, during forming the 4th contact hole, in sidewall spacer, can not produce the crack.As the result of this effect, can improve the ladder coverage property of storage node materials.
4A figure to the 4G figure is for illustrating the sectional drawing that is used for forming at semiconductor device the method for capacitor storage node according to third embodiment of the invention.
With reference to 4A figure, first interlayer insulating film 311 forms partly finishing on the substrate 310, follows etchedly to expose first contact hole (not shown) more than the predetermined portions of partly finishing substrate 310 to form.Although not shown, partly finish substrate 310 and comprise device isolated area, word line and bit line.First interlayer insulating film 311 forms by using oxide.
Next, based on the material with rate of etch different with first interlayer insulating film 311, for example the spacer layer of nitride is formed on first contact hole and first interlayer insulating film 311.Then, the spacer etch layer is to form sept 312 on the sidewall of first contact hole.
Afterwards, on the whole surface of the above board structure that obtains, form the contact plug material, be filled the contact plug material, a contact plug 313 more than then etching contact plug material is filled in first contact hole with formation up to first contact hole.At this moment, etching process is proceeded to project upwards and each contact plug 313 is had be higher than height of first interlayer insulating film 311 up to contact plug 313.Contact plug 313 is based on polysilicon and serve as storage node contact plug.
With reference to 4B figure, second interlayer insulating film 314 forms on described outstanding contact plug 313, then experiences chemico-mechanical polishing (CMP) process so that planarization second interlayer insulating film 314.Specifically, this planarization process proceeds to reach up to second interlayer insulating film 314 the similar face level of each contact plug 313.Second interlayer insulating film 314 is an oxide skin(coating).
With reference to 4C figure, on second interlayer insulating film 314 and contact plug 313, form etching stopping layer 315.Here, etching stopping layer 315 is used to stop to form the etching process of second contact hole subsequently, and this second contact hole is used for memory node.The formation of second contact hole will be described in detail in 4E figure.Particularly, etching stopping layer 315 stops etching by the etching selectivity of control sacrificial oxide layer, and described sacrificial oxide layer will form after forming etching stopping layer 315.The formation of sacrificial oxide layer will be described in detail in 4D figure.At this moment, etching stopping layer 315 uses nitride to form by adopting PECVD method or LPCVD method.
With reference to 4D figure, on etching stopping layer 315, form aforementioned sacrificial oxide layer 316.Sacrificial oxide layer 316 highly determine capacitor the height.In addition, also might form sacrificial oxide layer 316 with the stacked structure that comprises PSG and TEOS.
With reference to 4E figure, on sacrificial oxide layer 316, form predetermined photoresist pattern 317.As etching mask sacrificial oxide layer 316 is carried out etching with this photoresist pattern 317, on etching stopping layer 315, form the second aforementioned contact hole 318 thus.Second contact hole 318, promptly storage node contact hole is opened the zone that will form memory node.
With reference to 4F figure, utilize etched sacrificial oxide layer 316 etching stopping layer 315 to be carried out etching as etching mask, form a plurality of the 3rd contact hole 318A thus, it exposes second interlayer insulating film 314 that wherein limits the memory node zone.
With reference to 4G figure, the predetermined portions of etching second interlayer insulating film 314 to be forming a plurality of the 4th contact hole 318B, and it exposes contact plug 313 and is connected so that between contact plug 313 and the memory node each to be provided.Particularly, by with respect to the etching selectivity that reduces nitride with the contact plug 313 of polysilicon formation, be used to form the etching process employing isotropic etching of the 4th contact hole 318B.So the isotropic etching process makes and might prevent that sept 312 based on nitride is by over etching.So the 4th contact hole 318B can stably form, improved the ladder coverage property of the storage node materials that will form subsequently thus.
In other words, according to the present invention's the 3rd embodiment, during being formed for connecting the contact hole of storage node contact plug and memory node, adopt isotropic etching by the etching selectivity that reduces with respect to storage node contact plug based on the sept of nitride.As the result of isotropic etching, can stop over etching based on the sept of nitride.Therefore, in sept, can not produce the crack, thereby improve the ladder coverage property of storage node materials.
5A figure to the 5D figure is for illustrating the sectional drawing that is used for forming at semiconductor device the method for capacitor storage node according to fourth embodiment of the invention.
With reference to 5A figure, partly finish formation interlayer insulating film 511 on the substrate 510.Although not shown, partly finish substrate 510 comprise word line, bit line, interface, unit contact plug, based on the insulating barrier of oxide, and based on the etching stopping layer of nitride.In addition, be formed on the individual layer that the interlayer insulating film of partly finishing on the substrate 510 511 is based on the material of oxide, described material comprises high density plasma oxide, boron phosphorus silicate glass (borophosphosilicate glass) (BPSG), PSG, TEOS, the silicate glass of doping (undoped silicate glass) is not (USG), fluorinated silicate glass (fluorinated silicate glass) (FSG), carbon-doped oxide (carbon dopedoxide) (CDO), and organic silicate glass (organosilicate glass) (OSG).
Then, interlayer insulating film 511 experience CMP processes are so that planarization.Although not shown, form on interlayer insulating film 511 based on the hard mask layer of nitride, and be patterned into hard mask subsequently.Utilize this hard mask, interlayer insulating film 511 is etched with form exposes individual first contact hole (not shown) more than the unit contact plug that forms by polysilicon.
Afterwards, the hard mask of removing based on nitride also forms first insulating barrier 512 that is used as barrier layer subsequently on first contact hole.At this moment, first insulating barrier 512 is based on the layer of oxide, and it comprises aluminium oxide (Al 2O 3), PE-TEOS oxide, ALD oxide, and tantalum oxide (Ta 2O 5One of), and have the thickness of scope from approximate 50 to approximate 500 .The storage node contact plug material that comprises one of polysilicon and tungsten is filled first contact hole, and carry out CMP process or (etch-back) process of eat-backing be embedded in first contact hole with formation more than a storage node contact plug 513 and at segregate first interlayer insulating film 512 of the sidewall of first contact hole.In other words, first interlayer insulating film 512 of this isolation is as sept.
After forming storage node contact plug 513, on the whole surface of the above board structure that obtains, form second insulating barrier 514.Second insulating barrier 514 uses the material with etching selectivity different with first insulating barrier 512 to form.More specifically, second insulating barrier is based on the layer of nitride, and it comprises one of PECVD nitride, ALD nitride, low pressure nitride or the like, and has the thickness of scope from approximate 100 to approximate 1,000 .
With reference to 5B figure, on second interlayer insulating film 514, be formed for the 3rd insulating barrier 515 of memory node pattern.At this moment, the 3rd interlayer insulating film 515 forms with individual layer or its stack layer of the same material that is used to form interlayer insulating film 511.The example of this material is PE-TEOS oxide, LP-TEOS oxide, PSG oxide, BPSG oxide, ALD oxide etc.
The hard mask layer 516 that comprises polysilicon or nitride is formed on the top at the 3rd insulating barrier 515.Particularly, hard mask layer 516 can form with the individual layer of a material or with its stack layer, and described material is selected from the group of being made up of polysilicon, silicon nitride (SiN) and tungsten (W).Hard mask layer 516 has the thickness of scope from approximate 500 to approximate 5,000 .When the total height of the storage node contact hole structure of being wanted was lower than approximate 15,000 , hard mask layer 516 was unnecessary.
With reference to 5C figure, although not shown, photoresist layer forms on hard mask layer 516, uses mask to pass through in addition patterning of exposure and developing process then, thus formation photoresist pattern.Then, utilize the photoresist pattern that hard mask layer 516 is carried out etching, form hard mask pattern 516A thus.Then, remove the photoresist pattern by stripping process.
By utilizing hard mask pattern 516A, the 3rd insulating barrier 515 is etched with formation exposes 514 more than second contact holes 517 of second insulating barrier as etching mask.At this moment, the etching process that is used to form second contact hole 517 uses from comprising C 4F 6, C 5F 8And C 3F 8Group in the gas selected as main etching gas and from comprising Ar, He, Xe and O 2Group in the another kind of gas selected gas as a supplement.In addition, second insulating barrier 514 is used to form the etching stopping layer of the etching process of second contact hole 517.
With reference to 5D figure, the predetermined portions of second insulating barrier 514 by 517 exposures of second contact hole is etched under the specified conditions of the high etch-selectivity between second insulating barrier 514 and first insulating barrier 512.At this moment, CHF is used in the etching of second insulating barrier 514 3Gas is as main etching gas and use from comprising O 2, Ar, CF 4And the another kind of gas of selecting in the group of combination gas as a supplement.By this etching process, form 513 more than the 3rd contact hole 517A of exposure storage node contact plug.
Although not shown, on the 3rd contact hole 517A, sequentially form storage node layer and dielectric layer, then on dielectric layer, form upper electrode layer, make this upper electrode layer fill the 3rd contact hole 517A.Then it is carried out the CMP process to form capacitor.
6A figure and 6B figure are for illustrating the sectional drawing that is used for forming at semiconductor device the method for capacitor storage node according to fifth embodiment of the invention.
With reference to 6A figure, partly finish formation interlayer insulating film 611 on the substrate 610.Although not shown, partly finish substrate 610 comprise word line, bit line, interface, unit contact plug, based on the insulating barrier of oxide, and based on the etching stopping layer of nitride.Interlayer insulating film 611 is the individual layer based on the material of oxide, and this material is selected from the group that comprises HDP oxide, BPSG, PSG, TEOS, USG, FSG, CDO and OSG.
Then, by the CMP process interlayer insulating film 611 is carried out planarization.Then, although not shown, on interlayer insulating film 611, form hard mask based on nitride by adopting photoetching process to obtain.Then, use hard mask interlayer insulating film 611 to be carried out etching, form first contact hole (not shown) more than the exposure unit contact plug (not shown) thus as etching mask.
Remove hard mask then, and on first contact hole, form spacer layer 612.Spacer layer 612 as barrier layer uses nitride to form.Then, the storage node contact plug material as polysilicon or tungsten, is filled in first contact hole.This storage node contact plug material then experience CMP process or etch back process be filled in first contact hole (not shown) with formation more than a storage node contact plug 613.
After forming storage node contact plug 613, on the whole surface of the above board structure that obtains, form nitride layer 614.The insulating barrier 615 that is used for the memory node pattern is formed on nitride layer 614.At this moment, insulating barrier 615 uses the material identical with formation interlayer insulating film 611 to form with individual layer or with stack layer.
Then, on insulating barrier 615, form hard mask pattern 616A.Although not shown, this hard mask pattern 616A is by carrying out photoetching process and obtain being formed on hard mask layer on the insulating barrier 615.Use hard mask pattern 616A as etching stopping layer insulating barrier 615 to be carried out etching then as etching mask and nitride layer 614.Nitride layer 614 is etched with formation exposes 613 more than second contact hole 617A of storage node contact plug.
With reference to 6B figure, under the target that optionally makes by the predetermined portions depression of the interlayer insulating film 611 of the second contact hole 617A exposure, carry out another etching process.At this moment, preferably, by adopting high-density plasma to carry out, described prescription allows the spacer layer 612 based on nitride that is flattened to described another etching process under a prescription, be that sept is not etched, and be selectively etched based on the interlayer insulating film 611 of oxide.For example, by using C 4F 6/ C 3F 8/ O 2The mist of/Ar carries out the high-density plasma etching process to produce a large amount of polymer (polymer).At this moment, C 4F 6Gas, C 3F 8Gas, O 2Gas and Ar gas preferably mix with 29 to 14 to 26 to 400 ratio respectively.In addition, the ratio when supposition Ar gas is when being similar to 100%, to comprise C 4F 6Gas, C 3F 8Gas and O 2Every kind of the remaining gas of gas has and is arranged on approximate 4% to approximate 10% ratio.In addition, from approximate 1,000W is to approximate 2 by the supply scope for the high-density plasma etching process, and 000W is more preferably approximate 1, and the power of 500W, and scope is from approximate 1,500W be to approximate 2,600W, and more preferably 2, the bias power of 100W is implemented.At this moment, the scope of the constant pressure of high-density plasma Etaching device (chamberpressure) is to being similar to 20mtorr, more preferably approximate 17mtorr from approximate 15mtorr.Under this kind etching prescription, the part of interlayer insulating film 611 can optionally be caved in, and makes the spacer layer 612 based on nitride simultaneously, i.e. the loss of sept is minimum.The high-density plasma etching process can be carried out with the etching process that is used to form the second contact hole 617A on the spot.
In addition, described another etching process can utilize C by use 2F 6/ O 2The high-density plasma of mist carry out.Particularly, as supposition C 2F 6When the mixing ratio of gas is approximately 100sccm, O 2Gas mixes with the ratio of scope from approximate 1sccm to approximate 4sccm.The high-density plasma etching process in scope the pressure from approximate 1mtorr to approximate 10mtorr together with supply with approximate 300W to the power of approximate 500W and approximate 200W to approximate 400W substrate bias power and carry out.
Although not shown, on the second contact hole 617A, sequentially form storage node layer and dielectric layer, then on dielectric layer, form upper electrode layer, make this upper electrode layer fill the second contact hole 617A.Carry out the CMP process then thereon to form capacitor.
According to the present invention's first to the 5th embodiment, the generation in crack in the sept that several approach prevent that the over etching because of sept from causing is arranged.
At first, the insulating barrier that comprises storage node contact plug forms with first interlayer insulating film that respectively has different etch and the stacked structure of second interlayer insulating film, and the sept on the sidewall of storage node contact plug uses the material with rate of etch identical with second interlayer insulating film to form.Therefore, during being used to form the subsequent process of storage node contact hole, might prevent that sept is by over etching.
The second, the etching process that is used to form the storage node contact hole that connects storage node contact plug and memory node carries out under the specific prescription that provides with respect to the special etch selectivity of oxide.Therefore, might prevent that sept based on nitride is by over etching.
The 3rd, the etching process that is used to form storage node contact hole is by reducing nitride with respect to storage node contact plug, and promptly the etching selectivity of sept adopts the isotropic etching process and carries out.On the basis of isotropic etching, might prevent that sept is by over etching.
The 4th, for the formation of memory node, utilize a kind of material to form as the sept of the barrier layer of storage node contact plug, this material provide be formed on sept and storage node contact plug on and as the different etching selectivity of insulating barrier of etching stopping layer.By being that sept and insulating barrier use different materials, might prevent that sept is simultaneously etched with insulating barrier during memory node forms.
At last, for the formation of memory node, insulating barrier forms on the sidewall of the sept of the barrier layer that is used as storage node contact plug, caves in desired depth under the special etch prescription then.By this special etch prescription, might improve the ladder coverage property of storage node materials.
As above-mentioned, this effect that prevents from sept to produce the crack can further obtain the improvement to the ladder coverage property of storage node materials.Therefore, might prevent the degradation of equipment energy characteristic.Particularly, might reduce the leakage current of capacitor, make the defective in the semiconductor device minimum thus.Minimum defective produces the high production that further obtains semiconductor device.
The application comprise relevant respectively on December 20th, 2004, on December 22nd, 2004, and on December 27th, 2004 to the theme of korean patent application KR2004-0108694 number of Korean Patent office proposition, KR 2004-0110083 number and KR 2004-0112821 number, the full content of these applications is hereby incorporated by.
Though described the present invention at some preferred embodiment, those skilled in the art be it is evident that, can as spirit of the present invention that following claim limited and scope in make various changes and modification.
[main symbol description]
110 half completing substrates
111 first interlayer insulating films
112 second interlayer insulating films
113 septs
114 contact plugs
115 etching stopping layers
116 sacrificial oxide layer
117 photoresist patterns
118 contact holes.

Claims (26)

1. a method that is used for forming at semiconductor device storage node of capacitor comprises the steps:
On substrate, form interlayer insulating film;
The described interlayer insulating film of etching is to form a plurality of first contact holes;
On the sidewall of first contact hole, form first insulating barrier;
A storage node contact plug more than formation is filled in first contact hole;
On described storage node contact plug, form second insulating barrier with the rate of etch different with first insulating barrier;
On second insulating barrier, form the 3rd insulating barrier;
The 3rd insulating barrier of etching sequentially and second insulating barrier be second contact hole more than the described storage node contact plug of formation exposure; And
On each second contact hole, form described memory node.
2. as the method for claim 1, wherein said first insulating barrier is from by aluminium oxide (Al 2O 3) layer, plasma strengthen tetraethyl orthosilicate (PE-TEOS) oxide skin(coating), ald (ALD) oxide skin(coating), and tantalum oxide (Ta 2O 5) select in the group formed of layer one.
3. as the method for claim 1, wherein said second insulating barrier is one that selects from the group of being made up of plasma enhanced chemical vapor deposition (PE-CVD) nitride layer, ALD nitride layer and low pressure (LP) nitride layer.
4. as the method for claim 1, wherein said the 3rd insulating barrier forms with one of the individual layer of the same material that is used to form interlayer insulating film or its stack layer.
5. as the method for claim 1, wherein said the 3rd insulating barrier forms with one of the individual layer that comprises a material and stack layer, described material from by PE-TEOS oxide, LP-TEOS oxide, phosphosilicate glass (PSG) oxide, boron phosphorus silicate glass (BPSG) oxide, and the group formed of ALD oxide select.
6. as the method for claim 1, wherein said the 3rd insulating barrier is by adopting from by C 4F 6, C 5F 8And C 3F 8The gas of selecting in the group of forming is as main etching gas and from by Ar, He, Xe and O 2The another kind of gas of selecting in the group of forming gas as a supplement comes etched.
7. as the method for claim 1, wherein second insulating barrier is by adopting CHF 3Gas is as main etching gas and from by O 2, Ar, CF 4And gas is next etched as a supplement to make up the another kind of gas of selecting in the group of forming.
8. as the method for claim 1, further comprise step: before forming second contact hole, on the 3rd insulating barrier, form hard mask layer and this hard mask layer of patterning.
9. as the method for claim 8, wherein said hard mask layer forms by using from the material of selecting by the polysilicon of impurity, the group that polysilicon, silicon nitride, tungsten and the combination thereof of impurity are not formed.
10. as the method for claim 9, wherein said hard mask layer has the thickness of scope from approximate 500 to approximate 5,000 .
11. a method that is used for forming at semiconductor device storage node of capacitor comprises the steps:
Each sequentially forms first insulating barrier and second insulating barrier with different etch on substrate;
Formation runs through first contact hole more than first and second insulating barrier;
Same etch rate with second insulating barrier on the sidewall of first contact hole forms sept;
A storage node contact plug more than formation is filled in first contact hole;
Same etch rate with second insulating barrier on described storage node contact plug forms etching stopping layer;
On described etching stopping layer, form sacrificial oxide layer;
Described sacrificial oxide layer of etching sequentially and described etching stopping layer be second contact hole more than the described storage node contact plug of formation exposure; And
On each second contact hole, form described memory node.
12. as the method for claim 11, wherein said second insulating barrier forms by using nitride.
13. as the method for claim 11, wherein said first insulating barrier forms by using oxide.
14. a method that is used for forming at semiconductor device storage node of capacitor comprises the steps:
On substrate, form first insulating barrier;
Formation runs through first contact hole more than first insulating barrier;
On the sidewall of first contact hole, form sept with the rate of etch different with first insulating barrier;
A storage node contact plug more than formation is filled in first contact hole;
Same etch rate with described sept on described storage node contact plug forms etching stopping layer;
On described etching stopping layer, form sacrificial oxide layer;
According to the etching of oxide etching write out a prescription described sacrificial oxide layer of etching sequentially and described etching stopping layer, form thus and expose second contact hole more than the described storage node contact plug; And
On each second contact hole, form described memory node.
15. as the method for claim 14, wherein said first insulating barrier forms by using oxide.
16. as the method for claim 14, wherein said sept forms by using nitride.
17. a method that is used for forming at semiconductor device storage node of capacitor comprises the steps:
On substrate, form first insulating barrier;
Formation runs through first contact hole more than first insulating barrier;
On the sidewall of first contact hole, form sept with the rate of etch different with first insulating barrier;
Form a plurality of storage node contact plug, make described storage node contact plug be filled in first contact hole, and it highly is higher than described sept;
Same etch rate with first insulating barrier on described storage node contact plug forms second insulating barrier;
Second insulating barrier is planarized to the par of described storage node contact plug;
Same etch rate with described sept on described storage node contact plug forms etching stopping layer;
On described etching stopping layer, form sacrificial oxide layer;
Carry out etching process, it provides the low etching selectivity with respect to the sept of described storage node contact plug, second contact hole more than the described storage node contact plug of formation exposure; And
On each second contact hole, form described memory node.
18. as the method for claim 17, wherein said first insulating barrier forms by using oxide.
19. as the method for claim 17, wherein said sept forms by using nitride.
20. a method that is used for forming at semiconductor device storage node of capacitor comprises the steps:
On substrate, form interlayer insulating film;
The described interlayer insulating film of etching is to form a plurality of first contact holes;
On the sidewall of first contact hole, form sept;
Formation is filled into the interior storage node contact plug of first contact hole;
On described storage node contact plug, form etching stopping layer;
On described etching stopping layer, form insulating barrier;
Described insulating barrier of etching and described etching stopping layer be second contact hole more than the described storage node contact plug of formation exposure;
By using different etching selectivities between interlayer insulating film and the sept optionally to cave in through the predetermined portions of the interlayer insulating film of second contact holes exposing; And
On each second contact hole, form described memory node.
21. as the method for claim 20, if wherein described interlayer insulating film and described sept are respectively based on oxide and nitride, then by utilizing C 4F 6/ C 3F 8/ O 2The cave in predetermined portions of described interlayer insulating film of the high-density plasma method that adopts the mist of/Ar.
22. as the method for claim 21, wherein at described C 4F 6/ C 3F 8/ O 2In the mist of/Ar, approximate 100% if the ratio of Ar gas is set to, then every kind of remaining gas has and is set to approximate 4% to approximate 10% ratio.
23. as the method for claim 21, wherein said high-density plasma method is similar to 1 by supplying with, 000W is to approximate 2, the power of 000W and approximate 1,500W is to being similar to 2, and the bias power of 600W is implemented to the pressure of approximate 20mtorr from approximate 15mtorr in scope.
24. as the method for claim 20, wherein the step of the reservations branch of selectivity depression interlayer insulating film adopts and uses C 2F 6/ O 2The high-density plasma method of mist.
25. as the method for claim 24, wherein at described C 2F 6/ O 2Mist in, C 2F 6Gas has the flow-rate ratio that is arranged on approximate 100sccm, and O 2Gas has the flow-rate ratio of scope from approximate 1sccm to approximate 4sccm.
26. method as claim 24, wherein said high-density plasma method is similar to 300W to the power of approximate 500W and the bias power of the extremely approximate 400W of approximate 200W by supplying with, and implements to the pressure of approximate 10mtorr from approximate 1mtorr in scope.
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KR10-2004-0108694 2004-12-20
KR10-2004-0110083 2004-12-22
KR1020040110083 2004-12-22
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CN108538818A (en) * 2017-05-19 2018-09-14 睿力集成电路有限公司 A kind of preparation method and structure of high aspect ratio hole
CN115148672A (en) * 2021-03-29 2022-10-04 长鑫存储技术有限公司 Method for manufacturing semiconductor device
CN115472619A (en) * 2021-06-10 2022-12-13 旺宏电子股份有限公司 Memory element and manufacturing method thereof

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KR940006682B1 (en) * 1991-10-17 1994-07-25 삼성전자 주식회사 Method of fabricating a semiconductor memory device
JP3943320B2 (en) * 1999-10-27 2007-07-11 富士通株式会社 Semiconductor device and manufacturing method thereof
KR20010039179A (en) * 1999-10-29 2001-05-15 윤종용 Method for fabricating a cylindrical capacitor storage node in a semiconductor device
US6300191B1 (en) * 2001-02-15 2001-10-09 Taiwan Semiconductor Manufacturing Company Method of fabricating a capacitor under bit line structure for a dynamic random access memory device
US6383863B1 (en) * 2001-09-27 2002-05-07 Taiwan Semiconductor Manufacturing Company Approach to integrate salicide gate for embedded DRAM devices
KR100527401B1 (en) * 2002-06-03 2005-11-15 주식회사 하이닉스반도체 Method for fabricating semiconductor device

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Publication number Priority date Publication date Assignee Title
CN108538818A (en) * 2017-05-19 2018-09-14 睿力集成电路有限公司 A kind of preparation method and structure of high aspect ratio hole
CN115148672A (en) * 2021-03-29 2022-10-04 长鑫存储技术有限公司 Method for manufacturing semiconductor device
CN115472619A (en) * 2021-06-10 2022-12-13 旺宏电子股份有限公司 Memory element and manufacturing method thereof

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