CN1881858A - Realization process for synchronous channel transmitting code-level of broadband CDMA system - Google Patents
Realization process for synchronous channel transmitting code-level of broadband CDMA system Download PDFInfo
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- CN1881858A CN1881858A CNA2005100753736A CN200510075373A CN1881858A CN 1881858 A CN1881858 A CN 1881858A CN A2005100753736 A CNA2005100753736 A CN A2005100753736A CN 200510075373 A CN200510075373 A CN 200510075373A CN 1881858 A CN1881858 A CN 1881858A
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Abstract
The invention relates to a method for sending code sheet in synchronous channel of wideband code division multiple access system, which comprises: obtaining the main synchronous channel sending sequence CpNew and the auxiliary synchronous channel sending sequence CsNewi, k; then completing the projections of main synchronous channel sending sequence CpNew and the auxiliary synchronous channel sending sequence CsNewi, k; based on other treatments of descending physical channel, completing the frequency expansion, interference and weighting on the synchronous channel. With said invention, the resource used in other descending physical channel sending code treatment can be used to send code of synchronous channel, to improve the resource utilization and integration of base band processor of WCDMA system and reduce the cost of single channel.
Description
Technical field
The present invention relates to the baseband processor field of broadband CDMA system (WCDMA) base station, relate in particular to the implementation method that process for synchronous channel transmitting code-level is handled.
Background technology
Synchronizing channel is to support in the broadband CDMA system to comprise two subchannels: primary synchronization channel (P-SCH) and auxiliary synchronization channel (S-SCH) by the necessary down physical channel of Cell searching.The transmit frame structure that the third generation moves partnership (3GPP) regulation synchronizing channel is that every frame is 10 milliseconds, and every frame comprises 15 time slots, and every time slot is 2560 chips (chip), and spreading rate is 3.84 megahertzes.Each time-gap number in one frame is 0 from first time-gap number, and every time-gap number is bigger by 1 than previous time-gap number, and to the last a time-gap number is 14.3GPP regulation primary synchronization channel and auxiliary synchronization channel all only have data to send at 256 chips at first of every time slot, and the symbol sebolic addressing that 256 chips at first of the every time slot of primary synchronization channel send all is sequence ac
p, auxiliary synchronization channel is that the symbol sebolic addressing that 256 chips at first of the time slot of k send is sequence ac at time-gap number
s I, k, wherein: c
p, c
s I, kThe length that is the 3GPP regulation is specific nonzero value and the real part and the equal sequence of complex numbers of imaginary part of 256 chips; A is a real number, and value is+1 or-1; I is for sending sequence c
s I, kThe main scrambler group number of sector, auxiliary synchronization channel place, desirable 0,1 ..., in 64 integers such as 63 grades one; K is for sending sequence ac
s I, kThe time the timeslot number of synchronizing channel time slot at auxiliary synchronization channel place, desirable 0,1 ..., in 15 integers such as 14 grades one.
Primary synchronization channel sends sequence ac
pSend sequence ac with auxiliary synchronization channel
s I, kItself be exactly the sequence of spreading rate, primary synchronization channel and the auxiliary synchronization channel chip-level implementation method stipulated according to 3GPP are:
At first, obtain real number a, the main scrambler group number i of sector, auxiliary synchronization channel place and the value of synchronizing channel timeslot number k, generate primary ac
pAnd secondary synchronization channel sequences ac
s I, k
In timeslot number was preceding 256 chips of primary synchronization channel time slot of k, each chip was with primary ac then
pMultiplying each other with the weighted factor of primary synchronization channel respectively in I, Q road to sequential value that should chip, obtains I, the Q road chip-level weighted data of this chip primary synchronization channel respectively.Simultaneously in timeslot number was preceding 256 chips of auxiliary synchronization channel time slot of k, each chip was with secondary synchronization channel sequences ac
s I, kMultiplying each other with the weighted factor of auxiliary synchronization channel respectively in I, Q road to sequential value that should chip, obtains I, the Q road chip-level weighted data of this chip auxiliary synchronization channel respectively.
Follow the I road chip-level weighted data of the primary synchronization channel that will obtain and the I road chip-level weighted data addition of auxiliary synchronization channel, obtain the I road chip-level weighted data of synchronizing channel; With the Q road chip-level weighted data of the primary synchronization channel that obtains and the Q road chip-level weighted data addition of auxiliary synchronization channel, obtain the Q road chip-level weighted data of synchronizing channel simultaneously.
At last with the I of synchronizing channel, Q road chip-level weighted data respectively with I, the chip-level weighted data addition of Q road of the same chip of other down physical channels, obtain I, the Q road chip-level weighted data of all down physical channels, the I of all down physical channels, the chip-level processing of Q road finish.
Chip-level processing method according to other down physical channels transmissions except that synchronizing channel of 3GPP regulation is: at first the sign level data of down physical channel is gone here and there and change and be mapped as I, Q two paths of data, and the I that will obtain after will shining upon, Q two paths of data multiply each other with the spread spectrum code sequence of channel respectively, obtains channel code chip level I, Q two paths of data; Then with channel code chip level I, Q two paths of data according to the I road as real part, the Q road constitutes a channel code chip level complex data as the rule of imaginary part, again the channel code chip level complex data that obtains is multiplied each other with the weighted factor of channel scrambler sequence, channel successively, obtain I, the Q road chip-level weighted data of channel.
In the baseband processor design of WCDMA system base-station, when realizing that down physical channel sends the chip-level processing, if the method according to the 3GPP regulation realizes fully, then because the chip-level that synchronizing channel sends processing, different with other down physical channel chip-level processing methods, need independently to handle resource separately.When multichannel is integrated, it is identical that other down physical channels except that synchronizing channel send chip-level processing resource requirement, in the baseband processor down physical channel of WCDMA system base-station sends application-specific integrated circuit (ASIC), can adopt the mode that improves the operating frequency of handling resource, make same processing resource be finished the chip-level processing of a plurality of down physical channels by time division multiplexing ground.Finish the chip-level of synchronizing channel transmission and handle required processing resource with other down physical channel differences, the baseband processor down physical channel of WCDMA system base-station sends must use simultaneously in the application-specific integrated circuit (ASIC) handles the processing that resource is finished synchronizing channel.Sector of WCDMA system base-station only needs a primary synchronization channel and an auxiliary synchronization channel, there is the different separately relative delays different sectors, make each sector need synchronizing channel separately to handle resource, therefore to handle the utilance of resource low for process for synchronous channel transmitting code-level, caused waste very big on the resource.
Summary of the invention
The objective of the invention is to send low, the wasting shortcoming of process for synchronous channel transmitting code-level processing resource requirement reusability in the application-specific integrated circuit (ASIC) for the baseband processor down physical channel that overcomes the WCDMA system base-station, propose a kind of process for synchronous channel transmitting code-level implementation method, make process for synchronous channel transmitting code-level handle and to use other down physical channels transmission chip-levels processing resources to finish.
A kind of process for synchronous channel transmitting code-level of broadband CDMA system implementation method that the present invention proposes comprises
Step 1, acquisition primary synchronization channel send sequence C
PNewSend sequence C with auxiliary synchronization channel
SNew I, k: primary synchronization channel only sends ac at preceding 256 chips of every time slot
p, be embodied as at every time slot and all send out sequence C
PNew, sequence C
PNewLength is 2560 chips, and its preceding 256 chip value are followed successively by ac
p256 values, the sequential value of other chips be the plural number (0+0j); Auxiliary synchronization channel only sends ac at preceding 256 chips of every time slot
s I, k, being embodied as at timeslot number is that the synchronizing channel time slot of k is all sent out sequence C
SNew I, k, sequence C
SNew I, kLength is 2560 chips, and its preceding 256 chip value are followed successively by ac
s I, k256 values, the sequential value of other chips be the plural number (0+0j);
Step 2, with C
PNewAnd C
SNew I, kMapping obtains I, the Q circuit-switched data of primary synchronization channel and auxiliary synchronization channel respectively, and the Q circuit-switched data of the primary synchronization channel after the mapping, auxiliary synchronization channel all is zero, and the I road is respectively sequence C
PNewAnd sequence C
SNew I, kReal part;
Step 3, acquisition synchronizing channel spread spectrum code sequence are complete 1 sequence, and finish spread processing;
Step 4, selection synchronizing channel scrambler sequence are complete (1+j) sequence, and finish scrambling and handle;
Step 5, finish the primary synchronization channel weighting, finish the auxiliary synchronization channel weighting simultaneously;
Step 6, process for synchronous channel transmitting code-level processing finish, output synchronizing channel I, Q road weighted data.
Process for synchronous channel transmitting code-level implementation method provided by the invention, sending chip-level with other down physical channels handles the same, all passed through treatment steps such as mapping, spread spectrum, scrambling, weighting, finished the process for synchronous channel transmitting code-level processing thereby can use other down physical channels to send chip-level processing resource.Baseband processor down physical channel at the WCDMA system base-station sends in the application-specific integrated circuit (ASIC), no longer need independently resource processing synchronizing channel, thereby the baseband processor down physical channel that improves the WCDMA system base-station sends the resource utilization in the application-specific integrated circuit (ASIC), improve integrated level, reduce the single channel cost.Because the range of application of this channel processing resource has obtained expansion, increased the configurable flexibility of the channel processing resource of application-specific integrated circuit (ASIC) simultaneously.
Description of drawings
Fig. 1 process for synchronous channel transmitting code-level process flow provided by the invention figure.
Embodiment
Fig. 1 has provided process for synchronous channel transmitting code-level process chart provided by the invention.Below this figure, describe process for synchronous channel transmitting code-level processing method provided by the invention in detail.
At first obtain primary synchronization channel and send sequence C
PNewSend sequence C with auxiliary synchronization channel
SNew I, k: primary synchronization channel only sends ac at preceding 256 chips of every time slot
p, be embodied as at every time slot and all send out sequence C
PNew, sequence C
PNewLength is 2560 chips, and its preceding 256 chip value are followed successively by ac
p256 values, the sequential value of other chips be the plural number (0+0j); Auxiliary synchronization channel only sends ac at preceding 256 chips of every time slot
s I, k, being embodied as at timeslot number is that the synchronizing channel time slot of k is all sent out sequence C
SNew I, k, sequence C
SNew I, kLength is 2560 chips, and its preceding 256 chip value are followed successively by ac
s I, k256 values, the sequential value of other chips be the plural number (0+0j).These two sequences can generate in application-specific integrated circuit (ASIC), also can provide outside application-specific integrated circuit (ASIC).
Then with C
PNewAnd C
SNew I, kMapping obtains I, the Q circuit-switched data of primary synchronization channel and auxiliary synchronization channel respectively.The I circuit-switched data of primary synchronization channel is C
PNewReal part, the I circuit-switched data of auxiliary synchronization channel is C
SNew I, kReal part, the Q circuit-switched data of primary synchronization channel and the Q circuit-switched data of auxiliary synchronization channel are 0.
Then finish the spread processing of synchronizing channel.Selecting the synchronizing channel spread spectrum code sequence is complete 1 sequence, and I, the Q two paths of data of the primary synchronization channel that mapping is obtained multiply each other with the synchronizing channel spread spectrum code sequence respectively, obtain primary synchronization channel chip-level I, Q two paths of data; I, the Q two paths of data of the auxiliary synchronization channel that mapping is obtained multiply each other with the synchronizing channel spread spectrum code sequence respectively, obtain auxiliary synchronization channel chip-level I, Q two paths of data.
Then finishing the scrambling of synchronizing channel again handles.Selecting the synchronizing channel scrambler sequence is complete (1+j) sequence, with primary synchronization channel chip-level I, Q two paths of data and auxiliary synchronization channel chip-level I, the Q two paths of data that obtains, according to the I road as real part, the Q road is as the rule of imaginary part, constitute primary synchronization channel chip-level complex data and auxiliary synchronization channel chip-level complex data respectively, and multiply each other with the synchronizing channel scrambler sequence respectively, obtain after the primary synchronization channel scrambling data after the data and auxiliary synchronization channel scrambling.
At last with data after data and the auxiliary synchronization channel scrambling after the primary synchronization channel scrambling that obtains respectively and weighted factor separately multiply each other, the real part of the result of product of primary synchronization channel is as the I road chip-level weighted data of primary synchronization channel, and imaginary part is as the Q road chip-level weighted data of primary synchronization channel; The real part of the result of product of auxiliary synchronization channel is as the I road chip-level weighted data of auxiliary synchronization channel, and imaginary part is as the Q road chip-level weighted data of auxiliary synchronization channel.So far, the process for synchronous channel transmitting code-level processing finishes.
Claims (6)
1, a kind of process for synchronous channel transmitting code-level of broadband CDMA system implementation method comprises
Step 1, acquisition primary synchronization channel send sequence C
PNewSend sequence C with auxiliary synchronization channel
SNew I, k: primary synchronization channel only sends ac at preceding 256 chips of every time slot
p, be embodied as at every time slot and all send out sequence C
PNew, sequence C
PNewLength is 2560 chips, and its preceding 256 chip value are followed successively by ac
p256 values, the sequential value of other chips be the plural number (0+0j); Auxiliary synchronization channel only sends ac at preceding 256 chips of every time slot
s I, k, being embodied as at timeslot number is that the synchronizing channel time slot of k is all sent out sequence C
SNew I, k, sequence C
SNew I, kLength is 2560 chips, and its preceding 256 chip value are followed successively by ac
s I, k256 values, the sequential value of other chips be the plural number (0+0j);
Step 2, with C
PNewAnd C
SNew I, kMapping obtains I, the Q circuit-switched data of primary synchronization channel and auxiliary synchronization channel respectively, and the Q circuit-switched data of the primary synchronization channel after the mapping, auxiliary synchronization channel all is zero, and the I road is respectively sequence C
PNewAnd sequence C
SNew I, kReal part;
Step 3, acquisition synchronizing channel spread spectrum code sequence are complete 1 sequence, and finish spread processing;
Step 4, selection synchronizing channel scrambler sequence are complete (1+j) sequence, and finish scrambling and handle;
Step 5, finish the primary synchronization channel weighting, finish the auxiliary synchronization channel weighting simultaneously;
Step 6, process for synchronous channel transmitting code-level processing finish, output synchronizing channel I, Q road weighted data.
2, method according to claim 1 is characterized in that, the primary synchronization channel in the described step 1 sends sequence C
PNewSend sequence C with auxiliary synchronization channel
SNew I, kCan in application-specific integrated circuit (ASIC), form.
3, method according to claim 1 is characterized in that, the primary synchronization channel in the described step 1 sends sequence C
PNewSend sequence C with auxiliary synchronization channel
SNew I, kCan or provide outward by application-specific integrated circuit (ASIC).
4, according to the described method of the arbitrary claim of claim 1 to 3, it is characterized in that, spread spectrum in the described step 3 is that I, the Q two paths of data of primary synchronization channel that mapping is obtained multiplies each other with the synchronizing channel spread spectrum code sequence respectively, obtains primary synchronization channel chip-level I, Q two paths of data; I, the Q two paths of data of the auxiliary synchronization channel that mapping is obtained multiply each other with the synchronizing channel spread spectrum code sequence respectively, obtain auxiliary synchronization channel chip-level I, Q two paths of data.
5, method according to claim 4, it is characterized in that, scrambling in the described step 4, be primary synchronization channel chip-level I, Q two paths of data and auxiliary synchronization channel chip-level I, the Q two paths of data that to obtain, as real part, the Q road constitutes primary synchronization channel chip-level complex data and auxiliary synchronization channel chip-level complex data respectively as the rule of imaginary part according to the I road, and multiply each other with the synchronizing channel scrambler sequence respectively, obtain after the primary synchronization channel scrambling data after the data and auxiliary synchronization channel scrambling.
6, according to claim 1,2,3 or 5 described methods, it is characterized in that, described step 5, with data after data and the auxiliary synchronization channel scrambling after the primary synchronization channel scrambling that obtains respectively and weighted factor separately multiply each other, the real part of the result of product of primary synchronization channel is as the I road chip-level weighted data of primary synchronization channel, and imaginary part is as the Q road chip-level weighted data of primary synchronization channel; The real part of the result of product of auxiliary synchronization channel is as the I road chip-level weighted data of auxiliary synchronization channel, and imaginary part is as the Q road chip-level weighted data of auxiliary synchronization channel.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101383634B (en) * | 2008-10-16 | 2012-03-28 | 北京天碁科技有限公司 | Method and apparatus for searching downlink synchronous sequence |
| CN101102125B (en) * | 2007-08-09 | 2012-06-13 | 中兴通讯股份有限公司 | Auxiliary synchronization channel scrambling method and corresponding cell searching mode |
| CN101690340B (en) * | 2007-05-01 | 2012-08-29 | 株式会社Ntt都科摩 | Base station apparatus, mobile station apparatus, and synchronization channel transmission method |
| CN101682361B (en) * | 2007-05-25 | 2013-01-02 | 高通股份有限公司 | Scrambling methods for synchronization channels |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100389549C (en) * | 2002-06-11 | 2008-05-21 | 上海贝尔有限公司 | Downgoing baseband processing unit of WCDMA system |
| JP4181938B2 (en) * | 2003-07-28 | 2008-11-19 | 日本電気株式会社 | Asynchronous cellular mobile station between CDMA base stations and cell search method thereof |
-
2005
- 2005-06-16 CN CN200510075373A patent/CN1881858B/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101690340B (en) * | 2007-05-01 | 2012-08-29 | 株式会社Ntt都科摩 | Base station apparatus, mobile station apparatus, and synchronization channel transmission method |
| CN101682361B (en) * | 2007-05-25 | 2013-01-02 | 高通股份有限公司 | Scrambling methods for synchronization channels |
| CN101102125B (en) * | 2007-08-09 | 2012-06-13 | 中兴通讯股份有限公司 | Auxiliary synchronization channel scrambling method and corresponding cell searching mode |
| CN101383634B (en) * | 2008-10-16 | 2012-03-28 | 北京天碁科技有限公司 | Method and apparatus for searching downlink synchronous sequence |
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| CN1881858B (en) | 2010-05-05 |
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Effective date of registration: 20151111 Address after: Dameisha Yantian District of Shenzhen City, Guangdong province 518085 Building No. 1 Patentee after: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Address before: 518057 Nanshan District, Guangdong high tech Industrial Park, science and Technology Industrial Park, ZTE building, block A, layer 6, layer Patentee before: ZTE Corporation |
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Application publication date: 20061220 Assignee: Xi'an Chris Semiconductor Technology Co. Ltd. Assignor: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Contract record no.: 2019440020036 Denomination of invention: Realization process for synchronous channel transmitting code-level of broadband CDMA system Granted publication date: 20100505 License type: Common License Record date: 20190619 |
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