CN1875349A - Methods and apparatus for interleaving in a block-coherent communication system - Google Patents
Methods and apparatus for interleaving in a block-coherent communication system Download PDFInfo
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Abstract
Methods and apparatus for communication over a block-coherent communication system are described. The present invention is directed to methods of interleaving coded bits that are encoded by codes, e.g., LDPC codes, having graph structures largely comprised, of multiple identical copies of a much smaller graph.
Description
Technical field
The present invention relates to be used for the method and apparatus of data communication on the piece coherent channel, relate in particular to and be used for access and/or interweave by the method and apparatus of the parity check code coded data position of for example low-density checksum (LDPC) sign indicating number.
Background technology
When communication system can not make receiver keep a reliable estimation that is used for instant channel gain (amplitude, and especially phase place), it needed noncoherent detection.Noncoherent communication systems comprises, for example, wireless multiple access system, wherein the limited portable terminal of power can't transmit powerful known symbols (pilot tone) to start reliable channel estimating.Noncoherent communication channel can have some coherences: coherent block is very little time interval of channel variation betwixt.Communication on such channel is considered to the piece coherent communication.
The piece coherent communication can occur in fast frequency-hopped Orthodoxy Frequency Division Multiplex (OFDM) access system naturally.In such system, information can be modulated onto in each symbol time on the subclass of the usable frequency that is called tone (tone).In order to improve spectrum efficiency and to increase diversity gain, sometimes, the tone that is used is one group with every L code element and jumps on the frequency band of whole use apace, promptly, L continuous code element is mapped to a tone, and L symbol mapped arrives another different tone in addition subsequently, or the like.When L was very little, we can suppose that a continuous L code element has experienced the channel gain that equates.Though the amplitude of the gain of two continuous L code elements can be very approaching, their phase place normally fully independently.
Or rather, a block-coherent communication system can be defined as follows: for the system that represents in the discrete time territory, channel gain is unknown complex random variable, it is consistent for every L continuous code element, yet but changing independently aspect other according to certain distribution, for example, its phase place goes up evenly in [0,2pi] and distributes and the whose amplitude obeys rayleigh distributed.
For the piece coherent communication, nominal modulation scheme be difference M-unit phase-shift keying (PSK) (DMPSK).DMPSK carries information with the phase differential between two continuous code elements on the coherent block.Illustrate, transmit the individual MPSK information code element s (i) of N * (L-1), this N the continuous s (1) that is expressed as, s (2), ..., each group differential coding of the group of L-1 the code element of s (L-1) is to transmitted symbol t (1), t (2), ..., t (N), wherein t (1)=1, and t (j+1)=t (j) * s (j), j=1 ... .N-1.
Modulation except that DMPSK also is possible.For example, along with the insertion of known symbols in piece, information code element can directly be transmitted on other code element substitutes differential transfer.These can be called pseudo-pilot modulation.Yet, it is evident that because the phase place uncertainty, have L-1 information code element in length is the gap (dwell) of L, to transmit at most.Usually we transmit M information code element at hypothesis in each gap, and this can be considered to a transmission unit.In other words, each transmission unit comprises L-M known symbols.M has L-1 at most.For example, two schemes mentioning all have M=L-1.
The block-coherent communication system that has forward error correction generally includes scrambler (redundancy of its insert structure is in original data stream), DMPSK modulator (its maps binary data bits is to the MPSK code element), detuner (its difference ground extracts soft information and it is fed into demoder), and demoder (it is according to the soft information decoding origination message that obtains from detuner).
In most of coded systems, the receiver of using iterative demodulation sign indicating number-below be referred to as the scheme of turbo equilibrium-significant performance gain is arranged than non-iterative receiver.For example, convolution and/or turbo encoding D MPSK system, be published in by researchs such as Shamai among " the Iterative decoding for codednoncoherent MPSK communications over phase-noisy AWGNchannel " of IEEProceedings Communication 2000, proof turbo-equilibrium has realized the channel capacity of 1.3dB, manys 1dB than traditional scheme.
Shown that code Design need be considered the influence of iterative demodulation in order to make the turbo equilibrium effective to greatest extent.The needs of code Design and the effective means of realization are described in the paper " Design of Low-Density Parity-Check Codes inNoncoherent Communication " of Jin and Richardson, publish on the International symposium on June 30th, 2002 information theory.This method has improved the performance of channel capacity and has not exceeded 0.7dB.
For the optimum performance of turbo equilibrium, this coded-bit also should interweave in transmission fully.This interweaves is for two purposes.On the one hand, for the purpose of decoding, it can eliminate the correlativity between the flexible message related with the coded-bit of small distance in the block structure effectively.On the other hand, for the purpose of demodulation, interweave and to eliminate the correlativity that is present between the message that feeds back to same coherent block.It has been generally acknowledged that pilotaxitic texture is interweaving at random.Yet, in order to realize interweaving at random, must be addressable at transmitter and receiver, for example store identical (producing at random) displacement.This has caused the demand to mass storage, to be used for the real system by a large amount of block encodings.
Because the performance of turbo equilibrium is very important, in order to allow communication system can be implemented in large-scale equipment, subscriber equipment for example, middle use can realize that the turbo equilibrium be very important with rational cost.Therefore realizing being used for the ability of the turbo equalization scheme of block-coherent communication system effectively, for example, aspect hardware cost, is very important.
Consider its coding gain and sufficient design space near capacity, utilizing the LDPC coding is desirable as the encoding scheme in the piece coherent communication.
The LDPC coding is represented by the bigraph that is called Tanner figure (bipartile graphs) usually, wherein a group node (variable node) is corresponding to the position of code word, and organize node (restraint joint is called check-node sometimes) separately, corresponding to the parity check constraint group of this yard of definition.The limit link variable node of this figure is to restraint joint.If variable node is connected by the limit with restraint joint in the figure, their adjacent nodes of just being known as.For simplicity, we suppose that generally a pair of node is connected by a limit at most.
The bit sequence related one to one with variable node is the code word of this yard, and and if only if for each restraint joint, the bit adjacent (by they and variable node related) mould 2 and be 0 with restraint joint, that is and, they comprise even number 1.
Be connected to node promptly, the quantity on the limit of variable node or restraint joint is called the degree of this node.Regular graph or regular code are meant that its all variable node has identical degree j, and its all restraint joint has identical degree k.We say that this sign indicating number is (j, k) regular code in this case.These codings are invented by Gallager (1961) at first.Opposite with " regular " sign indicating number, the restraint joint of irregular code and/or variable node have different degree.For example, some variable node can be 4 degree, other be 3 degree, also some is 2 degree.
Though irregular coded representation or implement has more complicatedly shown that irregular LDPC sign indicating number can provide better error correction/detection performance than the LDPC sign indicating number of rule.
A typical bigraph 200 as shown in Figure 2, it has determined that a length is ten, ratio is (3,6) regular LDPC sign indicating number of 1/2nd.Length 10 expressions have 10 variable node V
1-V
10, each is by the code word X of 1 bit
1-X
10Sign, variable node group V
1-V
10Usually in Fig. 2, represent by Reference numeral 202.Ratio 1/2nd shows that the number of check-node is half of variable node,, has 5 check-node C that is
1-C
5, by Reference numeral 206 expressions.Ratio 1/2nd further these 5 restraint joints of expression is linear independences, and is as described below.
Because Fig. 2 for example understands the figure that is associated with the sign indicating number of length 10, be understandable that figuring length is that 1000 code word will complexity 100 times.
The practical problems that is caused by the turbo equilibrium according to implementation cost, is soft inputting and soft output (SISO) detuner and in the complicacy of the data interlacing of transmitter and receiver.To improving interleaving technology and/or realizing still existing demand.The present invention proposes a kind of effective and efficient manner and realizes interweaving.Data interlacing method of the present invention is suitable for using with the coded data bit very much, for example, and low-density checksum (LDPC) coding.
Description of drawings
Fig. 1 illustrates a typical communication system of the method and apparatus that adopts the present invention's proposition, comprises scrambler, interleaver, modulator, channel, detuner, deinterleaver and demoder.
Fig. 2 illustrates the bigraph that a typical length is 10 regular LDPC sign indicating number.
Fig. 3 be the diagrammatic representation of a little LDPC sign indicating number to present according to an example of the present invention, this little LDPC sign indicating number is as the basis of a bigger LDPC sign indicating number.
Effect when Fig. 4 illustrates the little LDPC figure that shows and is copied into three parts in Fig. 3.
Fig. 5 illustrates the result who uses the algebraically of typical 4 * 8LDPC sign indicating number to interweave according to the present invention.Particularly, this figure has illustrated the direct mapping from coded data bit to a transmission unit part.
Fig. 6 illustrates a typical interleaver, is suitable for using as interleaver in system transmitter shown in Figure 1, and it has realized interweaving according to algebraically of the present invention.
Fig. 7 illustrates the soft value of LDPC demoder and uses consistance between the transmission unit of typical code structure shown in Figure 5.This soft value comprises 3 bits.
Fig. 8 illustrates a typical structure that is used at iterative demodulation and decoding application interleaving and de-interleaving, is suitable for using as interleaver and deinterleaver in the receiver of system shown in Figure 1.
Summary of the invention
The present invention relates to method and apparatus at the enterprising row data communication of piece coherent channel.For the sake of simplicity, we are called a gap (dwell) to the code element of transmitting in a coherence interval.The length in gap is L.The code element in gap as information transmission unit, comprises M information code element and (L-M) individual known symbols.Each information code element is a code element by the mapping of the P bit in the code word.
The present invention relates to be used for the method and apparatus of algebraically interleaved coded bits between the scrambler of transmitter and modulator, it does not use or uses the storer of relatively small amount.The present invention also relates to be used for the interweave method and apparatus of flexible message of between the demoder of receiver and detuner algebraically, it need not or only need the storer of relatively small amount.
In order to set forth the present invention, we suppose that QPSK is a modulation constellation.According to this hypothesis, a transmitted symbol is used i.e. one two hyte (dibit) of two coded-bit 0--.Yet higher order modulation schemes can easily be summarized and be applied to the method for describing among the present invention, and for example in the such enforcement of MPSK or QAM, they are deemed to be within the scope of the present invention.
Algebraically of the present invention interweaves and relates to by LDPC sign indicating number coded data bit, and these LDPC sign indicating numbers have definite hierarchical structure, in this structure full UDPC figure show as on very most of by we can say Z or Z doubly the multiple copies of littler figure form.
This Z graph copies may equate.Exactly we will be with reference to this less chart as projection (projected) chart.We claim that this Z parallel edges is a vector edges, and the Z parallel nodes is as vector nodes.At one in first to file, the U.S. Patent application S.N.09/975 of application on October 10 calendar year 2001,331 titles are " Methods and Apparatus forPerforming LDPC Code Encoding and Decoding ", at this specially in conjunction with it as a reference, it has described the demoder realization that utilizes such structure.The observations of a key is that whole computings can be finished in that all copies are parallel.Yet this Z copy does not separate, and they are merged into a big chart, than the big Z of this projected graph doubly.This is to finish with Z the copy that a control mode connects this projected graph.Specifically, allow Z bar limit in the vector edges through displacement between the copy of a projected graph or exchange, for example, from the variable node side to the restraint joint side.In vector quantization encoding process, allow corresponding to the Z bit in the vector of a projection variable node through a displacement corresponding to Z parallel projected graph.
The purpose that interweaves between coding and modulation is the correlativity between the flexible message (value) that reduces the short-range coded-bit in the LDPC chart.In addition, expect equally to interweave to create the structure that helps the turbo equilibrium.For this purpose, the coded-bit in gap preferably has the large-scale number of degrees, since well-known, the speed of convergence of the node of different number of degrees significant difference in decode procedure.Decode successfully in phase place in front, the bit related with the higher number of degrees can be to producing more reliable estimation on the unknown phase in the gap.Usually like this, improve the flexible message that in the gap, produces on the adjacent code element, and then more effectively assisted this demoder.
When data bit is encoded by vector-LDPC sign indicating number, there is this desired characteristics in the gap of the node number of degrees that mix to realize easily that it has a developable structure on a large scale.Therefore if the storer of memory encoding bit is configured to Z * n matrix, the bit on same column (physically identical address) is corresponding to node identical in this projected graph and the identical number of degrees are arranged so.
This vector quantization encoding process, be as described in the U.S. Patent application S.N.__ of " Methodsand Apparatus for Performing LDPC Code Encoding and Decoding " as the title of on July 11st, 2003 application, can arrange these row so that the number of degrees of associated variable node are in an order that increases progressively.The algebraically deinterleaving method in the gap that forms the coded-bit that is associated with the variable node of the large-scale number of degrees has been simplified in such ordering.Typical mode is that this matrix is split into L-1 continuous submatrix equably.Row have been guaranteed that according to the characteristic that increases progressively number of degrees ordering this submatrix comprises the variable node of the similar number of degrees: first submatrix has the minimum number of degrees, and last submatrix has the highest number of degrees.Therefore by the gap of getting two bits formation from different submatrixs desired characteristics is arranged.
Interweaving of coded-bit can be as following execution implemented according to the invention.
A typical interleaver apparatus of the present invention comprises the storer and the interleave circuit that are used for the memory encoding bit.This interleave circuit produces one group of control information, is used for controlling reading bit from this storer.The control information group of each generation comprises transmission unit identifier, Z vector identifier and row identifier.This control circuit in one embodiment, comprises four elements: code element ID generation module, bit ID generation module, row ID generation module and control information generation module.This code element ID generation module can be used as repeat counter and realizes, it produces one from 0 to M-1 digital s.This repeat counter increases as the function cycle ground of a system clock clk, and for example, per clock period of s increases once; This numeral s determines the symbol index in a gap.This bit ID generation module also can be used as repeat counter and realizes, for example produces a repeat counter from 0 to z-1 digital b.This numeral b increases when symbol index signal s reaches zero periodically; Numeral b determines the bit index of selection in these row, for example, is kept at the delegation of row in the array in the storer.Row ID generation module 603 produces one from 0 to a-1 digital c, and can be implemented as another counter.This numeral c increases when bit index b reaches zero periodically; Numeral c is a column index.By bit index b, symbol index s and column index c, the control information generation module is produced one group of control information, comprises transmission unit identifier, Z vector identifier and row identifier, is used for being controlled at which position access of coded-bit storer.In one embodiment, this Z-vector identifier is c+a * s, and this row identifier is 2 * b.This transmission unit is by the transmission unit identifier sign of value for b+c * Z, and wherein b and c define as above, and Z is the component number in each Z vector, * expression multiplying.
At receiver side, the direct mapping of abideing by between data bit and the transmission unit comes demodulation.Here supposing has the ordering identical with this binary code word structure from demoder output soft.Yet this soft value comprises the K-bit corresponding to a coded-bit.Each of k bit can be kept in the different arrays in D the array in the storer, and wherein D is a positive integer.In most of the cases, k is the integral multiple of D.A typical storer is for every soft value than peculiar three bits, and each value is by identical code bit identifier sign.This three bit can be in a storage unit; Or this three bit can be in three different storage unit.By this structure, the interleaving apparatus that clearly is used for the same type of a transmitter can also be used for a receiver so that for the purpose access of the demodulation soft value corresponding to a transmission unit.
Suppose that this reception value also meets the ordering identical with code word, so identical pilotaxitic texture can be applied in again in the process of the access reception value for the purpose of demodulation.
The advantage of a lot of additional embodiment, feature and method and apparatus of the present invention will be discussed in detailed description subsequently.
Embodiment
Fig. 1 illustrates and realizes general communication system 10 of the present invention.This system 10 comprises the transmitter 100 that is coupled to receiver 120 by communication channel 110.This transmitter 100 comprises digital coding circuit (for example, scrambler 101), interleaver 102, and modulator 103.This receiver comprises detuner 121, deinterleaver 122, interleaver 123, and data decoder 124.The binary data stream A of these scrambler 101 mapping inputs is to having redundant structure binary data stream X
1This interleaver 102 X that interweaves
1To another data stream X
2This modulator 103 conversion binary stream X
2To the physical signalling that can be used in actual transmissions, QPSK signal for example.This channel 110 can be, for example, and airlink.Modulation signal is sent to receiver 120 by channel 110.At receiver side, detuner 121 receives from noise distortion and extracts information X the Y
2'.Deinterleaver 122 rearrangement flexible message X
2' to X corresponding to the original order of coding structure
1'.Demoder 123 is present in the encoded data stream X that is produced by demodulation by use
1' in redundanat code attempt to recover original binary data stream A.121 data path is expressed as a feedback control loop from demoder 123 to demodulation.This feedback information should interweave so that will transform to ordering when the modulation in the ordering in when coding by an interleaver 124.
Fig. 3 illustrates a simple irregular LDPC coding with chart 300 forms.This code length is 5,5 variable node V by 302
1To V
5Expression.The C of four check-nodes 306
1To C
4By 12 limits 304 altogether being coupled to variable node 302.
Fig. 4 is that a chart 400 illustrates the result who little chart shown in Figure 3 is made 3 parallel copies.Variable node 402 ', 402 " and 402 correspond respectively to first to the 3rd chart, obtain because the chart of Fig. 3 is produced three copies.In addition, check-node 406 ', 406 " and 406 correspond respectively to first to the 3rd chart, obtain by producing three copies.Note there is not the node of a chart in these three charts is connected to the limit of the node of another chart in these three charts.Therefore, this reproduction process, this basic scheme " promotes (lift) " 3 times, produces three disjunct identical charts.(these 3 copies are by the interconnection of permutation vector limit usually)
Our algebraically that will continue to describe the coded-bit of realizing according to the present invention interweaves now.
Coded-bit is kept in the storer that is configured to Z * n.Or equivalently, we are considered as n Z vector to this binary code word, and each vector comprises the Z bit.The Z that is used for vector LDPC sign indicating number is the multiple of P, and P is and a bit number that transmitted symbol is related.Because suppose P=2 in the QPSK modulation, we obtain Z=2z.We further select columns is the multiple of M, and M is the number of the information transmission code element in transmission unit, i.e. n=aM.A deinterleaving method of the present invention has been determined the position with the P bit that is associated with each code element in each transmission unit.Very clear, this storage unit is corresponding to the off-set value in Z-vector identifier and the Z-vector.Sorting coding data of the present invention are as follows: j gap (wherein j 1 to z * a) will comprise 2 bits, and this 2 bit is by i * n/M+[j/ (Z/P)] in the Z bit vectors determined, and side-play amount is 2 * (j mod Z/P), wherein i is 0 to M-1.In this case, the address that is used to retrieve this data bit can easily produce with algebraic method, needn't utilize storer for this purpose.
Fig. 5 illustrates a pilotaxitic texture that is used for coherence interval, wherein L=5, M=4 and P=2.The coded-bit of vector-LDPC coding of a Z=4 and n=8 has been passed through in array 500 expressions.This array can be kept in the corresponding structure array of storage unit.This coded-bit 500 is stored with one 4 * 8 structure, wherein each element representation one bit in this array 500; (i, bit j) is by c (i, j) expression in the unit.Each gap 501,502,503 and 504 will comprise 4 information code elements, and it forms by the bit that uses array 500.The method of this proposition makes the gap 801 of winning comprise coded-bit c (1,1), c (2,1), c (1,3), c (2,3), c (1,5), c (2,5), c (1,7), c (2,7).For ease of illustrating, the typical modulation of this use is a pseudo-pilot modulation, so one two hyte 00 is inserted in each gap (centre), is provided in this gap one in 5 code elements.Therefore, first gap that is sent out is S (c (1,1) c (2,1)), S (c (1,3) c (2,3)), S (00), S (c (1,5) c (2,5)), S (c (1,7) c (2,7)), shown in 501.Similarly, second gap 502 comprises S (c (3,1) c (4,1)), S (c (3,3) c (4,3)), S (00), S (c (3,5) c (4,5)), S ((3,7) c (4,7)).Or the like.
Be used for an equipment of the deinterleaving method that proposed, for example interleaver 102, as shown in Figure 6.This interleaver 102 comprises the storer 610 and the interleave circuit 600 that is coupled that is used to store coded-bit, as shown in Figure 6.One group of control information of interleave circuit 600 generations is used for controlling reads two hytes from storer 610.The control information group of each generation comprises transmission unit identifier, Z vector identifier and row identifier.Circuit 600 comprises four elements: code element ID generation module 601, bit ID generation module 602, row ID generation module 603 and control information generation module 604.Module 601 is repeat counters, and it produces one from 0 to M-1 digital s.This counter 601 increases progressively as the periodicity of function ground of a system clock clk, and for example, each clock period of s increases progressively once; This numeral s determines the symbol index in the gap.Module 602 is repeat counters, produces one from 0 to z-1 digital b.This numeral b increases when symbol index signal s reaches zero periodically; Numeral b determines the bit index of selection in these row, for example can be kept at the delegation of row in the array 600 in the storer 605.Module 603 is another counters.Module 603 produces one from 0 to a-1 digital c.This numeral c increases progressively when bit index b reaches zero periodically; Numeral c is a column index.Utilize bit index b, symbol index s and column index c, control information generation module 604 is produced one group of control information, comprises transmission unit identifier, Z vector identifier and row identifier, is used for being controlled at which cell access of coded-bit storer 605.In one embodiment, this Z-vector identifier is c+a * s, and this row identifier is 2 * b.The transmission unit identifier sign that this transmission unit is b+c * Z by a value, wherein b and c define as above, and Z is the element number in each Z vector, * expression multiplying.
At receiver side, the direct mapping of abideing by between data ratio and the transmission unit comes demodulation.We suppose from the soft output of demoder the ordering identical with this binary code word structure arranged, for example, and shown in array 600.Yet this soft value comprises the K bit corresponding to coded-bit.Each of k bit can be kept at the different array in D the array, and wherein D is a positive integer.In most of the cases, k is the integral multiple of D.Than peculiar three bit soft values, each is by identical sign indicating number bit identifier sign for each for typical storer 700.This three bit can be in a storage unit; Or these three bits are in three different storage unit 701,702,703, shown in 700.Utilize this structure, obviously identical interleave circuit 600 can be used for the soft value that is used for transmission unit that access is used for demodulation.
Suppose that this reception value also meets the ordering identical with code word, so identical pilotaxitic texture can be applied in again in the process of the access reception value for demodulation.
In the turbo equilibrium, we have the structure identical with coded-bit from the soft output of this vector decode device (module 800) with soft input from channel receiver (module 808) at hypothesis, for example, and shown in array 600.Yet the clauses and subclauses of the above-mentioned structure of mentioning will be the integer rather than the bit of K bit, because they are flexible messages.Interleave circuit 802 can be identical with circuit 600 shown in Figure 6.This interleave circuit 802 produce correct address with by gap order access from soft output of demoder and the soft input that comes self-channel.Identical calculated address, the delay that experience is introduced by lag line 810 is provided for being controlled at demodulation this soft write address of writing input that is input to demoder afterwards.
Describing method or method step can use to be included in such as the machine-executable instruction in the machine-readable medium of RAM, floppy disk etc. and realize above many, for example soft, control is such as having or not having the equipment of the multi-purpose computer of additional firmware for example to realize all or the part said method at one or more communication net nodes.Therefore, except other, the machine-readable medium that this present invention relates to comprise machine-executable instruction is used to cause the step of carrying out one or more said methods such as the machine of processor and related hardware.
In view of the brief description of foregoing invention, a lot of additional variation of aforesaid method and apparatus of the present invention it will be apparent to those skilled in the art that.Such variation will be thought within the scope of the present invention.Method and apparatus of the present invention is passable, in various embodiments, be used to the communication means that can be used to provide the wireless telecommunications link between Ingress node and the mobile terminal node of CDMA, Orthodoxy Frequency Division Multiplex (OFDM) and/or multiple other types.This Ingress node is established as the base station in some embodiment, and it uses OFDM and/or CDMA and mobile terminal node to establish a communications link.In multiple embodiment, this mobile terminal node realizes as notebook, PDA(Personal Digital Assistant) or other portable set, comprises reception/transtation mission circuit and logical and/or program, is used to realize method of the present invention.
Claims (22)
1. method of handling a plurality of Z vectors, each Z vector comprises Z element, each element comprises the K bit, wherein Z is to be positive integer greater than zero greater than 1 positive integer and K, these a plurality of Z vectors are corresponding to binary code word, the described binary code word of part has the direct mapping relations to a plurality of transmission units, described a plurality of Z vector is stored in one group of D memory array, wherein D is the integer greater than zero, each memory array comprises the Z line storage unit, each storage unit of delegation is corresponding to different array row, each array is listed as the different Z vector corresponding to described a plurality of Z vectors, row of each array in the described D of each the Z vector identification memory array, this method comprises:
Produce a series of control information groups, each control information group comprises:
I) transmission unit identifier;
Ii) Z vector identifier;
Iii) row identifier; And
Control information group at least one generation:
Read P and multiply by K divided by the D bit from each row, each is listed as by described Z vector identification, and described Z vector is by the sign of the Z vector identifier in the control information group that is included in described at least one generation, and wherein P is the positive integer greater than zero.
2. the method for claim 1,
The processing of wherein said method is carried out prior to the transmission of described transmission unit by transmission equipment;
Wherein D equals 1; And
K equals 1.
3. the method for claim 2 further comprises:
Control information group for described at least one generation:
According to the described P bit that reads from storer, generate the part of described transmission unit, described transmission unit is identified by the transmission unit identifier in the control information group that is included in described at least one generation.
4. the method for claim 3,
Wherein said a plurality of Z vector comprises n of described a plurality of Z vectors, and wherein n is the positive integer greater than 1; And
The step that wherein produces a series of control information groups also comprises:
The value of Z vector identifier is increased progressively n divided by M, and wherein M is the number of the part of a part with binary code word transmission unit that direct mapping relations are arranged, and the part of described binary code word comprises M P bit doubly.
5. the method for claim 4,
Wherein each part of transmission unit is a code element; And
Wherein said transmission unit is the gap.
6. the method for claim 3, the step that wherein produces a series of control information groups also comprises:
Increase progressively the value of described Z vector identifier for M time;
After increasing progressively the value of described Z vector for M time:
I) reset the value of this Z vector identifier to the described Z vector identifier value that increases progressively when beginning; And
Ii) row identifier is increased progressively P.
7. the method for claim 6, the step that wherein produces a series of control information groups also comprises:
Z increased progressively described row identifier value divided by P time after, wherein Z was an integer divided by P,
It is zero that this row identifier value is set; And
This Z vector identifier value is increased progressively the positive integer value of preliminary election.
8. the method for claim 7, the positive integer value of wherein said preliminary election is 1.
9. the method for claim 2, wherein said binary code word is a low density parity check codewords.
10. the method for claim 1,
The processing of wherein said method is used to handle the reception transmission unit; And
Wherein K is greater than zero integer and is the bit number that is used to represent corresponding to the soft value of a bit of described binary code word.
11. the method for claim 10, wherein D equals K or 1.
12. the method for claim 11 further comprises:
Control information group for described at least one generation:
To offer detuner from the P bit that storer reads.
13. the method for claim 10 further comprises:
Control information group for described at least one generation:
According to the P bit that reads from described storer, generate the part of described transmission unit, described transmission unit is identified by the transmission unit identifier in the control information group that is included in described each generation.
14. the method for claim 13,
Wherein said a plurality of Z vector comprises n of described a plurality of Z vectors, and wherein n is the positive integer greater than 1; And
The step that wherein produces a series of control information groups also comprises:
The value of Z vector identifier is increased progressively n divided by M, and wherein M is the number of the part of a part with binary code word transmission unit that direct mapping relations are arranged, and the part of described this binary code word comprises M P bit doubly.
15. the method for claim 13, the step that wherein produces a series of control information groups also comprises:
The row identifier value is increased progressively P, described Z vector identifier value is increased progressively M time;
Increase progressively for M time after the value of described Z vector:
I) reset the value of this Z vector identifier to the described Z vector value that increases progressively when beginning; And
Ii) row identifier is increased progressively P.
16. the method for claim 15, the step that wherein produces a series of control information groups also comprises:
Z increase progressively divided by P time add the row identifier value after, wherein Z is an integer divided by P,
It is zero that this row identifier value is set; And
This Z vector identifier value is increased progressively the positive integer value of preliminary election.
17. the method for claim 16, the positive integer value of wherein said preliminary election is 1.
18. the method for claim 10, wherein said binary code word are low density parity check codewords.
19. equipment that is used to handle a plurality of Z vectors, each Z vector comprises Z element, each element comprises the K bit, wherein Z is to be positive integer greater than zero greater than 1 positive integer and K, these a plurality of Z vectors are corresponding to binary code word, the described binary code word of part has the direct mapping relations to a plurality of transmission units, and described equipment comprises:
The storer that comprises one group of D memory array, be used to store described a plurality of Z vector, wherein D is the integer greater than zero, each memory array comprises the Z line storage unit, each storage unit of delegation is corresponding to different array row, each array is listed as the different Z vector corresponding to described a plurality of Z vectors, row of each memory array in the described D of each the Z vector identification memory array;
Memory access control module is used to generate a series of control information groups, and each control information group comprises:
I) transmission unit identifier;
Ii) Z vector identifier;
Iii) row identifier; And
Be used for reading P from each row of described storer and multiply by the device of K divided by the D bit, wherein P is the positive integer greater than zero, and each is listed as by the Z vector identification, and described Z vector is identified by the Z vector identifier in the control information group that is included in described at least one generation.
20. the method for claim 1,
Wherein D equals 1; And
Wherein K equals 1.
21. the method for claim 19, wherein said memory access control module comprises:
First counter is used to produce described Z vector identifier; And
Second counter is used to produce described row identifier.
22. machine-readable medium, comprise the machine-executable instruction that is used for a plurality of Z vectors of control computer device processes, each Z vector comprises Z element, each element comprises the K bit, wherein Z is to be positive integer greater than zero greater than 1 positive integer and K, these a plurality of Z vectors are corresponding to binary code word, and the described binary code word of part has the direct mapping relations to a plurality of transmission units, and described machine-executable instruction comprises and is used for the instruction that control computer equipment carries out following operation:
Produce a series of control information groups, each control information group comprises:
I) transmission unit identifier;
Ii) Z vector identifier; With
Iii) row identifier; And
Control information group for described at least one generation:
Read P and multiply by K divided by the D bit from each row, each is listed as by described Z vector identification, and described Z vector is by the sign of the Z vector identifier in the control information group that is included in described at least one generation, and wherein P is the positive integer greater than zero.
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| US45967703P | 2003-04-02 | 2003-04-02 | |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102282846A (en) * | 2009-01-19 | 2011-12-14 | Lg电子株式会社 | Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal |
| CN107104678A (en) * | 2011-05-18 | 2017-08-29 | 松下电器产业株式会社 | Sending method, dispensing device and method of reseptance, reception device |
| CN107707332A (en) * | 2011-05-18 | 2018-02-16 | 松下电器产业株式会社 | Parallel bit interleaver |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101136896B (en) * | 2007-09-18 | 2011-06-29 | 东南大学 | Frequency domain iteration equalizing method based on fast Fourier transformation |
| US8345784B2 (en) * | 2009-06-05 | 2013-01-01 | Telefonaktiebolaget L M Ericsson (Publ) | Reduced-complexity equalization with sphere decoding |
| US8543882B2 (en) * | 2010-10-15 | 2013-09-24 | Tyco Electronics Subsea Communications Llc | Joint carrier phase estimation and forward error correction |
| CN104079378B (en) * | 2014-06-30 | 2017-05-24 | 天津七一二通信广播股份有限公司 | Digital trunked communication 3/4 code rate grouped data error-resisting decoding method |
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| US5392299A (en) * | 1992-01-15 | 1995-02-21 | E-Systems, Inc. | Triple orthogonally interleaed error correction system |
| US5457704A (en) * | 1993-05-21 | 1995-10-10 | At&T Ipm Corp. | Post processing method and apparatus for symbol reliability generation |
| US5968198A (en) * | 1996-08-16 | 1999-10-19 | Ericsson, Inc. | Decoder utilizing soft information output to minimize error rates |
| EP0991237A1 (en) * | 1998-09-30 | 2000-04-05 | TELEFONAKTIEBOLAGET L M ERICSSON (publ) | Multicarrier communication method with time-frequency differential encoding |
| US6490705B1 (en) * | 1998-10-22 | 2002-12-03 | Lucent Technologies Inc. | Method and apparatus for receiving MPEG video over the internet |
| US6731700B1 (en) * | 2001-01-04 | 2004-05-04 | Comsys Communication & Signal Processing Ltd. | Soft decision output generator |
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2004
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| CN102282846A (en) * | 2009-01-19 | 2011-12-14 | Lg电子株式会社 | Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal |
| CN102282846B (en) * | 2009-01-19 | 2015-05-06 | Lg电子株式会社 | Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal |
| CN104883333A (en) * | 2009-01-19 | 2015-09-02 | Lg电子株式会社 | Apparatus For Transmitting And Receiving A Signal And Method Of Transmitting And Receiving A Signal |
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| CN107707332A (en) * | 2011-05-18 | 2018-02-16 | 松下电器产业株式会社 | Parallel bit interleaver |
| CN107104678B (en) * | 2011-05-18 | 2020-07-07 | 松下电器产业株式会社 | Transmission method, transmission device, reception method, and reception device |
| US10886946B2 (en) | 2011-05-18 | 2021-01-05 | Panasonic Corporation | Parallel bit interleaver |
| US11070236B2 (en) | 2011-05-18 | 2021-07-20 | Panasonic Corporation | Parallel bit interleaver |
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| US11894861B2 (en) | 2011-05-18 | 2024-02-06 | Panasonic Holdings Corporation | Parallel bit interleaver |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100461116C (en) | 2009-02-11 |
| CN100483952C (en) | 2009-04-29 |
| CN1799201A (en) | 2006-07-05 |
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