CN1873562A - Multichannel intelligent PID controller based on FPGA - Google Patents
Multichannel intelligent PID controller based on FPGA Download PDFInfo
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Abstract
The invention relates to a single channel parameter fuzzy self-setting PID controller. The chief controller module connects to A/D converting control module, error calculating module, fuzzy control output module, PID arithmetic module, parameter setting module, and serial port communication module. The error calculating module connects to A/D converting control module, serial communication module, data transforming module, and address decoding module. The parameter setting module connects to fuzzy control output module and PID arithmetic module that connects to data transforming module. The external connects to A/D transforming module and the controller object. The multi-channel parameter fuzzy self-setting PID controller shares clock, host and key. The invention has the advantages of high process speed, small volume, low energy consumption and convenient to update.
Description
One, technical field
The invention belongs to multichannel intelligent PID control technology field.Relate in particular to a kind of multichannel intelligent PID controller based on FPGA.
Two, background technology
Intelligent PID controller is that Based Intelligent Control is controlled both combination with conventional PID.At first, it possesses the ability of self study, self-adaptation, self-organization, can automatically identification controlled process parameter, automatic adjusting controlled variable, can adapt to the variation of controlled process parameter; Secondly, it has again that conventional PID controller architecture is simple, strong robustness, reliability height, is characteristics such as the field engineering designer is familiar with.Thereby make Intelligent PID Control become a kind of comparatively ideal control device of numerous process control.
At present, the multi-channel digital intelligent PID controller adopts single-chip microcomputer, PLC to realize mostly, for example: " pid parameter fuzzy adaptive controller " (CN1393746A, 2003), can online parameter adjust in real time the PID controller, be a complete intelligent PID control system, but this technology is to adopt software programming to realize, in the process that program is carried out, there is certain hysteresis phenomenon,, can not satisfies rate request than higher controlled device so real-time is relatively poor.The special-purpose pid parameter of employing is also arranged from adjusting module (Zhu Haifeng, Yang Zhi, Zhang Mingzhou. instrument with pid parameter from adjust design of Controller and application. instrument and meter for automation, 2005 26 7 phases of volume), pid parameter wherein is the integration module of a special use carrying among the Modicon PLC from the module of adjusting, because this module is integrated among the PLC, its dirigibility is relatively poor, the user must select special PLC for use when selecting this module for use, and volume is big, power consumption is high, be difficult for upgrading, the product life cycle is short, the cost height.
Three, summary of the invention
Task of the present invention provides that a kind of processing speed is fast, volume is little, low in energy consumption, upgrading is easily based on the multichannel intelligent PID controller of FPGA.
For finishing above-mentioned task, the technical solution adopted in the present invention is: a plurality of single channel parameter fuzzy are integrated among a slice FPGA from the Tuning PID Controller device, each single channel parameter fuzzy from the Tuning PID Controller device respectively with separately independently the A/D modular converter be connected with controlled device, a plurality of single channel parameter fuzzy are connected with clock, host computer and keyboard respectively from the Tuning PID Controller device;
The single channel parameter fuzzy is made up of A/D conversion and control module, error calculating module, address decoding module, fuzzy control output module, master controller module, pid algorithm module, parameter setting module, numerical value modular converter and serial communication modular from the Tuning PID Controller device, above-mentioned module is to generate with the Hardware Description Language VHDL programming, and the annexation between each module is: A/D conversion and control module links to each other with error calculating module with the master controller module respectively; Error calculating module links to each other with A/D conversion and control module, master controller module, serial communication modular, numerical value modular converter and address decoding module respectively; The address decoding module links to each other with the fuzzy control output module with error calculating module respectively; The fuzzy control output module links to each other with parameter setting module with address decoding module, master controller module respectively; The pid algorithm module links to each other with master controller module, numerical value modular converter, parameter setting module respectively; Serial communication modular links to each other with error calculating module with the master controller module; The numerical value modular converter links to each other with error calculating module with the pid algorithm module; Parameter setting module links to each other with fuzzy control output module, pid algorithm module and master controller module; The master controller module links to each other with serial communication modular with A/D conversion and control module, error calculating module, fuzzy control output module, pid algorithm module, parameter setting module respectively.
The single channel parameter fuzzy from the structure of each module of Tuning PID Controller device is respectively:
A/D conversion and control module is made up of fifo cache module and A/D control module, the written allowance signal end rd of A/D control module, read to allow signal end wr, full end and empty end to link to each other with rdreq end, wrreq end, full end and the empty end of fifo cache module respectively, the fifoclk end of fifo cache module links to each other with the clk end of A/D control module, and the fifo cache module is 256 bytes; The clkin end of A/D control module links to each other with the ad_clk end of master controller module, the clkout end of A/D control module, ad_oe end link to each other with clk, the oe end of A/D modular converter respectively, data output end d0～the d7 of A/D modular converter links to each other with the data input pin i0～i7 of fifo cache module, and the data output end q0～q7 of fifo cache module links to each other with the input end u0～u7 of error calculating module.
Data input pin r0～the r7 of error calculating module is connected with the data output end dout0～dout7 of serial communication modular, data output end q0～the q7 of the fifo cache module in the data input pin u0～u7 of error calculating module and the A/D conversion and control module links to each other, the input end clkin of error calculating module links to each other with date_out8 with the output terminal e_clk of master controller module respectively with reset, data output end e0～the e8 of error calculating module links to each other the data output end eout0～eout8 of error calculating module respectively with ec0～ec8 with dinec0～dinec8 with the data input pin dine0～dine8 of address decoding module, ecout0～ecout8, eccut0～eccout8 and uout0～uout7 respectively with the data input pin eto0～eto8 of numerical value modular converter, ecto0～ecto8, eccto0～eccto8 links to each other with uto0～uto7.
Data input pin dine0～the dine8 of address decoding module links to each other with ec0～ec8 with the data output end e0～e8 of error calculating module respectively with dinec0～dinec8, and address decoding module output terminal code0～code5 links to each other with the input end address0～address5 of fuzzy control output module.
Input end address0～the address5 of fuzzy control output module links to each other with the output terminal code0～code5 of address decoding module, the input end clkin of fuzzy control output module links to each other with the Ausgang _ clk of master controller module, and output terminal qkp0～qkp7, the qki0～qki7 of fuzzy control output module links to each other with kdin0～kdin7 with input end kpin0～kpin7, the kiin0～kiin7 of parameter setting module respectively with qkd0～qkd7.
The master controller module is made up of clock frequency division module and control module, and the output terminal control_out of clock frequency division module links to each other with the input end control_in of control module; The input end clk_in of clock frequency division module links to each other with clock, the output terminal ad_clk of clock frequency division module links to each other with the input end clkin of A/D conversion and control module, the output terminal uart_clk of clock frequency division module links to each other with the input end clkin of serial communication modular, the output terminal e_clk of clock frequency division module links to each other with the input end clkin of error calculating module, Ausgang _ the clk of clock frequency division module links to each other with the input end clkin of fuzzy control output module, output end p _ the clk of clock frequency division module links to each other with the input end clkin of parameter setting module, the output terminal c_clk of clock frequency division module links to each other with the input end clkin of pid algorithm module, input end date_in0～the date_in9 of control module links to each other with the output terminal date0～date9 of keyboard, output terminal date_out0～the date_out7 of control module respectively with the input end kp0～kp7 of parameter setting module, ki0～ki7 links to each other with kd0～kd7, the output terminal date_out8 of control module links to each other with the input end reset of error calculating module, and the output terminal date_out9 of control module links to each other with the input end load of parameter setting module.
Pid algorithm module input kp0～kp11, ki0～ki17 and kd0～kd11 respectively with the output terminal kp_out0～kp_out11 of parameter setting module, ki_out0～ki_out17 links to each other with kd_out0～kd_out11, pid algorithm module input e_in0～e_in8, ec_in0～ec_in8, ecc_in0～ecc_in8 and u_in0～u_in7 respectively with the output terminal e0～e8 of numerical value modular converter, ec0～ec8, ecc0～ecc8 links to each other with u0～u7, pid algorithm module input clkin links to each other with the output terminal c_clk of master controller module, and pid algorithm module output terminal u_out0～u_out16 links to each other with controlled device.
Input end kp0～the kp7 of parameter setting module, ki0～ki7 all links to each other with the output terminal date_out0～date_out7 of master controller module with kd0～kd7, input end kpin0～the kpin7 of parameter setting module, kiin0～kiin7 and kdin0～kdin7 respectively with the output terminal qkp0～qkp7 of fuzzy control output module, qki0～qki7 links to each other with qkd0～qkd7, the input end clkin of parameter setting module links to each other the output terminal kp_out0～kp_out11 of parameter setting module respectively with load with date_out9 with the output end p _ clk of master controller module, ki_out0～ki_out17 and kd_out0～kd_out11 respectively with the input end kp0～kp11 of pid algorithm module, ki0～ki17 links to each other with kd0～kd11.
Input end eto0～eto8, ecto0～ecto8, eccto0～eccto8 and the uto0～uto7 of numerical value modular converter links to each other with data output end eout0～eout8, ecout0～ecout8, eccout0～eccout8 and the uout0～uout7 of error calculating module respectively, and output terminal e0～e8, ec0～ec8, ecc0～ecc8 and the u0～u7 of numerical value modular converter links to each other with input end e_in0～e_in8, ec_in0～ec_in8, ecc_in0～ecc_in8 and the u_in0～u_in7 of pid algorithm module respectively.
Serial communication modular is made up of baud rate generation module, receiver module and sending module, and the baud rate output terminal bd_out of baud rate generation module links to each other with the baud rate input end rxd_bd of receiver module and the baud rate input end txd_bd of sending module respectively; The clkin end of baud rate generation module links to each other with the uart_clk of master controller module, the rxd end of receiver module links to each other by the txd of Serial Port Line with the host computer serial ports, data output end dout0～the dout7 of receiver module links to each other with the r0～r7 of error calculating module, and the txd end of sending module links to each other with the rxd end of host computer serial ports by Serial Port Line.
Because adopt technique scheme, the present invention utilizes the characteristic of FPGA, utilizes VHDL language to design from the Tuning PID Controller device with modular design idea a single channel parameter fuzzy, form IP kernel; Then a plurality of such IP kernels are integrated among the FPGA, each module independent parallel work connects the parallel control that realizes a plurality of passages by signal wire between the module.Owing to adopt hardware circuit design, its processing speed height; Simultaneously,, make that the dirigibility of design is good, be convenient to upgrading because design is the thought that adopts the software implementation design; A plurality of single channel intelligent PID controllers are integrated in a slice FPGA and go up realization, so system bulk is little, in light weight, low in energy consumption.
Four, description of drawings
Fig. 1 is a kind of structural representation of the present invention;
Fig. 2 be among Fig. 1 the single channel parameter fuzzy from Tuning PID Controller device [3] synoptic diagram;
Fig. 3 is the structural representation of A/D conversion and control module [8] among Fig. 2;
Fig. 4 is the structural representation of error calculating module among Fig. 2 [9];
Fig. 5 is the structural representation of address decoding module [10] among Fig. 2;
Fig. 6 is the structural representation of fuzzy control output module [11] among Fig. 2;
Fig. 7 is the structural representation of master controller module [12] among Fig. 2;
Fig. 8 is the structural representation of pid algorithm module [13] among Fig. 2;
Fig. 9 is the structural representation of parameter setting module among Fig. 2 [14];
Figure 10 is the structural representation of numerical value modular converter [15] among Fig. 2;
Figure 11 is the structural representation of serial communication modular among Fig. 2 [16].
Five, embodiment
Below in conjunction with accompanying drawing, the invention will be further described: a kind of multichannel intelligent PID controller based on FPGA as shown in Figure 1, is integrated in a slice FPGA[4 with a plurality of single channel parameter fuzzy from Tuning PID Controller device [3]] in.Each single channel parameter fuzzy from Tuning PID Controller device [3] respectively with separately independently A/D modular converter [1] be connected with controlled device [2], a plurality of single channel parameter fuzzy are connected with clock [5], host computer [6] and keyboard [7] respectively from Tuning PID Controller device [3].
The single channel parameter fuzzy from Tuning PID Controller device [3] as shown in Figure 2, form by A/D conversion and control module [8], error calculating module [9], address decoding module [10], fuzzy control output module [11], master controller module [12], pid algorithm module [13], parameter setting module [14], numerical value modular converter [15] and serial communication modular [16], above-mentioned module is to generate with the Hardware Description Language VHDL programming, and concrete structure is: A/D conversion and control module [8] links to each other with error calculating module [9] with master controller module [12] respectively; Error calculating module [9] links to each other with A/D conversion and control module [8], master controller module [12], serial communication modular [16], numerical value modular converter [15] and address decoding module [10] respectively; Address decoding module [10] links to each other with fuzzy control output module [11] with error calculating module [9] respectively; Fuzzy control output module [11] links to each other with address decoding module [10], master controller module [12] and parameter setting module [14] respectively; Pid algorithm module [13] links to each other with master controller module [12], numerical value modular converter [15] and parameter setting module [14] respectively; Serial communication modular [16] links to each other with error calculating module [9] with master controller module [12]; Numerical value modular converter [15] links to each other with error calculating module [9] with pid algorithm module [13]; Parameter setting module [14] links to each other with fuzzy control output module [11], pid algorithm module [13] and master controller module [12]; Master controller module [12] links to each other with A/D conversion and control module [8], error calculating module [9], fuzzy control output module [11], pid algorithm module [13], parameter setting module [14] and serial communication modular [16] respectively.
The single channel parameter fuzzy from Tuning PID Controller device [3] principle of work is: A/D modular converter [1] will be worked with A/D conversion and control module [8] is collaborative, convert the analog quantity of collection value to digital quantity, and output in the error calculating module [9], given input quantity is delivered in the error calculating module [9] by serial communication modular [16], this specified rate is made comparisons with the collection value after the A/D conversion, calculate the error between collection value and the specified rate, the rate of change of error rate and error rate, three output quantities for the data sync of back, in error calculating module [9], be sent to respectively in the address decoding module [10] and numerical value modular converter [15] of back behind several clocks of time-delay, the sum of errors error rate of delivering in the address decoding module [10] produces the address that is used to inquire about fuzzy control output module [11] through address decoding module [10] decoding, deliver to the error in the numerical value modular converter [15], error rate, the output quantity of the rate of change of error rate and the last one-period of collection is converted into integer by original bit vector, output in the pid algorithm module [13], fuzzy control output module [11] is one and sets up good rule query table, that storage is three parameter kp of the pairing PID controller of sum of errors error rate in each sampling period in this table, ki, the increment of kd, the increment of three parameters in parameter setting module [14] with three parameter kp that produce the PID controller by the given initial value addition of keyboard [7], ki, the currency of kd, this value is output in the pid algorithm module [13] and is used for the increment type PID computing, be stored in the storage unit initial value simultaneously as next cycle, be shown below, Kp wherein, Ki, Kd is a currency, Kp ', Ki ' and Kd ' are the parameter in last sampling period, they are as the initial value of current period and the output quantity Δ Kp of fuzzy control output module [4], Δ Ki and Δ Kd addition respectively obtain the parameter of current period, that is:
Kp＝Kp′+ΔKp
Li＝Ki′+ΔKi
Kd＝Kd′+ΔKd
Kp, ki, kd output to pid algorithm module [13], finish the increment type PID computing by the rate of change of the error of error calculating module [9] output, error rate, error rate with three parameters in this module.
Δu(k)＝Kp[e(k)-e(k-1)]+Kie(k)+Kd[e(k)-2e(k-1)+e(k-2)]
The sampled value addition of the last one-period of this increment and output quantity can calculate the current controlled quentity controlled variable of exporting to controlled device [2].
u(k)＝u(k-1)+Δu(k)
The user can set the initial value of kp, ki, three parameters of kd by keyboard [7], and given input quantity can be set by host computer by serial communication modular.
The single channel parameter fuzzy from the concrete structure of each module of Tuning PID Controller device [3] is respectively:
The structure of A/D conversion and control module [8] as shown in Figure 3, form by fifo cache module [17] and A/D control module [18], the written allowance signal end rd of A/D control module [18], read to allow signal end wr, full end and empty end to link to each other with rdreq end, wrreq end, full end and the empty end of fifo cache module [17] respectively, the fifoclk end of fifo cache module [17] links to each other with the clk end of A/D control module [18], and fifo cache module [17] is 256 bytes; The clkin end of A/D control module [18] links to each other with the ad_clk end of master controller module [12], the clkout end of A/D control module [18], ad_oe end link to each other with clk, the oe end of A/D modular converter [1] respectively, data output end d0～the d7 of A/D modular converter [1] links to each other with the data input pin i0～i7 of fifo cache module [17], and the data output end q0～q7 of fifo cache module [17] links to each other with the input end u0～u7 of error calculating module [9].
The structure of error calculating module [9] as shown in Figure 4, data input pin r0～the r7 of error calculating module [9] is connected with the data output end dout0～dout7 of serial communication modular [16], data output end q0～the q7 of the fifo cache module [17] in the data input pin u0～u7 of error calculating module [9] and the A/D conversion and control module [8] links to each other, the input end clkin of error calculating module [9] links to each other with date_out8 with the output terminal e_clk of master controller module [12] respectively with reset, data output end e0～the e8 of error calculating module [9] links to each other the data output end eout0～eout8 of error calculating module [9] with the data input pin dine0～dine8 of address decoding module [10] respectively with ec0～ec8 with dinec0～dinec8, ecout0～ecout8, eccut0～eccout8 and uout0～uout7 respectively with the data input pin eto0～eto8 of numerical value modular converter [15], ecto0～ecto8, eccto0～eccto8 links to each other with uto0～uto7.
The structure of address decoding module [10] as shown in Figure 5, data input pin dine0～the dine8 of address decoding module [10] links to each other with ec0～ec8 with the data output end e0～e8 of error calculating module [9] respectively with dinec0～dinec8, and address decoding module [10] output terminal code0～code5 links to each other with the input end address0～address5 of fuzzy control output module [11].
The structure of fuzzy control output module [11] as shown in Figure 6, input end address0～the address5 of fuzzy control output module [11] links to each other with the output terminal code0～code5 of address decoding module [10], the input end clkin of fuzzy control output module [11] links to each other with the Ausgang _ clk of master controller module [12], and output terminal qkp0～qkp7, the qki0～qki7 of fuzzy control output module [11] links to each other with kdin0～kdin7 with input end kpin0～kpin7, the kiin0～kiin7 of parameter setting module [14] respectively with qkd0～qkd7.
The structure of master controller module [12] is made up of clock frequency division module [19] and control module [20] as shown in Figure 7, and the output terminal control_out of clock frequency division module [19] links to each other with the input end control_in of control module [20]; The input end clk_in of clock frequency division module [19] links to each other with clock [5], the output terminal ad_clk of clock frequency division module [19] links to each other with the input end clkin of A/D conversion and control module [8], the output terminal uart_clk of clock frequency division module [19] links to each other with the input end clkin of serial communication modular [16], the output terminal e_clk of clock frequency division module [19] links to each other with the input end clkin of error calculating module [9], Ausgang _ the clk of clock frequency division module [19] links to each other with the input end clkin of fuzzy control output module [11], output end p _ the clk of clock frequency division module [19] links to each other with the input end clkin of parameter setting module [14], the output terminal c_clk of clock frequency division module [19] links to each other with the input end clkin of pid algorithm module [13], input end date_in0～the date_in9 of control module [20] links to each other with the output terminal date0～date9 of keyboard [7], output terminal date_out0～the date_out7 of control module [20] respectively with the input end kp0～kp7 of parameter setting module [14], ki0～ki7 links to each other with kd0～kd7, the output terminal date_out8 of control module [20] links to each other with the input end reset of error calculating module [9], and the output terminal date_out9 of control module [20] links to each other with the input end load of parameter setting module [14].
The structure of pid algorithm module [13] as shown in Figure 8, pid algorithm module [13] input end kp0～kp11, ki0～ki17 and kd0～kd11 respectively with the output terminal kp_out0～kp_out11 of parameter setting module [14], ki_out0～ki_out17 links to each other with kd_out0～kd_out11, pid algorithm module [13] input end e_in0～e_in8, ec_in0～ec_in8, ecc_in0～ecc in8 and u_in0～u_in7 respectively with the output terminal e0～e8 of numerical value modular converter [15], ec0～ec8, ecc0～ecc8 links to each other with u0～u7, pid algorithm module [13] input end clkin links to each other with the output terminal c_clk of master controller module [12], and pid algorithm module [13] output terminal u_out0～u_out16 links to each other with controlled device [2].
The structure of parameter setting module [14] as shown in Figure 9, input end kp0～the kp7 of parameter setting module [14], ki0～ki7 all links to each other with the output terminal date_out0～date_out7 of master controller module [12] with kd0～kd7, input end kpin0～the kpin7 of parameter setting module [14], kiin0～kin7 and kdin0～kdin7 respectively with the output terminal qkp0～qkp7 of fuzzy control output module [11], qki0～qki7 links to each other with qkd0～qkd7, the input end clkin of parameter setting module [14] links to each other the output terminal kp_out0～kp_out11 of parameter setting module [14] with the output end p _ clk of master controller module [12] respectively with load with date_out9, ki_out0～ki_out17 and kd_out0～kd_out11 respectively with the input end kp0～kp11 of pid algorithm module [13], ki0～ki17 links to each other with kd0～kd11.
The structure of numerical value modular converter [15] as shown in figure 10, input end eto0～the eto8 of numerical value modular converter [15], ecto0～ecto8, eccto0～eccto8 and uto0～uto7 respectively with the data output end eout0～eout8 of error calculating module [9], ecout0～ecout8, eccout0～eccout8 links to each other with uout0～uout7, the output terminal e0～e8 of numerical value modular converter [15], ec0～ec8, ecc0～ecc8 and u0～u7 respectively with the input end e_in0～e_in8 of pid algorithm module [13], ec_in0～ec_in8, ecc_in0～ecc_in8 links to each other with u_in0～u_in7.
The structure of serial communication modular [16] as shown in figure 11, serial communication modular [16] is made up of baud rate generation module [21], receiver module [22] and sending module [23], and the baud rate output terminal bd_out of baud rate generation module [21] links to each other with the baud rate input end rxd_bd of receiver module [22] and the baud rate input end txd_bd of sending module [23] respectively; The clkin end of baud rate generation module [21] links to each other with the uart_clk of master controller module [12], the rxd end of receiver module [22] links to each other by the txd of Serial Port Line with host computer [6] serial ports, data output end dout0～the dout7 of receiver module [22] links to each other with the data input pin r0～r7 of error calculating module [9], and the txd end of sending module [23] links to each other with the rxd end of host computer [6] serial ports by Serial Port Line.
Claims (10)
1, a kind of multichannel intelligent PID controller based on FPGA, it is characterized in that a plurality of single channel parameter fuzzy are integrated in a slice FPGA[4 from Tuning PID Controller device [3]] in, each single channel parameter fuzzy from Tuning PID Controller device [3] respectively with separately independently A/D modular converter [1] be connected with controlled device [2], a plurality of single channel parameter fuzzy are connected with clock [5], host computer [6] and keyboard [7] respectively from Tuning PID Controller device [3];
The single channel parameter fuzzy is made up of A/D conversion and control module [8], error calculating module [9], address decoding module [10], fuzzy control output module [11], master controller module [12], pid algorithm module [13], parameter setting module [14], numerical value modular converter [15] and serial communication modular [16] from Tuning PID Controller device [3], above-mentioned module is to generate with the Hardware Description Language VHDL programming, and the annexation between each module is: A/D conversion and control module [8] links to each other with error calculating module [9] with master controller module [12] respectively; Error calculating module [9] links to each other with A/D conversion and control module [8], master controller module [12], serial communication modular [16], numerical value modular converter [15] and address decoding module [10] respectively; Address decoding module [10] links to each other with fuzzy control output module [11] with error calculating module [9] respectively; Fuzzy control output module [11] links to each other with address decoding module [10], master controller module [12] and parameter setting module [14] respectively; Pid algorithm module [13] links to each other with master controller module [12], numerical value modular converter [15], parameter setting module [14] respectively; Serial communication modular [16] links to each other with error calculating module [9] with master controller module [12]; Numerical value modular converter [15] links to each other with error calculating module [9] with pid algorithm module [13]; Parameter setting module [14] links to each other with fuzzy control output module [11], pid algorithm module [13] and master controller module [12]; Master controller module [12] links to each other with A/D conversion and control module [8], error calculating module [9], fuzzy control output module [11], pid algorithm module [13], parameter setting module [14] and serial communication modular [16] respectively.
2, the multichannel intelligent PID controller based on FPGA according to claim 1, it is characterized in that described A/D conversion and control module [8] is made up of fifo cache module [17] and A/D control module [18], the written allowance signal end rd of A/D control module [18], read to allow signal end wr, full end and empty end to link to each other with rdreq end, wrreq end, full end and the empty end of fifo cache module [17] respectively, the fifoclk end of fifo cache module [17] links to each other with the clk end of A/D control module [18], and fifo cache module [17] is 256 bytes; The clkin end of A/D control module [18] links to each other with the ad_clk end of master controller module [12], the clkout end of A/D control module [18], ad_oe end link to each other with clk, the oe end of A/D modular converter [1] respectively, data output end d0～the d7 of A/D modular converter [1] links to each other with the data input pin i0～i7 of fifo cache module [17], and the data output end q0～q7 of fifo cache module [17] links to each other with the input end u0～u7 of error calculating module [9].
3, multichannel intelligent PID controller based on FPGA according to claim 1, data input pin r0～the r7 that it is characterized in that described error calculating module [9] is connected with the data output end dout0～dout7 of serial communication modular [16], data output end q0～the q7 of the fifo cache module [17] in the data input pin u0～u7 of error calculating module [9] and the A/D conversion and control module [8] links to each other, the input end clkin of error calculating module [9] links to each other with date_out8 with the output terminal e_clk of master controller module [12] respectively with reset, data output end e0～the e8 of error calculating module [9] links to each other the data output end eout0～eout8 of error calculating module [9] with the data input pin dine0～dine8 of address decoding module [10] respectively with ec0～ec8 with dinec0～dinec8, ecout0～ecout8, eccut0～eccout8 and uout0～uout7 respectively with the data input pin eto0～eto8 of numerical value modular converter [15], ecto0～ecto8, eccto0～eccto8 links to each other with uto0～uto7.
4, the multichannel intelligent PID controller based on FPGA according to claim 1, data input pin dine0～the dine8 that it is characterized in that described address decoding module [10] links to each other with ec0～ec8 with the data output end e0～e8 of error calculating module [9] respectively with dinec0～dinec8, and address decoding module [10] output terminal code0～code5 links to each other with the input end address0～address5 of fuzzy control output module [11].
5, multichannel intelligent PID controller based on FPGA according to claim 1, input end address0～the address5 that it is characterized in that described fuzzy control output module [11] links to each other with the output terminal code0～code5 of address decoding module [10], the input end clkin of fuzzy control output module [11] links to each other with the Ausgang _ clk of master controller module [12], the output terminal qkp0～qkp7 of fuzzy control output module [11], qki0～qki7 and qkd0～qkd7 respectively with the input end kpin0～kpin7 of parameter setting module [14], kiin0～kiin7 links to each other with kdin0～kdin7.
6, the multichannel intelligent PID controller based on FPGA according to claim 1, it is characterized in that described master controller module [12] is made up of clock frequency division module [19] and control module [20], the output terminal control_out of clock frequency division module [19] links to each other with the input end control_in of control module [20]; The input end clk_in of clock frequency division module [19] links to each other with clock [5], the output terminal ad_clk of clock frequency division module [19] links to each other with the input end clkin of A/D conversion and control module [8], the output terminal uart_clk of clock frequency division module [19] links to each other with the input end clkin of serial communication modular [16], the output terminal e_clk of clock frequency division module [19] links to each other with the input end clkin of error calculating module [9], Ausgang _ the clk of clock frequency division module [19] links to each other with the input end clkin of fuzzy control output module [11], output end p _ the clk of clock frequency division module [19] links to each other with the input end clkin of parameter setting module [14], the output terminal c_clk of clock frequency division module [19] links to each other with the input end clkin of pid algorithm module [13], input end date_in0～the date_in9 of control module [20] links to each other with the output terminal date0～date9 of keyboard [7], output terminal date_out0～the date_out7 of control module [20] respectively with the input end kp0～kp7 of parameter setting module [14], ki0～ki7 links to each other with kd0～kd7, the output terminal date_out8 of control module [20] links to each other with the input end reset of error calculating module [9], and the output terminal date_out9 of control module [20] links to each other with the input end load of parameter setting module [14].
7, multichannel intelligent PID controller based on FPGA according to claim 1, it is characterized in that described pid algorithm module [13] input end kp0～kp11, ki0～ki17 and kd0～kd11 respectively with the output terminal kp_out0～kp_out11 of parameter setting module [14], ki_out0～ki_out17 links to each other with kd_out0～kd_out11, pid algorithm module [13] input end e_in0～e_in8, ec_in0～ec_in8, ecc_in0～ecc_in8 and u_in0～u_in7 respectively with the output terminal e0～e8 of numerical value modular converter [15], ec0～ec8, ecc0～ecc8 links to each other with u0～u7, pid algorithm module [13] input end clkin links to each other with the output terminal c_clk of master controller module [12], and pid algorithm module [13] output terminal u_out0～u_out16 links to each other with controlled device [2].
8, multichannel intelligent PID controller based on FPGA according to claim 1, input end kp0～the kp7 that it is characterized in that described parameter setting module [14], ki0～ki7 all links to each other with the output terminal date_out0～date_out7 of master controller module [12] with kd0～kd7, input end kpin0～the kpin7 of parameter setting module [14], kiin0～kiin7 and kdin0～kdin7 respectively with the output terminal qkp0～qkp7 of fuzzy control output module [11], qki0～qki7 links to each other with qkd0～qkd7, the input end clkin of parameter setting module [14] links to each other the output terminal kp_out0～kp_out11 of parameter setting module [14] with the output end p _ clk of master controller module [12] respectively with load with date_out9, ki_out0～ki_out17 and kd_out0～kd_out11 respectively with the input end kp0～kp11 of pid algorithm module [13], ki0～ki17 links to each other with kd0～kd11.
9, multichannel intelligent PID controller based on FPGA according to claim 1, input end eto0～the eto8 that it is characterized in that described numerical value modular converter [15], ecto0～ecto8, eccto0～eccto8 and uto0～uto7 respectively with the data output end eout0～eout8 of error calculating module [9], ecout0～ecout8, eccout0～eccout8 links to each other with uout0～uout7, the output terminal e0～e8 of numerical value modular converter [15], ec0～ec8, ecc0～ecc8 and u0～u7 respectively with the input end e_in0～e_in8 of pid algorithm module [13], ec_in0～ec_in8, ecc_in0～ecc_in8 links to each other with u_in0～u_in7.
10, the multichannel intelligent PID controller based on FPGA according to claim 1, it is characterized in that described serial communication modular [16] is made up of baud rate generation module [21], receiver module [22] and sending module [23], the baud rate output terminal bd_out of baud rate generation module [21] links to each other with the baud rate input end rxd_bd of receiver module [22] and the baud rate input end txd_bd of sending module [23] respectively; The clkin end of baud rate generation module [21] links to each other with the uart_clk of master controller module [12], the rxd end of receiver module [22] links to each other by the txd of Serial Port Line with host computer [6] serial ports, data output end dout0～the dout7 of receiver module [22] links to each other with the data input pin r0～r7 of error calculating module [9], and the txd end of sending module [23] links to each other with the rxd end of host computer [6] serial ports by Serial Port Line.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102426417A (en) * | 2011-12-13 | 2012-04-25 | 中冶南方（武汉）自动化有限公司 | PI (Proportional Integral) parameter mixed setting method |
| CN102611516A (en) * | 2012-01-17 | 2012-07-25 | 成都府河电力自动化成套设备有限责任公司 | Method and device for generating high-precision synchronous clock |
| CN102662322A (en) * | 2012-04-10 | 2012-09-12 | 西华大学 | FPGA (field programmable gate array) processor and PID (proportion integration differentiation) membrane optimization neural network controller |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102426417A (en) * | 2011-12-13 | 2012-04-25 | 中冶南方（武汉）自动化有限公司 | PI (Proportional Integral) parameter mixed setting method |
| CN102426417B (en) * | 2011-12-13 | 2013-10-02 | 中冶南方（武汉）自动化有限公司 | PI (Proportional Integral) parameter mixed setting method |
| CN102611516A (en) * | 2012-01-17 | 2012-07-25 | 成都府河电力自动化成套设备有限责任公司 | Method and device for generating high-precision synchronous clock |
| CN102662322A (en) * | 2012-04-10 | 2012-09-12 | 西华大学 | FPGA (field programmable gate array) processor and PID (proportion integration differentiation) membrane optimization neural network controller |
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