CN1870099A - Plasma display and driver - Google Patents
Plasma display and driver Download PDFInfo
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- CN1870099A CN1870099A CNA2006100095929A CN200610009592A CN1870099A CN 1870099 A CN1870099 A CN 1870099A CN A2006100095929 A CNA2006100095929 A CN A2006100095929A CN 200610009592 A CN200610009592 A CN 200610009592A CN 1870099 A CN1870099 A CN 1870099A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
- G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery
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Abstract
A plasma display includes: a plurality of electrodes extending in one direction; at least one inductor coupled between the plurality of electrodes and a power recovery power source; a first transistor coupled either between the at least one inductor and the electrode or between the at least one inductor and the power recovery power source; a second transistor coupled either between the at least one inductor and the electrode or between the at least one inductor and the power recovery power source; and a gate driving circuit adapted to supply either a high or low level voltage to a gate of either the first or second transistor, and including a Light Emitting Diode (LED) adapted to emit light in response to a current flow to the gate, and a first diode coupled to the LED in reverse parallel.
Description
Technical field
The present invention relates to plasma scope and driver.
Background technology
Plasma scope uses the plasma that generates by gas discharge to come the flat-panel monitor of character display or image.It comprises Plasmia indicating panel (PDP), and wherein the size according to it provides tens of to millions of pixels with matrix form.
According to the typical method that drives PDP, each frame is divided into a plurality of sons field with corresponding brightness weights, and display image is represented by this combination of a little.Each son field has reset period, address period and keeps the phase.
Reset period is used for the state of the corresponding arc chamber of initialization, so that the addressing operation on this arc chamber.Address period is used to select the chamber (that is, the chamber that be switched on or turn-off) that is switched on/turn-offs, and the wall electric charge is run up on the chamber (that is the chamber that, is addressed) of connection.The phase of keeping is used for the corresponding cycle of weights of keeping discharge one segment length and corresponding son field to the chamber that is addressed.
When keeping pulse and alternately offer two electrodes, can cause such discharge of keeping.Be applied to this two electrodes in order to keep pulse, the power that extra reactive power must be provided and be used to keep discharge, this is because these two electrodes play the electric capacity load effect of (hereinafter, being called panel capacitor).Therefore, typically keep the discharge driving circuit and comprise the power restoring circuit that is used to recover with multiplexing reactive power.
Yet, when not having the driving power restoring circuit, be used to provide the switch of keeping pulse to damage owing to the heat that direct-cut operation produced by switch, this is because recover also still to generate to keep discharge even without carrying out power.
Therefore, need provide a kind of method that easily determines whether to drive the power restoring circuit.
Summary of the invention
In the process of the plasma scope of making great efforts to provide advantage and driver, made the present invention with fault of easily determining the power restoring circuit.
Example plasma display apparatus according to one embodiment of the invention comprises: a plurality of electrodes, extend in one direction; At least one inductance is connected between a plurality of electrodes and the power recovery power source; The first transistor is connected between at least one inductance and the electrode, perhaps is connected between at least one inductance and the power recovery power source; Transistor seconds is connected between at least one inductance and the electrode, perhaps is connected between at least one inductance and the power recovery power source; And gate driver circuit, be adapted for the grid that height or low level voltage to the first or transistor seconds are provided, and comprise light emitting diode (LED), be adapted in response to the electric current that flows to grid luminous; And first diode, be connected with this LED reverse parallel connection.
This gate driver circuit preferably also comprises amplifier, and it is adapted for signal output high level voltage or low level voltage in response to oxide-semiconductor control transistors; And LED and first diode preferably are connected in parallel between the grid of this amplifier and the first transistor or transistor seconds.Gate driver circuit preferably also comprises first capacitor, and its first end is connected to amplifier, and second end is connected to first or the grid and the source electrode thereof of transistor seconds; And LED preferably is connected between this amplifier and the capacitor, perhaps is connected between amplifier and the grid.
LED preferably includes the anode that is connected to amplifier and is connected to first or the grid of transistor seconds and the negative electrode of source electrode thereof; And first diode preferably include the negative electrode that is connected to amplifier and be connected to first or the grid of transistor seconds and the anode of source electrode thereof.
Amplifier preferably includes the 3rd transistor and the 4th transistor, and they are connected and are adapted for first power supply that first voltage is provided and are adapted between the second source that second voltage is provided, and third and fourth transistor layout is a push-pull circuit; And this amplifier preferably be adapted for by push-pull circuit to first or the grid of transistor seconds driving voltage is provided.
One of third and fourth transistor preferably includes NPN transistor, and in third and fourth transistor another comprises the PNP transistor.
Plasma scope preferably also comprises: first resistance, be connected first capacitor second end and first or the grid of transistor seconds between; And second resistance, be connected first capacitor second end and first or the source electrode of transistor seconds between.
Plasma scope preferably also comprises second resistance, be connected first capacitor second end and first or the source electrode of transistor seconds between.Plasma scope preferably also comprises the 3rd resistance, is connected between first end and second source of first capacitor.
Plasma scope preferably also comprises the 3rd capacitor, and its first end is adapted for first voltage that first power supply is provided, and second end provides second voltage of second source; Second end is connected to first or the source electrode of transistor seconds, and the 3rd capacitor preferably is charged to and first voltage and second voltage between the corresponding voltage of difference.Plasma scope preferably also comprises second diode, is connected between first terminal and amplifier of the 3rd capacitor.
Plasma scope preferably also comprises: the 5th transistor is connected electrode and is adapted between the 3rd power supply that tertiary voltage is provided; And the 6th transistor, be connected electrode and be adapted between the 4th power supply that the 4th voltage that is lower than tertiary voltage is provided; This power recovery power source preferably is adapted for the voltage that is provided between tertiary voltage and the 4th voltage.The preferred voltage level of second voltage is identical with the voltage level of the 4th voltage.
First and second transistors preferably comprise body diode respectively, and this plasma display apparatus preferably also comprises: second diode is connected in series to the first transistor with the direction opposite with body diode in the first transistor; And the 3rd diode, be connected in series to transistor seconds with the direction opposite with the body diode of transistor seconds.
Example plasma display apparatus according to another embodiment of the present invention comprises: a plurality of electrodes, extend in one direction; At least one inductance is connected between a plurality of electrodes and the power recovery power source; The first transistor is connected between at least one inductance and the electrode, perhaps is connected between at least one inductance and the power recovery power source; Transistor seconds is connected between at least one inductance and the electrode, perhaps is connected between at least one inductance and the power recovery power source; And gate driver circuit, preferably be adapted for the grid that height or low level voltage to the first or transistor seconds are provided, and comprise light emitting diode (LED), preferably be connected first or the grid and source electrode of transistor seconds between, and preferably be adapted in response to the electric current that flows to grid luminous.
Gate driver circuit preferably also comprises amplifier, and it is adapted for signal output high level voltage or low level voltage in response to oxide-semiconductor control transistors; And wherein LED is connected between amplifier and the source electrode.This gate driver circuit preferably also comprises: first capacitor, and its first end is connected to amplifier, and second end is connected to first or the grid and the source electrode of transistor seconds; And first resistance, it preferably is connected to second end and first or the source electrode of transistor seconds of first capacitor.
The negative electrode of LED preferably is connected to first or the source electrode of transistor seconds, and the anode of LED is connected to second end of first capacitor.
Plasma scope preferably also comprises: second resistance, be connected first capacitor second end and first or the grid of transistor seconds between; And the 3rd resistance, be connected first capacitor second end and first or the source electrode of transistor seconds between.
The plasma scope evaluation method selecting optimal equipment also comprises second capacitor, be connected first capacitor second end and first or the source electrode of transistor seconds between.
Plasma scope preferably also comprises Zener (Zener) diode, its be connected LED and first or the source electrode of transistor seconds between.Preferably, the negative electrode of Zener diode is connected to the negative electrode of LED, and anode is connected to first or the source electrode of transistor seconds.
Plasma scope preferably also comprises the 4th resistance, is connected between first end and ground power supply of first capacitor.This plasma display preferably also comprises the 3rd capacitor, and its first end is adapted for first voltage that first power supply is provided high level power input end to amplifier, and second end provides the low-level of power input end of second voltage of second source to amplifier; This capacitor preferably charge into and first voltage and second voltage between the corresponding voltage of difference; And second end of capacitor preferably is connected to first or the source electrode of transistor seconds.
According to an alternative embodiment of the invention, a kind ofly be used to drive example driver and comprise with a plurality of plasma scopes at the upwardly extending electrode of single side: gate driver circuit, it comprises: at least one inductance is connected to a plurality of electrodes; The first transistor is connected at least one inductance, and is adapted for the voltage that increases the electrode place when the first transistor is connected; Transistor seconds is connected at least one inductance, and is adapted for the voltage that reduces the electrode place when transistor seconds is connected; Light emitting diode (LED) is connected to first or the grid of transistor seconds, and is adapted in response to first or the connection of transistor seconds and luminous; And diode, being connected to first or the grid of transistor seconds, this diode is connected with the LED reverse parallel connection.
Gate driver circuit preferably also comprises amplifier, and it is adapted for the signal of the connection that receives control first or transistor seconds, control output predetermined voltage, and control is luminous from LED.
This driver preferably also comprises: the 3rd transistor, and being adapted in response to the voltage at electrode place increases and connects, and the 3rd transistor preferably provides first voltage to electrode; And the 4th transistor, being adapted for voltage in response to the electrode place and reducing and connect, the 4th transistor preferably provides second voltage less than first voltage.This driver preferably also comprises: the 3rd transistor, and it is adapted in response to the voltage increase at electrode place and connects, and the 3rd transistor preferably provides first voltage to electrode; And the 4th transistor, it is adapted for voltage in response to the electrode place and reduces and connect, and the 4th transistor preferably provides second voltage less than first voltage.This driver preferably also comprises capacitor, and it is adapted for the voltage that charges between first voltage and second voltage, and this capacitor preferably is connected between the first transistor and the transistor seconds.This driver preferably also comprises capacitor, and it is adapted for the voltage that charges between first voltage and second voltage, and this capacitor preferably is connected between the first transistor and the transistor seconds.
Description of drawings
When considered in conjunction with the accompanying drawings, because by make the present invention's easy to understand more that becomes with reference to following detailed description, so the present invention is more fully understood and many advantages of the present invention will become more obvious, in the accompanying drawings, the identical identical or similar parts of Reference numeral indication, wherein:
Fig. 1 is the synoptic diagram according to the plasma scope of illustrated embodiments of the invention.
Fig. 2 is the interim drive waveforms view of keeping according to the plasma scope of example embodiment of the present invention.
Fig. 3 is the synoptic diagram of keeping the discharge driving circuit according to illustrated embodiments of the invention.
Fig. 4 is the synoptic diagram of keeping the discharge driving circuit according to another example embodiment of the present invention.
Fig. 5 is the view according to the drive waveforms of the power restoring circuit of example embodiment of the present invention.
Fig. 6 is the synoptic diagram according to the gate driver circuit of first example embodiment of the present invention.
Fig. 7 is the synoptic diagram according to the push-pull amplifier of illustrated embodiments of the invention.
Fig. 8 is the synoptic diagram according to the gate driver circuit of the present invention's second example embodiment.
Fig. 9 is the synoptic diagram according to the gate driver circuit of the present invention's the 3rd example embodiment.
Figure 10 is the synoptic diagram according to the gate driver circuit of the present invention's the 4th example embodiment.
Figure 11 is the synoptic diagram according to the gate driver circuit of the present invention's the 5th example embodiment.
Embodiment
In the following detailed description, illustrate and described example embodiment of the present invention in the mode that illustrates simply.As those skilled in the art will recognize, described embodiment can make amendment in various mode, and all modifications does not all break away from spirit of the present invention or scope.
Therefore, accompanying drawing and describe will be considered to be in essence illustrative and and unrestricted.In whole instructions, identical Reference numeral is represented components identical.
" wall electric charge " is the electric charge that forms and accumulate on this electrode on the wall of each electrode that approaches arc chamber.Though in fact the wall electric charge does not contact with electrode, and the wall electric charge is described as on electrode " formation " or " accumulation ".In addition, " wall voltage " is the electric potential difference that is formed on the wall of arc chamber by the wall electric charge.
The plasma scope and the driver of foundation example embodiment of the present invention are described below with reference to accompanying drawing.
Fig. 1 is the synoptic diagram according to the plasma scope of illustrated embodiments of the invention.
As shown in Figure 1, plasma scope comprises Plasmia indicating panel (PDP) 100, controller 200, addressing electrode driver 300, scan electrode driver 400 and keeps electrode driver 500.
Arc chamber (hereinafter, being called the chamber) is by forming with the discharge space that the place, intersection region that comprises one of scan electrode Y1-Yn and the pair of electrodes of keeping one of electrode X1-Xn forms at one of addressing electrode A1-Am.
Addressing driver 300 slave controllers 200 receive the addressing drive control signal, and are provided for selecting the display data signal of the arc chamber (that is the arc chamber that be switched on) connected to corresponding addressing electrode.
Keep 200 receptions of electrode driver 500 slave controllers and keep the electrode drive control signal, and provide driving voltage to keeping electrode.
Below with reference to Fig. 2 the interim drive waveforms of keeping according to the Plasmia indicating panel of example embodiment of the present invention is described.
Fig. 2 is the view of keeping interim drive waveforms of the plasma scope of foundation example embodiment of the present invention.In Fig. 2, illustrate interim, as to offer X and the Y electrode drive waveforms of keeping a son field.
As shown in Figure 2, offer X and Y electrode keeping the interim pulse of keeping that will alternately have Vs and 0V voltage, and offer the X electrode keep pulse have with offer the Y electrode keep the pulse opposite phases.Therefore, the voltage difference between X and the Y electrode alternately becomes voltage Vs and voltage-Vs.
When in address period, between X and Y electrode, forming predetermined wall voltage, produce discharge with the voltage difference Vs that offers two electrodes by this wall voltage.Wall voltage on two electrodes is converted to opposite polarity by the discharge that is produced, and by the opposite polarity voltage that offers two electrodes poor-Vs produces another discharge.Then, after the aforesaid operations that produces discharge is repeatedly carried out the corresponding number of times of weighted value with corresponding son, display image.
Be used to produce the power restoring circuit of keeping pulse shown in Figure 2 below with reference to Fig. 3 to Fig. 5 description.
Fig. 3 is the synoptic diagram of keeping the discharge driving circuit according to illustrated embodiments of the invention.
Transistor among Fig. 3 is shown as the N slot field-effect transistor (FET) with body diode (not shown).The negative electrode of body diode is connected to transistor drain, and the anode of body diode is connected to transistorized source electrode.Such transistor can be replaced by other switch with identical or similar functions.In addition, each transistor among Fig. 3 can be a plurality of parallel connected transistors.In Fig. 3, the electric capacity that is formed by X and Y electrode is shown as panel capacitor Cp, and describes in order better to understand and to be easy to, show be connected to the X electrode keep the discharge driving circuit.
As shown in Figure 3, the discharge driving circuit of keeping according to illustrated embodiments of the invention comprises power restoring circuit 510 and keeps voltage driver 520.
What first end of inductance L was connected to panel capacitor Cp keeps electrode X, and second end of inductance L is connected to the negative electrode of diode D1.The anode of diode D1 is connected to the source electrode of transistor Xr, and the drain electrode of transistor Xr is connected to power restoring circuit capacitor C1.
Second end of inductance L is also connected to the anode of diode D2.The negative electrode of diode D2 is connected to the drain electrode of transistor Xf, and the source electrode of transistor Xf is connected to power recovery capacitor C1.
Being stored in power corresponding to half voltage Vs/2 of the difference of voltage Vs and 0V recovers among the capacitor C1.
When transistor Xr had body diode, diode D1 disconnected the path of recovering capacitor C1 formation from inductance L by the body diode of transistor Xr to power.In a similar fashion, when transistor Xf had body diode, diode D2 disconnected from power recovery capacitor C1 and passes through the path of the body diode of transistor Xf to inductance L formation.When switch Xr and Xf do not have body diode, can remove diode D1 and D2.
In addition, in power restoring circuit 510, the connection between diode D1 and the transistor Xr can change with the order that is connected between diode D2 and the transistor Xf.
That keeps that voltage driver 520 is connected to panel capacitor Cp keeps electrode X, and comprises two transistor Xs and Xg.Transistor Xs is connected provides the keeping between the electrode X of the power supply of keeping sparking voltage Vs and panel capacitor Cp, and transistor Xg is connected between the power supply and panel capacitor Cp that ground voltage is provided.Transistor Xs and Xg provide voltage Vs and ground voltage to panel capacitor Cp respectively.
As shown in Figure 4, inductance L can be connected between power recovery capacitor C1 and transistor Xr and the Xf.
The operation of the driving circuit among Fig. 3 is described below with reference to Fig. 5.
As shown in Figure 5, in period T 1, transistor Xg turn-offs when the X electrode voltage Vx of panel capacitor Cp is 0V, and when transistor Xr connects, because resonance current flows to capacitor C1, transistor Xr, diode D1, inductance L and panel capacitor Cp, so the X electrode voltage Vx of panel capacitor Cp has increased.That is to say that transistor Xr and diode D1 have formed the voltage rising path of the voltage that is used to increase panel capacitor Cp place.Though X electrode voltage Vx can be increased to the voltage Vs that recovers the voltage twice at capacitor C1 place at power in theory, because the parasitic element in the circuit, this voltage can also be increased to the voltage less than voltage Vs.Subsequently, in period T 2, transistor Xs connects, and voltage Vs is offered the X electrode of panel capacitor.
In period T 3, when transistor Xs turn-offs and transistor Xf when connecting, because resonance current flows to panel capacitor Cp, inductance L, diode D2, transistor Xf and capacitor C1, so the X electrode voltage Vx of panel capacitor Cp has reduced.That is to say that transistor Xf and diode D2 have formed the low path of voltage drop of the voltage that is used to reduce panel capacitor Cp place.Though X electrode voltage Vx can be reduced to 0V in theory, because the parasitic element in this circuit, this electrode voltage can also be reduced to the voltage that is higher than 0V.Subsequently, in period T 4, transistor Xg connects, and 0V is offered the X electrode of panel capacitor Cp.
Repetition period T1 is to T4, so can offer the X electrode to the pulse of keeping among Fig. 3 because transistor Xr, Xs, Xf and Xg turn on and off as mentioned above.In addition, though an inductance L has been shown among Fig. 4, between voltage rising path and the X electrode and be connected between low path of voltage drop and the X electrode and can connect two different inductance respectively.
Be connected to the gate driver circuit 511 of the grid of transistor Xr or Xf below with reference to Fig. 6 description with the mode of operation of definite power restoring circuit 510.
Because it is identical being connected to the respective gates driving circuit of the respective gates of transistor Xr and Xf, so only describe the gate driver circuit that is connected to transistor Xf below.
Fig. 6 is the synoptic diagram according to the gate driver circuit of the present invention's first example embodiment.
In Fig. 6, control signal in swings between 0V and 5V, and amplifier 511a exports the signal of swinging between 0V and 15V in response to control signal in.
As shown in Figure 6, the gate driver circuit 511 according to the present invention's first example embodiment comprises amplifier 511a, capacitor C2, light emitting diode (LED) D3, diode D4 and resistance R 1 and R2.Amplifier 511a is in response to control signal in, and output is used for the high level voltage or the low level voltage of the grid of driving transistors Xf.Usually, 200 outputs of control signal in slave controller are operated with connection/shutoff of oxide-semiconductor control transistors Xf, and have the low voltage level that uses in controller 200.Yet, because the connection of transistor Xf/shutoff operation can not be by the voltage level control of control signal in, so used the amplifier 511a of the voltage level that is used to amplify control signal in.For example, can use push-pull amplifier.
That is to say that the anode of LED D3 is connected to second end of capacitor C2, and its negative electrode is connected to the grid of transistor Xf.In addition, the negative electrode of diode D4 is connected to second end of capacitor C2, and its anode is connected to the grid of transistor Xf.
Resistance R 1 and R2 can be connected between the grid of transistor Xf and the capacitor C2 and between the source electrode and capacitor C2 of transistor Xf, change to avoid unexpected voltage.In addition, resistance R 3 can be connected between first end and ground power supply of capacitor C2, changes so that prevent unexpected voltage.
The operation of the gate driver circuit 511 among Fig. 6 is described below.
In the period T 3 at Fig. 5, control signal in becomes 5V when reducing the X electrode voltage Vx of panel capacitor Cp, and the output voltage out of amplifier 511a becomes 15V.Because capacitor C1 has been charged to voltage Vs/2, so will offer the grid of transistor Xf with voltage Vs/2 and the corresponding voltage of 15V sum (15+Vs/2).Then, because the grid-source voltage of transistor Xf is the 15V greater than threshold voltage, so connect transistor Xf when transistor Xf is in normal condition following time.Therefore, because electric current flows to the grid of transistor Xf from amplifier 511a by LED D3, so LED D3 is luminous.
Yet, in this case, when transistor Xf has damaged, driving transistors Xf not.Therefore, when control signal in is 5V, because between the grid of amplifier 511a and transistor Xf, do not form current path, so LED is not luminous.
In addition, when control signal in was 0V, the output voltage out of amplifier 511a became 0V.In this case, because the grid-source voltage of transistor Xf is 0V, so electric current flows to the ground power supply by diode D4 and resistance R 3.
According to first example embodiment of the present invention, can determine the mode of operation of transistor Xf by the light emission state of LED.Therefore, can provide LED D3 and the diode D4 that is connected in parallel between the output terminal of amplifier 511a and the capacitor C2 or between the grid of transistor Xf and resistance R 1.
In example embodiment of the present invention, amplifier 511a is used to amplify the voltage level of control signal in, and push-pull amplifier can be used as amplifier 511a.
Fig. 7 is the synoptic diagram according to the push-pull amplifier of example embodiment of the present invention, formation amplifier 511a.
As shown in Figure 7, NPN transistor X1 and PNP transistor X2 form push-pull circuit 511a, and push-pull circuit 511a exports the voltage of 15V or 0V in response to the control signal in by base stage B connected to one another and B ' input.
In more detail, the high level power input of push-pull circuit 511a (that is, the collector C of NPN transistor X1) is connected to the power supply of supply 15V, and its low level power input end (that is the collector C ' of PNP transistor X2) is connected to the ground power supply.The emitter E of the emitter E of NPN transistor X1 and PNP transistor X2 ' be connected to the output terminal out of push-pull circuit 511a.
Therefore, when the input end in by push-pull circuit 511a imports the 5V control signal, because produce the voltage that is amplified to 15V, so transistor Xf connects by output terminal out.When by input end input 0V control signal, because produced the 0V signal, so transistor Xf turn-offs by output terminal out.
Except the gate driver circuit of foundation the present invention first example embodiment, when between the grid of amplifier 511a and transistor Xf, connecting LED as shown in Figure 6, can realize dissimilar gate driver circuits.
Fig. 8 is the synoptic diagram according to the gate driver circuit of second example embodiment of the present invention.In Fig. 8, for convenience of description, show the gate driver circuit that is connected to the transistor Xf among two transistor Xr and the Xf.
In addition, control signal in swings between 0V and 5V, and amplifier 512a exports the signal of swinging between 0V and 15V in response to control signal in.For the sake of brevity, omitted here the description of the element of description already.
As shown in Figure 8, the gate driver circuit 512 according to the present invention's second example embodiment comprises amplifier 512a, capacitor C2, LED D5 and resistance R 1, R2, R3 and R4.Capacitor C2 is connected between the grid of the output terminal out of amplifier 512a and transistor Xf.In addition, resistance R 3 is connected between first end and ground power supply of capacitor C2, and resistance R 4 is connected between the source electrode of second end of capacitor C2 and transistor Xf.Therefore, when the output terminal out by gate driver circuit 512 exports 0V, capacitor C2 is charged to the source voltage of transistor Xf by resistance R 4, capacitor C2 and ground power supply.In addition, LED D5 and resistance R 2 are connected between the source electrode of second end of capacitor C2 and transistor Xf.
In addition, resistance R 1 is connected between second end of the grid of transistor Xf and capacitor C2, and resistance R 1, R2 and R3 prevent that the unexpected voltage of capacitor C2 from changing.The operation of the gate driver circuit 512 among Fig. 8 is described below.
In period T 3, when control signal in is 5V, 15V is outputed to output terminal out by amplifier 512a at Fig. 3.Because capacitor C2 has been charged to the source voltage Vs/2 of transistor Xf, so the grid voltage of transistor Xf is increased to the corresponding voltage of source voltage sum (15V+Vs/2) with 15V and transistor Xf.Then, because the grid-source voltage of transistor Xf is the 15V greater than threshold voltage, so be switched on when transistor Xf is in normal condition this transistor of following time Xf.Therefore, because electric current flows to the source electrode of transistor Xf from amplifier 512a, so LED D5 is luminous.When transistor Xf has damaged, driving transistors Xf not.Therefore, do not have to form grid current path, and LED D5 does not have luminous from amplifier 512a to transistor Xf.
Fig. 9 is the synoptic diagram according to the gate driver circuit of the 3rd example embodiment of the present invention.
As shown in Figure 9, the gate driver circuit 513 according to the 3rd example embodiment comprises amplifier 513a, capacitor C2, LED D5 and resistance R 1, R2, R3 and R4.Zener (Zener) the diode D6 between the source electrode that is connected LED D5 and transistor Xf, according to the configuration of the gate driver circuit 513 of the 3rd example embodiment with shown in Figure 8 identical.The operation of gate driver circuit 513 is identical with the present invention's second example embodiment, and has therefore omitted its detailed description.When Zener diode D6 was connected between the source electrode of LED D5 and transistor Xf, the voltage at the terminal two ends of LED D5 had reduced the corresponding voltage with the voltage breakdown Vz of Zener diode D6.Therefore, when not providing resistance R 2, provide voltage (15V-Vz) at the terminal two ends of LED D5.
Therefore, the load when LED D5 is luminous has reduced, and because can use the LED D5 with low-voltage, so can reduce production costs.
Figure 10 is the synoptic diagram according to the gate driver circuit of the present invention's the 4th example embodiment.
As shown in figure 10, the gate driver circuit 514 according to the present invention's the 4th example embodiment comprises amplifier 514a, capacitor C3 and C4, LED D3, diode D4 and D7 and resistance R 1 and R2.To be similar to the mode of first example embodiment of the present invention, LED D3 and diode D4 are connected in parallel with each other between the output terminal out of amplifier 514a and transistor Xf.Diode D4 is connected to LED D3 with reversed polarity.In addition, capacitor C3 is connected between the low level power input end of the grid of transistor Xf and amplifier 514a.
In addition, resistance R 1 and R2 are connected between the grid of transistor Xf and the output terminal and between the source electrode and output terminal out of transistor Xf, change so that prevent unexpected voltage.First end of capacitor C4 is connected to the high level power input of amplifier 514a by diode D7, and second end of capacitor C4 is connected to the low level power input end of amplifier 514a.
Capacitor C4 is charged to 15V, and the low level power input end of second end of capacitor C4 and amplifier 514a is connected to the source electrode of transistor Xf.Therefore, the voltage that offers the high level power input of amplifier 514a becomes and voltage Va and the corresponding voltage of voltage vcc sum (Vcc+Va), and voltage Va is offered the low level power input end.In addition, diode D7 is connected between the high level power input of capacitor C4 and amplifier 514a, so that electric current flows along single direction.In addition, the voltage difference between the source electrode of the output terminal out of capacitor C3 hold amplifier 514a and transistor Xf.The operation of the gate driver circuit 512 among Figure 10 is described below.
In the period T 3 at Fig. 3, control signal in becomes 5V when reducing the X electrode voltage Vx of panel capacitor Cp, and the voltage of the output voltage out of amplifier 514a becomes voltage (15V+Va).Therefore, because the grid-source voltage of transistor Xf is the 15V greater than threshold voltage, so be switched on when transistor Xf is in normal condition this transistor of following time Xf.Therefore, because electric current flows to the grid of transistor Xf from amplifier 514a by LED D3, so LED D3 is luminous.
Yet when transistor Xf had damaged, transistor Xf was not driven.Therefore, when control signal in is 5V, because be not formed on current path between the grid of amplifier 514a and transistor Xf, so LED is not luminous.
In addition, when control signal in was 5V, the output voltage out of amplifier 514a was voltage Va.Because the grid-source voltage of transistor Xf is 0V, so electric current flows to the low level power input end of amplifier 514a by diode D4.
Figure 11 is the synoptic diagram according to the gate driver circuit of the present invention's the 5th example embodiment.
As shown in figure 11, the gate driver circuit 515 according to the present invention's the 5th example embodiment comprises amplifier 515a, capacitor C2, C3 and C4, LED D5, Zener diode D6, diode D7 and resistance R 1, R2 and R4.Operation according to the gate driver circuit of the present invention's the 5th example embodiment is identical with the operation in the present invention's third and fourth example embodiment, has therefore omitted the description to said units.
According to example embodiment of the present invention, can determine the mode of operation of transistor Xf by the light emission state of LED.
Except the gate driver circuit of foundation the present invention first example embodiment, when between the grid of amplifier and transistor Xf or source electrode, having connected LED, can realize dissimilar gate driver circuits.
In addition, though in example embodiment of the present invention as shown in Figure 2, the pulse of keeping described voltage Vs alternately offers X and Y electrode, can will alternately have voltage Vs and voltage-Vs, offer X electrode and/or Y electrode as the pulse of keeping of the voltage difference between X and the Y electrode.
For example, the pulse of keeping that alternately has voltage Vs and voltage-Vs can be offered the X electrode, simultaneously the Y electrode is biased to ground voltage.In this case, must change the power source voltage level that links to each other with Xg with power recovery capacitor C1 and transistor Xs.
In addition, though the power restoring circuit is described as in the interim use of keeping of example embodiment of the present invention, this power restoring circuit can be used for address period.That is to say, can use the power restoring circuit to be created in the addressing pulse that offers the A electrode in the address period.
According to example embodiment of the present invention,, can easily determine the mode of operation of power restoring circuit and do not need expensive power supply by changing the position of transistor and LED.In addition, can determine easily according to example embodiment of the present invention whether transistor has damaged.
Though in conjunction with the current content description of thinking actual example embodiment the present invention, but be appreciated that, the present invention is not limited to the disclosed embodiments, but opposite, and intention contains various modifications and the equivalents in the spirit and scope that are included in claim.
Claims (30)
1, a kind of plasma scope comprises:
A plurality of electrodes extend in one direction;
At least one inductance is connected between described a plurality of electrode and the power recovery power source;
The first transistor is connected between described at least one inductance and the electrode, perhaps is connected between described at least one inductance and the power recovery power source;
Transistor seconds is connected between described at least one inductance and the electrode, perhaps is connected between described at least one inductance and the power recovery power source; And
Gate driver circuit is adapted for the grid that height or low level voltage to the first or transistor seconds are provided, and comprises light emitting diode (LED), is adapted in response to the electric current that flows to described grid luminous; And first diode, be connected with this LED reverse parallel connection.
2, plasma scope as claimed in claim 1, wherein, described gate driver circuit also comprises amplifier, it is adapted in response to control described transistorized signal output high level voltage or low level voltage, and wherein said LED and first diode are connected in parallel between the grid of described amplifier and the first transistor or transistor seconds.
3, plasma scope as claimed in claim 2, wherein, described gate driver circuit also comprises first capacitor, its first end is connected to described amplifier, and second end is connected to first or the grid and the source electrode thereof of transistor seconds; And wherein said LED is connected between described amplifier and the capacitor, perhaps is connected between described amplifier and the grid.
4, plasma scope as claimed in claim 2, wherein, described LED comprises the anode that is connected to amplifier and is connected to first or the grid of transistor seconds and the negative electrode of source electrode thereof; And wherein said first diode comprises the negative electrode that is connected to described amplifier and is connected to first or the grid of transistor seconds and the anode of source electrode thereof.
5, plasma scope as claimed in claim 3, wherein, described amplifier comprises the 3rd transistor and the 4th transistor, they are connected and are adapted for first power supply that first voltage is provided and are adapted between the second source that second voltage is provided, and described third and fourth transistor layout is a push-pull circuit; And wherein said amplifier be adapted for by described push-pull circuit to first or the grid of transistor seconds driving voltage is provided.
6, plasma scope as claimed in claim 5, wherein, one of described third and fourth transistor comprises NPN transistor, and in described third and fourth transistor another comprises the PNP transistor.
7, plasma scope as claimed in claim 5 also comprises:
First resistance, be connected described first capacitor second end and first or the grid of transistor seconds between; And
Second resistance, be connected first capacitor second end and first or the source electrode of transistor seconds between.
8, plasma scope as claimed in claim 7 also comprises: second resistance, be connected described first capacitor second end and first or the source electrode of transistor seconds between.
9, plasma scope as claimed in claim 8 also comprises: the 3rd resistance is connected between first end and described second source of described first capacitor.
10, plasma scope as claimed in claim 8 also comprises: the 3rd capacitor, and its first end is adapted for first voltage that first power supply is provided, and its second end provides second voltage of second source; Described second end is connected to first or the source electrode of transistor seconds, and described the 3rd capacitor is charged into and first voltage and second voltage between the corresponding voltage of difference.
11, plasma scope as claimed in claim 10 also comprises: second diode is connected between first end and described amplifier of described the 3rd capacitor.
12, plasma scope as claimed in claim 1 also comprises:
The 5th transistor is connected described electrode and is adapted between the 3rd power supply that tertiary voltage is provided; And
The 6th transistor is connected described electrode and is adapted between the 4th power supply that the 4th voltage that is lower than described tertiary voltage is provided;
Wherein, described power recovery power source is adapted for the voltage that is provided between described tertiary voltage and described the 4th voltage.
13, plasma scope as claimed in claim 12, wherein, the voltage level of described second voltage is identical with the voltage level of described the 4th voltage.
14, plasma scope as claimed in claim 1, wherein, described first and second transistors comprise body diode respectively, and wherein this plasma display apparatus also comprises:
Second diode is connected in series to described the first transistor with the direction opposite with body diode in the described the first transistor; And
The 3rd diode is connected in series to described transistor seconds with the direction opposite with the body diode of described transistor seconds.
15, a kind of plasma scope comprises:
A plurality of electrodes extend in one direction;
At least one inductance is connected between described a plurality of electrode and the power recovery power source;
The first transistor is connected between described at least one inductance and the electrode, perhaps is connected between described at least one inductance and the power recovery power source;
Transistor seconds is connected between described at least one inductance and the electrode, perhaps is connected between described at least one inductance and the power recovery power source; And
Gate driver circuit, being adapted for provides height or low level voltage to described first or the grid of transistor seconds, and comprise light emitting diode (LED), be connected described first or the grid and source electrode of transistor seconds between, and be adapted in response to the electric current that flows to grid luminous.
16, plasma scope as claimed in claim 15, wherein, described gate driver circuit also comprises amplifier, it is adapted in response to described transistorized signal output high level voltage of control or low level voltage; And wherein said LED is connected between described amplifier and the source electrode.
17, plasma scope as claimed in claim 16, wherein, described gate driver circuit also comprises:
First capacitor, its first end is connected to described amplifier, and second end is connected to described first or the grid and the source electrode of transistor seconds; And
First resistance, it is connected to second end and described first or the source electrode of transistor seconds of described first capacitor.
18, plasma scope as claimed in claim 17, wherein, the negative electrode of described LED is connected to described first or the source electrode of transistor seconds, and the anode of described LED is connected to second end of described first capacitor.
19, plasma scope as claimed in claim 17 also comprises:
Second resistance, be connected described first capacitor second end and described first or the grid of transistor seconds between; And
The 3rd resistance, be connected described first capacitor second end and described first or the source electrode of transistor seconds between.
20, plasma scope equipment as claimed in claim 19 also comprises: second resistance, be connected described first capacitor second end and described first or the source electrode of transistor seconds between.
21, plasma scope as claimed in claim 18 also comprises: Zener diode, be connected described LED and described first or the source electrode of transistor seconds between.
22, plasma scope as claimed in claim 21, wherein, the negative electrode of described Zener diode is connected to the negative electrode of described LED, and anode is connected to described first or the source electrode of transistor seconds.
23, plasma scope as claimed in claim 20 also comprises: the 4th resistance is connected between first end and described ground power supply of described first capacitor.
24, plasma scope as claimed in claim 22, also comprise: the 3rd capacitor, first end is adapted for the high level power input end that first voltage that first power supply is provided arrives described amplifier, and second end provides the low-level of power input end of second voltage of second source to described amplifier; Wherein said capacitor be charged to and described first voltage and second voltage between the corresponding voltage of difference; And second end of wherein said capacitor is connected to described first or the source electrode of transistor seconds.
25, a kind ofly be used to drive the driver with a plurality of plasma scopes at the upwardly extending electrode of single side, this driver comprises:
Gate driver circuit, it comprises:
At least one inductance is connected to described a plurality of electrode;
The first transistor is connected to described at least one inductance, and is adapted for the voltage that increases described electrode place when this first transistor is connected;
Transistor seconds is connected to described at least one inductance, and is adapted for the voltage that reduces described electrode place when this transistor seconds is connected;
Light emitting diode (LED) is connected to described first or the grid of transistor seconds, and is adapted in response to described first or the connection of transistor seconds and luminous; And
Diode is connected to described first or the grid of transistor seconds, and this diode is connected with the LED reverse parallel connection.
26, driver as claimed in claim 25, wherein, described gate driver circuit also comprises amplifier, it is adapted for the signal of the connection that receives control described first or transistor seconds, control output predetermined voltage, and control is luminous from LED.
27, driver as claimed in claim 25 also comprises:
The 3rd transistor, being adapted in response to the voltage at described electrode place increases and connects, and the 3rd transistor provides first voltage to described electrode; And
The 4th transistor, it is adapted for voltage in response to described electrode place and reduces and connect, and the 4th transistor provides second voltage less than first voltage.
28, driver as claimed in claim 26 also comprises:
The 3rd transistor, being adapted in response to the voltage at described electrode place increases and connects, and the 3rd transistor provides first voltage to described electrode; And
The 4th transistor, it is adapted for voltage in response to described electrode place and reduces and connect, and the 4th transistor provides second voltage less than first voltage.
29, driver as claimed in claim 27 also comprises: capacitor, and it is adapted for the voltage that charges between described first voltage and second voltage, and this capacitor is connected between described the first transistor and the transistor seconds.
30, driver as claimed in claim 28 also comprises: capacitor, and it is adapted for the voltage that charges between described first voltage and second voltage, and this capacitor is connected between described the first transistor and the transistor seconds.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR42934/05 | 2005-05-23 | ||
| KR20050042934 | 2005-05-23 | ||
| KR98032/05 | 2005-10-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1870099A true CN1870099A (en) | 2006-11-29 |
| CN100474369C CN100474369C (en) | 2009-04-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100095929A Expired - Fee Related CN100474369C (en) | 2005-05-23 | 2006-02-24 | Plasma display and driver |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100739078B1 (en) |
| CN (1) | CN100474369C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100787462B1 (en) * | 2006-11-21 | 2007-12-26 | 삼성에스디아이 주식회사 | Apparatus for plasma display |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100626075B1 (en) * | 2005-04-19 | 2006-09-20 | 삼성에스디아이 주식회사 | Circuit for detecting operation state and apparatus for driving plasma display panel comprising the same |
-
2005
- 2005-10-18 KR KR1020050098032A patent/KR100739078B1/en not_active IP Right Cessation
-
2006
- 2006-02-24 CN CNB2006100095929A patent/CN100474369C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN100474369C (en) | 2009-04-01 |
| KR100739078B1 (en) | 2007-07-12 |
| KR20060121079A (en) | 2006-11-28 |
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Granted publication date: 20090401 Termination date: 20100224 |