CN1862968A - 电路布置以及设计电路布置的方法 - Google Patents
电路布置以及设计电路布置的方法 Download PDFInfo
- Publication number
- CN1862968A CN1862968A CNA2006100569963A CN200610056996A CN1862968A CN 1862968 A CN1862968 A CN 1862968A CN A2006100569963 A CNA2006100569963 A CN A2006100569963A CN 200610056996 A CN200610056996 A CN 200610056996A CN 1862968 A CN1862968 A CN 1862968A
- Authority
- CN
- China
- Prior art keywords
- circuit
- logic
- dynamic logic
- function
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
- H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
- H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes
Abstract
Description
Claims (30)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/128,069 US7389481B2 (en) | 2005-05-12 | 2005-05-12 | Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells |
US11/128,069 | 2005-05-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1862968A true CN1862968A (zh) | 2006-11-15 |
CN1862968B CN1862968B (zh) | 2010-05-12 |
Family
ID=37390311
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2006100569963A Expired - Fee Related CN1862968B (zh) | 2005-05-12 | 2006-03-07 | 集成电路以及设计集成电路的方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US7389481B2 (zh) |
CN (1) | CN1862968B (zh) |
TW (1) | TW200707908A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113361219A (zh) * | 2020-05-21 | 2021-09-07 | 台湾积体电路制造股份有限公司 | 用于优化集成电路设计的系统和方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7458051B2 (en) * | 2005-11-17 | 2008-11-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | ECO cell for reducing leakage power |
US8839162B2 (en) * | 2010-07-14 | 2014-09-16 | International Business Machines Corporation | Specifying circuit level connectivity during circuit design synthesis |
US10169617B2 (en) | 2014-04-29 | 2019-01-01 | Bar-Ilan University | Multi-topology logic gates |
US9712112B1 (en) * | 2016-10-21 | 2017-07-18 | International Business Machines Corporation | Dynamic noise mitigation in integrated circuit devices using local clock buffers |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6181163B1 (en) * | 1999-01-21 | 2001-01-30 | Vantis Corporation | FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals |
US6285218B1 (en) * | 2000-05-10 | 2001-09-04 | International Business Machines Corporation | Method and apparatus for implementing logic using mask-programmable dynamic logic gates |
TWI234737B (en) * | 2001-05-24 | 2005-06-21 | Ip Flex Inc | Integrated circuit device |
US6765408B2 (en) * | 2002-02-11 | 2004-07-20 | Lattice Semiconductor Corporation | Device and method with generic logic blocks |
US6690204B1 (en) * | 2002-09-12 | 2004-02-10 | International Business Machines Corporation | Limited switch dynamic logic circuit |
-
2005
- 2005-05-12 US US11/128,069 patent/US7389481B2/en active Active
-
2006
- 2006-03-07 CN CN2006100569963A patent/CN1862968B/zh not_active Expired - Fee Related
- 2006-05-08 TW TW095116227A patent/TW200707908A/zh unknown
-
2008
- 2008-04-02 US US12/061,155 patent/US7954077B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113361219A (zh) * | 2020-05-21 | 2021-09-07 | 台湾积体电路制造股份有限公司 | 用于优化集成电路设计的系统和方法 |
CN113361219B (zh) * | 2020-05-21 | 2023-08-08 | 台湾积体电路制造股份有限公司 | 用于优化集成电路设计的系统和方法 |
Also Published As
Publication number | Publication date |
---|---|
US7954077B2 (en) | 2011-05-31 |
CN1862968B (zh) | 2010-05-12 |
US20060259887A1 (en) | 2006-11-16 |
US7389481B2 (en) | 2008-06-17 |
US20080189663A1 (en) | 2008-08-07 |
TW200707908A (en) | 2007-02-16 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20171116 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171116 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20171122 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171122 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
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TR01 | Transfer of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100512 Termination date: 20190307 |
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CF01 | Termination of patent right due to non-payment of annual fee |