CN1862812A - Multi-stage cross cascade circuit and coordination controlling method - Google Patents
Multi-stage cross cascade circuit and coordination controlling method Download PDFInfo
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- CN1862812A CN1862812A CN 200510069216 CN200510069216A CN1862812A CN 1862812 A CN1862812 A CN 1862812A CN 200510069216 CN200510069216 CN 200510069216 CN 200510069216 A CN200510069216 A CN 200510069216A CN 1862812 A CN1862812 A CN 1862812A
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Abstract
This invention relates to multi grades crossing series circuit and its synergetic control method. The circuit includes multi grade crossing units and its corresponding control device. Each grade checker is set on the connecting line between the second and third crossing units, and adjustable time delay control device is set between each grade crossing unit and the corresponding control device. Exchanging connecting of the multiplex transmission signal is realized through each grade crossing unit. Control is done by each control device and the corresponding grades enable and crossing connecting configuration relation signal line that connected to each crossing unit, and the adjustable time delay controller. The time of each adjustable delay controller delay enable signal to the corresponding crossing unit is accurately adjusted by the check result to the crossing configuration switching. The signal integrity before and after the crossing chip action is ensured by using the device and method in this invention, so error code will not occur.
Description
Technical field
The present invention relates to a kind of circuit design of extensive Cross Connect equipment, the improvement of in particular multistage intersection cascade circuit; What the present invention related to simultaneously is that a kind of multistage intersection cascade circuit guarantees intersection instruction and the harmonious control method of input signal.
Background technology
When multistage cross connection device cascade, change the cross-over configuration of cross chips at different levels, the cross reference of whole cascade unit is changed, the intersection instruction and the input signal of skewing mechanisms at different levels must be harmonious, the time of change action is consistent with the time that the transmission signals that needs the change cross reference arrives this cross chips, and output signal gets muddled under skewing mechanism co-operating states at different levels to avoid.
Arrival next stage cross unit has time-delay to a certain degree behind the transmission signals process upper level cross unit, brings certain difficulty therefore for the co-operating of cross units at different levels.Existing common method is to adopt master controller to issue the cross-over configuration enabled instruction to cross unit unifications at different levels, and the action of cross units at different levels is close to consistent in time.But because transmission signals has to a certain degree time-delay through arriving the next stage cross unit behind the upper level cross unit again, if secondary cross unit starts change action with higher level's cross unit in the identical time, then with respect to transmission signals, the first frame transmission signals that the change action of secondary cross unit is finished switching early than higher level's cross unit arrives the time of secondary cross unit.Will cause losing of some frames like this, even because the transmission disorder of signal causes wrong connection, part signal is transferred to wrong place formation and divulges a secret.
Therefore, also there is defective in prior art, and awaits improving and development.
Summary of the invention
The object of the present invention is to provide the method for a kind of multistage intersection cascade circuit and Collaborative Control thereof, the technical problem that solves is the shortcoming of the mistake frame that causes in order to overcome the inconsistency that multistage cross unit in the prior art occurs between the unit starting change actions at different levels when finishing whole cross-over configuration and change, proposed to utilize and to have adjusted the high accuracy delay controller at the second level and later delay cross-over configuration switching command at different levels, make that the cross-over configuration switching command arrives simultaneously with the input signal that needs the handover configurations relation in cross units at different levels, thereby realize the harmonious of multi-level pmultistage circuit action launching, guarantee not lose when whole cross-over configuration changes the apparatus and method of frame; The present invention realizes the harmless switching of multistage transposition circuit for transmission signals by issuing the cross-over configuration relation, sending the mode of switching checking data, adjusting high accuracy delay controller, monitoring verifier, selected optimum time delay.
Technical scheme of the present invention is as follows:
A kind of multistage intersection cascade circuit, wherein, described circuit includes multistage cross unit and corresponding controller thereof, and described controller receives the outside by control line and switches instruction, connects corresponding cross units at different levels, and described cross units at different levels connect in turn;
From the connecting line between the second level and the third level cross unit, also be provided with verifiers at different levels between the described cross unit at different levels, and can adjust delay controller from also being provided with between the cross units at different levels of the second level cross unit controller corresponding with it; Multiway transmission signal realizes that through cross units at different levels exchange connects successively;
Each controller is by with enabling of linking to each other respectively of corresponding cross units at different levels, interconnection configuration relation holding wire with can adjust delay controller and implement control, the described delay controller of adjusting at different levels postpones the time that enable signal arrives corresponding cross unit, and the assay that the corresponding verifier of dependence switches cross-over configuration is accurately adjusted.
A kind of method of Collaborative Control of multistage intersection cascade circuit, it may further comprise the steps:
Adjust the cross-over configuration switching command of cross unit and the consistency of input signal step by step,, and the corresponding levels can be adjusted delay controller be fixed on optimal value up to success.
Described method, wherein, the cross unit set-up procedure of described each grade comprises:
A: the interconnection to the corresponding levels concerns initialization;
B: checking data is switched in input;
C: regulate time delay controller at the corresponding levels;
D: issue and switch instruction;
E: check verifier at the corresponding levels, whether fault is arranged, as do not have then process ends;
F: repeat above-mentioned a～e step, up to verifier fault-free process ends at the corresponding levels.
Described method, wherein, among the described step c, at the circulation time first time, the time delay controller begins to adjust from zero time delay, adjust step-length and be each frame transmission time of transmission signals half or littler.
The method of a kind of multistage intersection cascade circuit provided by the present invention and Collaborative Control thereof, owing to adopt apparatus and method of the present invention to guarantee the signal integrity of cross chips action front and back, can not guarantee losing of frame not taken place because of the existing error code that crosses.
Description of drawings
Fig. 1 is cross-over configuration switching command and three grades of harmonious intersection cascade circuit schematic diagrames of input signal of a preferred embodiment of the present invention;
Fig. 2 is that multistage intersection cascade circuit of the present invention is regulated cross-over configuration switching command and input signal consistency flow chart;
Fig. 3 is that the second level of the present invention cross unit is regulated cross-over configuration switching command and input signal consistency flow chart;
Wherein, the representative meaning of each symbol is as follows:
I: switch instruction
DATA: switch checking data
B: control bus
C1, C2, C3 ...: the 1st grade of controller, the 2nd grade of controller, the 3rd level controller ...
X1, X2, X2 ...: the 1st grade of cross unit, the 2nd grade of cross unit, the 3rd level cross unit ...
D2, D3 ...: can adjust delay controller for the 2nd grade, 3rd level can be adjusted time-delay trigger ...
CH2, CH3 ...: the 2nd grade of checker, the 3rd level checker ...
EN: intersect and switch enable signal
S1:X1 interconnection configuration relation signal
S2:X2 interconnection configuration relation signal
S3:X3 interconnection configuration relation signal
1-i: enter cross unit 1 i road transmission signals (i=1,2 ..., n)
2-i: enter cross unit 2 i road transmission signals (i=1,2 ..., n)
3-i: enter cross unit 3 i road transmission signals (i=1,2 ..., n)
Out-i: i pipeline equipment output signal (i=1,2 ..., n)
Embodiment
Below, will describe each preferred embodiment of the present invention in detail.
Described multistage intersection cascade circuit device of the present invention by first order cross unit X1 and controller C1, second level cross unit X2 and controller C2, third level cross unit X3 and controller C3 thereof ... n level cross unit Xn and controller Cn thereof, can adjust delay controller D2, D3, ..., Dn, verifier CH2, CH3, ..., formations such as CHn, control bus B; Multiway transmission signal 1,2 ..., n pass through successively first order cross unit X1, second level cross unit X2, third level cross unit X3 ... n level cross unit Xn realizes that exchange connects.Each controller C1, C2, C3 ..., Cn can by with first order cross unit X1 at different levels, X2, X3 ..., Xn links to each other respectively enables EN, interconnection configuration relation S1, S2, S3, ..., Sn equisignal line and can adjust delay controller D2, D3 ..., Dn implements to control.The delay controller D2 that adjust at different levels, D3 ..., Dn can postpone enable signal EN and arrive second level cross unit X2, X3 ..., the time of Xn.The delay controller D2 that adjust at different levels, D3 ..., Dn relies on verifiers at different levels the assay of cross-over configuration switching is accurately adjusted.
The design of technical solution of the present invention is applicable to the multistage i.e. control of the intersection cascade circuit more than 3 grades or 3 grades.
The method of the multistage intersection cascade circuit of realization of the present invention Collaborative Control, its core thinking be utilize issue the cross-over configuration relation, send switch checking data, regulate the high accuracy delay controller, monitoring verifier, selected optimum time delay implement action.Following rule is followed in the design of two groups of cross-over configuration relations before and after switching checking data and switching: cross-over configuration is switched preceding in the test side, be second level cross unit output signal, third level cross unit output signal ... n level cross unit output signal, can receive signal specific from one or more, cross-over configuration is switched the back also can receive signal specific from one or more in the test side, if the cross-over configuration switching is inconsistent between multistage, then can not receive signal specific for some time in the test side.Verifier can have been discerned the disorderly appearance of no signal, as the criterion of regulating the time delay controller.
The collaborative adjustment process of multistage intersection cascade circuit is as follows:
From integral body intersection cascade circuit, its step is to adjust step by step:
The first step: regulate second level cross unit cross-over configuration switching command and input signal consistency, up to success;
Second step: regulate third level cross unit cross-over configuration switching command and input signal consistency, up to success;
The 3rd step:, handle successively if transposition circuit is more than 3 grades.
From each grade cross unit, its adjustment process is as follows:
The first step: interconnection concerns initialization;
Second step: checking data is switched in input;
The 3rd step: regulate the time delay controller;
The 4th step: issue and switch instruction;
The 5th step: check verifier;
The 6th step: repeat five step of the first step to the content, up to success.
Be example with three grades of intersection cascade circuits as shown in Figure 1, the structure of the multistage intersection cascade circuit that cross-over configuration switching command and input signal are harmonious is described, device by first order cross unit X1 and controller C1, second level cross unit X2 and controller C2, third level cross unit X3 and controller C3 thereof, can adjust delay controller D2, D3, verifier CH2, formations such as CH3, control bus B. Multiway transmission signal 1,2 ..., n realizes that through first order cross unit X1, second level cross unit X2 and the third level cross unit X3 exchange is connected successively.Each controller can enable EN, interconnection configuration relation S1 by what link to each other respectively with cross units at different levels, S2, and S3 equisignal line and can adjust delay controller D2, D3 implements control to cross unit.
Annexation between above-mentioned each part is: the 1st to n road transmission signals 1-i enters first order cross unit X1.In first order cross unit X1, transmission signals is finished the first order and is intersected, and forms the 1st to n road transmission signals 2-i.Transmission signals 2-i enters second level cross unit X2.In the cross unit X2 of the second level, transmission signals is finished the second level and is intersected, and forms transmission signals 3-i.Transmission signals 3-i enters third level cross unit X3.In third level cross unit X3, transmission signals is finished the third level and is intersected apparatus output signal out-i.First order cross unit X1, second level cross unit X2 are connected by transmission signals with third level cross unit X3.
Between the corresponding controller C1 of first order cross unit X1 with it by enable EN, interconnection configuration relation S1 equisignal line is connected.When first order cross unit X1 receives enable signal EN, cross-over configuration takes place switch.Controller C1 controls first order cross unit X1 by these holding wires.
Be connected by enabling EN, interconnection configuration relation S2 equisignal line and can adjust delay controller D2 between the corresponding controller C2 of second level cross unit X2 with it.Delay controller D2 can be adjusted and the time that enable signal EN arrives second level cross unit X2 can be postponed.When second level cross unit X2 receives enable signal EN, cross-over configuration takes place switch.Second level controller C2 controls second level cross unit X2 by these holding wires.
Be connected by enabling EN, interconnection configuration relation S3 equisignal line and can adjust delay controller D3 between the corresponding controller C3 of third level cross unit X3 with it.Delay controller D3 can be adjusted and the time that enable signal EN arrives third level cross unit X3 can be postponed.When third level cross unit X3 receives enable signal EN, cross-over configuration takes place switch.Third level controller C3 controls third level cross unit X3 by these holding wires.
Total instruction I that switches of multistage intersection cascade circuit enters first order controller C1, second level controller C2 and third level controller C3 by control bus B.
Be that multistage intersection cascade circuit is regulated cross-over configuration switching command and input signal consistency flow chart as shown in Figure 2.This flow chart is that example illustrates with three grades of transposition circuits, but its principle also is applicable to more multistage transposition circuit.
The first step: at first regulate second level cross unit cross-over configuration switching command and input signal consistency, up to success; Can adjust delay controller D2 and be fixed on optimal value.
Second step: regulate third level cross unit cross-over configuration switching command and input signal consistency, up to success; Can adjust delay controller D3 and be fixed on optimal value.
The 3rd step:, handle successively if transposition circuit is more than 3 grades.
Be illustrated in figure 3 as second level cross unit and regulate cross-over configuration switching command and input signal consistency flow chart, in this embodiment, two groups of cross-over configuration relations before and after two-stage cross unit X1, X2 switch with the design principle of switching checking data are: have at least one the tunnel can supply signal identical signal specific of output before and after switching of check among the signal 3-i; If cross-over configuration is switched when inconsistent between multistage, be the first frame transmission signals that the enable signal EN during secondary intersects finishes switching prior to first order cross unit X1 when arriving second level cross unit X2 or the secondary enable signal EN in intersecting and being later than the first frame transmission signals that first order cross unit X1 finishes switching and arriving second level cross unit X2, this road signal is not exported signal specific.
Introduce adjustment control method of the present invention in detail below in conjunction with Fig. 3.
The first step: interconnection concerns initialization.Controller C1 at different levels, C2 issue first group of interconnection configuration relation by interconnection configuration signal line S1, S2, and move first group of interconnection configuration relation by enable signal EN.Controller C1 at different levels, C2 issue second group of interconnection configuration relation by interconnection configuration signal line S1, S2, cross unit X1 at different levels, X2 store second group of cross-over configuration relation, wait for that enable signal EN carries out old cross-over configuration and concerns the switching that concerns with new cross-over configuration.
Second step: checking data is switched in input.
The 3rd step: regulate time delay controller D2.In circulation for the first time, the time delay controller can begin to adjust from zero time delay, adjust step-length can select each frame transmission time of transmission signals half or littler.
The 4th step: issue and switch instruction.Issue to the first order and second level controller C1, C2 from control bus B and to switch instruction I.Enable signal EN during the first order is intersected does not have time-delay and arrives first order cross unit X1, and first order cross unit X1 finishes the cross-over configuration relation and switches; Enable signal EN during the second level intersects arrives second level cross unit X2 through time-delay, and second level cross unit X2 finishes the cross-over configuration relation and switches.
The 5th step: check that verifier has fault-free.Occur if verifier CH2 shows signal is disorderly, then repeat the first step to the work in five steps; If verifier CH2 shows the disorderly appearance of no signal, then fix the delay value of current time delay controller D2.
Third level cross unit cross-over configuration switching command of the present invention and the conforming adjustment of input signal are to carry out after the optimum delay value of finishing third level cross unit cross-over configuration switching command and the conforming adjustment of input signal and fixed delay controller D2.Two groups of cross-over configuration relations before and after three grades of cross unit X1, X2, X3 switch with the design principle of switching checking data are: have at least one the tunnel can supply signal identical signal specific of output before and after switching of check among the signal out-i; If cross-over configuration is switched when inconsistent between multistage, be the first frame transmission signals that the enable signal EN during the third level is intersected finishes switching prior to second level cross unit X2 when arriving third level cross unit X3 or the third level enable signal EN in intersecting and being later than the first frame transmission signals that second level cross unit X2 finishes switching and arriving third level cross unit X3, this road signal is not exported signal specific.Remaining method of adjustment is identical with the conforming method of adjustment of input signal with second level cross unit cross-over configuration switching command.
Cross unit cross-over configuration switching commands at different levels and the conforming adjustment of input signal are to carry out after the optimum delay value of finishing prime cross unit cross-over configuration switching command and the conforming adjustment of input signal and fixed delay controller D2.Method of adjustment is carried out successively, and is ditto described.
Should be understood that above-mentioned description at preferred embodiment is comparatively concrete, can not therefore be interpreted as the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (4)
1, a kind of multistage intersection cascade circuit, it is characterized in that described circuit includes multistage cross unit and corresponding controller thereof, described controller receives the outside by control line and switches instruction, connect corresponding cross units at different levels, described cross units at different levels connect in turn;
From the connecting line between the second level and the third level cross unit, also be provided with verifiers at different levels between the described cross unit at different levels, and can adjust delay controller from also being provided with between the cross units at different levels of the second level cross unit controller corresponding with it; Multiway transmission signal realizes that through cross units at different levels exchange connects successively;
Each controller is by with enabling of linking to each other respectively of corresponding cross units at different levels, interconnection configuration relation holding wire with can adjust delay controller and implement control, the described delay controller of adjusting at different levels postpones the time that enable signal arrives corresponding cross unit, and the assay that the corresponding verifier of dependence switches cross-over configuration is accurately adjusted.
2, a kind of method of Collaborative Control of multistage intersection cascade circuit, it may further comprise the steps:
Adjust the cross-over configuration switching command of cross unit and the consistency of input signal step by step,, and the corresponding levels can be adjusted delay controller be fixed on optimal value up to success.
3, method according to claim 2 is characterized in that, the cross unit set-up procedure of described each grade comprises:
A: the interconnection to the corresponding levels concerns initialization;
B: checking data is switched in input;
C: regulate time delay controller at the corresponding levels;
D: issue and switch instruction;
E: check verifier at the corresponding levels, whether fault is arranged, as do not have then process ends;
F: repeat above-mentioned a～e step, up to verifier fault-free process ends at the corresponding levels.
4, method according to claim 3 is characterized in that, among the described step c, at the circulation time first time, the time delay controller begins to adjust from zero time delay, adjust step-length and be each frame transmission time of transmission signals half or littler.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100692164A CN100530641C (en) | 2005-05-12 | 2005-05-12 | Multi-stage cross cascade circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100692164A CN100530641C (en) | 2005-05-12 | 2005-05-12 | Multi-stage cross cascade circuit |
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| CN1862812A true CN1862812A (en) | 2006-11-15 |
| CN100530641C CN100530641C (en) | 2009-08-19 |
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| CNB2005100692164A Expired - Fee Related CN100530641C (en) | 2005-05-12 | 2005-05-12 | Multi-stage cross cascade circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112507641A (en) * | 2020-12-17 | 2021-03-16 | 中科芯云微电子科技有限公司 | Alternating verification method and system for integrated circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112507641A (en) * | 2020-12-17 | 2021-03-16 | 中科芯云微电子科技有限公司 | Alternating verification method and system for integrated circuit |
| CN112507641B (en) * | 2020-12-17 | 2022-07-05 | 中科芯云微电子科技有限公司 | Alternating verification method and system for integrated circuit |
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| CN100530641C (en) | 2009-08-19 |
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Effective date of registration: 20180703 Address after: California, USA Patentee after: Global innovation polymerization LLC Address before: 518057 Department of law, Zhongxing building, South hi tech Industrial Park, Nanshan District hi tech Industrial Park, Guangdong, Shenzhen Patentee before: ZTE Corp. |
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Granted publication date: 20090819 |