CN1859829A - Method for producing circuit board - Google Patents
Method for producing circuit board Download PDFInfo
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- CN1859829A CN1859829A CN 200610087670 CN200610087670A CN1859829A CN 1859829 A CN1859829 A CN 1859829A CN 200610087670 CN200610087670 CN 200610087670 CN 200610087670 A CN200610087670 A CN 200610087670A CN 1859829 A CN1859829 A CN 1859829A
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- dielectric layer
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- path
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Abstract
The present invention provides circuit board making method. It includes providing substrate having at least first dielectric layer; moulding first dielectric layer to form cave pattern which does not penetrate first dielectric layer; solidifying first dielectric layer; filling-in conductor material to cave pattern to form first circuit pattern; then to form conducting layer on first dielectric layer and first circuit pattern.
Description
Technical field
The invention relates to a kind of manufacture method of wiring board, and particularly relevant for a kind of manufacture method with wiring board of flush type line pattern (embedded wiring pattern or embedded circuits pattern).
Background technology
On large-sized print circuit board and base plate for packaging, in order to electrically connect the signal conductor between two elements or two end points, its live width all need be consistent, so that electronic signal is when transmitting between signal conductor, the characteristic impedance of signal conductor (characteristic impedance) can remain unchanged.In addition, use and design general, between two signal conductor also because of the shortening of distance, and make capacitive couplings and inductive couplings between the signal will become big thereupon, and make the phenomenon of near-end crosstalk (near-end crosstalk) and far-end crosstalk (far-end crosstalk) become more serious, thereby cause signal can't be correctly and intactly by an endpoint transfers of signal conductor to another end points.Especially transmitting with the signal of high frequency at a high speed, signal because the interactive interference between the electromagnetic field, thereby can be observed unnecessary interference signal cross-talk on another signal conductor when switching.
Please refer to Figure 1A and Figure 1B, its schematic top plan view that illustrates known a kind of line construction respectively and generalized section along the I-I line.With general circuit base plate 100 is example, the circuit 110,112,114,116 of many live width unanimities is disposed on the upper surface 122 of dielectric layer 120, and dielectric layer 120 coincides on reference planes 130 with its lower surface 124, and make reference planes 130 and these circuits 110,112,114,116 keep equidistant, wherein reference planes 130 for example are power plane or ground plane.
The manufacture method of circuit base plate 100 is that the upper surface 122 at dielectric layer 120 forms a copper foil layer (not illustrating) respectively with lower surface 124, then carries out little shadow and etch process respectively to form these circuit 110,112,114,116 and reference planes 130 for these copper foil layers.
When it should be noted that,, and on another signal, form cross-talk, influence signal transmitting quality owing to the electromagnetic field couples of 112 of adjacent lines for fear of signal flow via line 110.So in the known techniques, often by the circuit 112,114 of widening the transmission signal of interest and another circuit 110,116 distance D 1, the D2 to each other that transmits adjacent signals, to reduce cross-talk.Yet this practice reduces the wiring space of substrate 100 relatively.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of wiring board makes that the technology yield and the wiring density of the flush type line pattern that width is thinner are promoted.
For reaching above-mentioned or other purposes, the present invention proposes a kind of manufacture method of wiring board, and it comprises the following steps.At first, provide substrate (base), substrate has at least one first dielectric layer.Then, to form recess patterns (sunken pattern), recess patterns does not run through first dielectric layer with die marks (press) first dielectric layer.Then, solidify (cure) first dielectric layer.Afterwards, electric conducting material is filled up recess patterns to form first line pattern (wiring pattern).Then, form conductive layer on first dielectric layer and first line pattern.
For reaching above-mentioned or other purposes, the present invention proposes the manufacture method of another kind of wiring board, and it comprises the following steps.At first, provide substrate, substrate has at least the first dielectric layer.Then, having the mould of first pattern, first pattern of mould is pressed in first dielectric layer, forms second pattern, wherein, second pattern does not run through first dielectric layer.Then, solidify first dielectric layer.Afterwards, form at least one path, this path runs through first dielectric layer.Afterwards, electric conducting material is filled up the sunk part and the path of first dielectric layer, to form first line pattern and first conductive path.Then, form conductive layer on first dielectric layer, first conductive path and first line pattern.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A illustrates the schematic top plan view of known a kind of line construction.
Figure 1B illustrates the generalized section of the line construction of Figure 1A along the I-I line.
Fig. 2 A to Fig. 2 G illustrates the schematic flow sheet of manufacture method of the wiring board of first embodiment of the invention.
Fig. 3 illustrates the schematic diagram of the processing step that carries out patterned conductive layer of second embodiment of the invention.
Fig. 4 illustrates the schematic diagram of the processing step that carries out patterned conductive layer of third embodiment of the invention.
Fig. 5 illustrates the schematic diagram of the wiring board of fourth embodiment of the invention.
[main element symbol description]
100: circuit base plate 110,112,114,116: circuit
120: dielectric layer 122: upper surface
124: lower surface 130: reference planes
200,300,400,500: substrate
210,410,510: the first dielectric layers
220,350,460,520: line layer
230,330,430,530: the first line patterns
340,440,540: the second line patterns
450,550: the tertiary circuit pattern
510 ': the second dielectric layer 2006: mould
2007,2008 ': recess patterns
2008: protrude pattern 2009: path
2012,2014: 2013: the second conductive paths of wiring board
D1, D2: distance D 3, D4, D5, D6: thickness
W1, W2, W3, W4: width
Embodiment
First kind embodiment
Fig. 2 A to Fig. 2 G illustrates the schematic flow sheet of manufacture method of the wiring board of first kind embodiment of the present invention.
In the present invention, wiring board can be printed circuit board (PCB) (rigid or soft), and carrier (carrier) or substrate that wiring board can also be a wafer package to be used.
The manufacture method of the wiring board of first kind embodiment comprises the following steps.At first, please refer to Fig. 2 A, substrate 200 is provided, it has at least one first dielectric layer 210.
In the present invention, substrate 200 comprises line layer 220, and it is disposed on the surface of first dielectric layer 210.And line layer 220 also can comprise power line, earth connection or any wiring pattern.In addition, the material of first dielectric layer 210 can be epoxy resin, for example: contain the epoxy resin (epoxy resin without glassfiber) of the epoxy resin (epoxyresin with glass fiber) of glass fibre, no glass fibre or the epoxy resin of other kinds.
Then, please refer to Fig. 2 B and Fig. 2 C, mould 2006 is impressed first dielectric layer 210 with formation recess patterns 2007, and recess patterns 2007 does not run through first dielectric layer 210.
Among the present invention, mould 2006 can have and protrudes pattern 2008, therefore the time with mould 2006 impressions first dielectric layer 210, the protrusion pattern 2008 of mould 2006 can be pressed in first dielectric layer 210 and first dielectric layer 210 in formation recess patterns 2007.
Mandatory declaration be, mould 2006 can have the protrusion pattern of the different external forms or the different depths according to design requirement, the recess patterns that perhaps has the different external forms or the different depths, forming the sunk part (in the present embodiment, this sunk part is recess patterns 2007) that can not run through first dielectric layer 210 as long as mould 2006 can impress first dielectric layer 210 gets final product.
For example, mould 2006 of the present invention also can have recess patterns 2008 ', and this recess patterns 2008 ' and 2008 complementations of protrusion pattern, in other words, the purpose of using mould is for formation recess patterns 2007 in first dielectric layer 210, and the selection of mould can be to have mould that protrudes pattern or the mould with recess patterns.
In view of the above, mould 2006 is non-limiting the present invention in order to give an example.
Then, please refer to Fig. 2 C, solidify first dielectric layer 210, and the mode of solidifying can adopt and is heating and curing (heat-curing) or mode that UV-irradiation is solidified (ultraviolet-curing) is carried out.
In the present invention, can in mould 2006 impressions first dielectric layer 210, solidify first dielectric layer 210, when solidifying, can not produce distortion to keep recess patterns 2007.Yet, after also can mould 2006 being removed, be cured technology at first dielectric layer 210 again, but do not illustrate with drawing according to design requirement.
Then, after removing mould 2006, please refer to Fig. 2 D, form at least one path (via) 2009, it runs through first dielectric layer 210.
In the present invention, the mode moulding that path 2009 can laser processing.And path 2009 also can be in the zone outside the recess patterns 2007, the moulding in the mode that runs through first dielectric layer 210, and path 2009 connects recess patterns 2007.In addition, path 2009 also can directly be run through first dielectric layer 210 and moulding in certain some of recess patterns 2007, but does not illustrate with drawing.It should be noted that the step that forms at least one path 2009 is optionally, the designer can omit the processing step that Fig. 2 D is illustrated according to design requirement.
Afterwards, please refer to Fig. 2 D and 2E, electric conducting material is filled up recess patterns 2007 to form first line pattern 230.In the present invention, can simultaneously electric conducting material be filled up path 2009 to form first conductive path (conducive via) 2010.In addition, the used electric conducting material of the present invention can be copper, aluminium, gold or nickel or the like, or the alloy of conducting metal, or the material of other conductions or compound.
Then, please refer to Fig. 2 F, form conductive layer 2011 on first dielectric layer 210, first line pattern 230 and first conductive path 2010.Mandatory declaration be that the step of filling up recess patterns 2007 and path 2009 and forming conductive layer 2011 can adopt plating, evaporation or sputter to form in regular turn usually.
For example, can be with the target of metal (for example: copper, aluminium, gold, nickel or alloy) as ion bombardment, fill up recess patterns 2007 and conductive path 2009 simultaneously forming first line pattern 230 and first conductive path 2010 respectively in the mode of sputter, and on first dielectric layer 210, first line pattern 230 and first conductive path 2010 formation conductive layer 2011.Therefore, first line pattern 230, first conductive path 2010 are generally identical with the conductive material of conductive layer 2011.
It should be noted,, can once finish, or can finish stage by stage by the step of Fig. 2 E step to Fig. 2 F; In other words, can be in the same stage, electric conducting material is filled up recess patterns 2007 (or simultaneously electric conducting material being filled up path 2009) and forms conductive layer 2011 on first dielectric layer 210, first line pattern 230 and first conductive path 2010, and also can in different phase, electric conducting material be filled up sunk area 2007,2009 and form conductive layer 2011.In addition, when filling up recess patterns 2007 with path 2009, outside the zone of desiring to fill up, have conductive layer and form.And this conductor layer can be considered conductive layer 2011, in other words, when electric conducting material fills up recess patterns 2007 or will fill up path 2009 simultaneously, also take place simultaneously to form conductive layer 2011 on first dielectric layer 210, first line pattern 230 and first conductive path 2010.
At last, please refer to Fig. 2 F and Fig. 2 G, in the present invention, the mode that can grind (grinding) or etching (etching) removes conductive layer 2011.So, the wiring board 2012 of first embodiment can be finished.By Fig. 2 G as can be known, first dielectric layer 210 is between first line pattern 230 and line layer 220, and first line pattern 230 and first conductive path 2010 are embedded in first dielectric layer 210.
After finishing wiring board 2012, can continue on wiring board 2012, to form conductive layer (not shown), and with this conductive layer patternization forming line pattern, to reach the line pattern kenel of Fig. 3 and Fig. 4 as described below.Yet, also can behind the intermediate of finishing Fig. 2 F, form line pattern.This moment, the thickness factor of conductive layer 2011 should be included in to consider and be beneficial to form line pattern.(see second embodiment and the 3rd embodiment.)
It should be noted, the present invention embodiment in, the step of patterned conductive layer can be to carry out patterning step finishing line pattern, or carries out once above patterning step finishing line pattern, to reach the line pattern kenel of Fig. 3 and Fig. 4 as described below.And patterning method can comprise little shadow and etch process, or other patterning methods that will be invented.
Second embodiment
Fig. 3 illustrates the schematic diagram of the processing step that carries out patterned conductive layer of second embodiment of the invention.
Please refer to Fig. 3 and Fig. 2 F, after the step of the formation conductive layer 2011 that Fig. 2 F that is equivalent to first embodiment is illustrated, the manufacture method of the wiring board of second embodiment comprises that also patterned conductive layer 2011 is to form second line pattern 340.
In the present invention, the mode of patterned conductive layer 2011 can be finished by little shadow and etch process, second line pattern 340 is disposed on first line pattern 330, and the thickness D3 of second line pattern 340 can be less than the thickness D4 of first line pattern 330, and first line pattern 330 and second line pattern 340 constitute (compose) another line layers 350.
In addition, the width W 1 of second line pattern 340 can be less than or equal to the width W 2 of first line pattern 330 according to design requirement.
The 3rd embodiment
Fig. 4 illustrates the schematic diagram of the processing step that carries out patterned conductive layer of third embodiment of the invention.
Please refer to Fig. 4 and Fig. 2 F, after the step of the formation conductive layer 2011 that Fig. 2 F that is equivalent to first embodiment is illustrated, the manufacture method of the wiring board of the 3rd embodiment comprises that also patterned conductive layer 2011 is to form second line pattern 440 and tertiary circuit pattern 450.
In the present invention, the mode of patterned conductive layer 2011 can be finished by little shadow and etch process, wherein the thickness of second line pattern 440, width and relative position are same as thickness, width and the relative position of above-mentioned second line pattern 340, so repeat no more in this.
In addition, tertiary circuit pattern 450 is disposed on first dielectric layer 410, the width W 3 of tertiary circuit pattern 450 can be greater than the width W 4 of first line pattern 430, and the thickness D5 of tertiary circuit pattern 450 can be less than the thickness D6 of first line pattern 430, and first line pattern 430, second line pattern 440 constitute another line layers 460 with tertiary circuit pattern 450.
The 4th embodiment
In first embodiment, second embodiment and the 3rd embodiment, substrate 200,300 and 400 (seeing Fig. 2 G, Fig. 3 and Fig. 4) is the example explanation with single dielectric layer and uniline layer all, but substrate also can have a plurality of dielectric layers and a plurality of line layer.
Please refer to Fig. 5, it illustrates the schematic diagram of the wiring board of fourth embodiment of the invention.In the 4th embodiment, substrate 500 comprises at least the first dielectric layer 510 (illustrating two among Fig. 5), at least one second dielectric layer 510 ' (illustrating three among Fig. 5) and at least one line layer 520 (illustrating four among Fig. 5).Substrate 500 also comprises a plurality of second conductive paths 2013, and wherein each second conductive path 2013 runs through one of them of these second dielectric layers 510 '.These line layers 520 and these second dielectric layer, 510 ' alternate configurations, these line layers 520 at least wherein two be by these second conductive paths 2013 one of them electrically connects at least, and these line layers 520 wherein two embed respectively in these first dielectric layers 510.
As shown in Figure 5, these first line patterns 530 of wiring board 2014 are disposed at respectively in these first dielectric layers 510, these second line patterns 540 are disposed at respectively on these first line patterns 530, and these tertiary circuit patterns 550 are disposed at respectively on these first dielectric layers 510.These first line patterns 530, these second line patterns 540 and the then corresponding relevant narration that is same as first line pattern 430, second line pattern 440 and the tertiary circuit pattern 450 of the 4th embodiment of the relevant narration of these tertiary circuit patterns 550 are so repeat no more in this.
In sum, the manufacture method of wiring board of the present invention has following advantage at least:
One,, therefore can promote the technology yield and the wiring density of the thinner line pattern of live width because the present invention can make the thinner line pattern of live width be embedded in the dielectric layer.
Two, because the present invention can make the thinner line pattern of live width be embedded in the dielectric layer, therefore, high-frequency signal or other signal of interests can intactly transmit through line pattern thus, and then reduce the energy loss and the quality that improves the signal transmission of signal.
Three, the manufacture method of wiring board of the present invention can be widely used in the manufacturing of large-sized print circuit board and compact package substrate.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those of ordinary skill in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (10)
1. the manufacture method of a wiring board comprises:
Substrate is provided, and this substrate has at least one first dielectric layer;
Having the mould of first pattern, this first pattern of this mould is pressed in this first dielectric layer, form second pattern, wherein, this second pattern does not run through this first dielectric layer;
Solidify this first dielectric layer;
Form at least one path, this path runs through this first dielectric layer;
Electric conducting material is filled up sunk part and this path of this first dielectric layer, to form first line pattern and first conductive path; And
Form conductive layer on this first dielectric layer, this first conductive path and this first line pattern.
2. the manufacture method of wiring board as claimed in claim 1, wherein this path is the mode moulding with laser processing.
3. the manufacture method of wiring board as claimed in claim 1, the mode that wherein forms this path are in this depressed part office of part, and this first dielectric layer is run through and moulding.
4. the manufacture method of wiring board as claimed in claim 1, the mode that wherein forms this path is the zone outside this sunk part, run through this first dielectric layer and moulding, and this path is connected with this sunk part.
5. the manufacture method of wiring board as claimed in claim 1, it also comprises and removes this conductive layer.
6. the manufacture method of wiring board as claimed in claim 5, the mode that wherein removes this conductive layer is for grinding.
7. the manufacture method of wiring board as claimed in claim 5, the mode that wherein removes this conductive layer is etching.
8. the manufacture method of wiring board as claimed in claim 1, it also comprises and forms second line pattern in this conductive layer.
9. the manufacture method of wiring board as claimed in claim 1, it also comprises and forms second line pattern and tertiary circuit pattern in this conductive layer.
10. the manufacture method of wiring board as claimed in claim 1, when wherein solidifying this first dielectric layer, this mould still is pressed into this first dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100876707A CN100490613C (en) | 2006-05-31 | 2006-05-31 | Method for producing circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100876707A CN100490613C (en) | 2006-05-31 | 2006-05-31 | Method for producing circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1859829A true CN1859829A (en) | 2006-11-08 |
| CN100490613C CN100490613C (en) | 2009-05-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100876707A Active CN100490613C (en) | 2006-05-31 | 2006-05-31 | Method for producing circuit board |
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| Country | Link |
|---|---|
| CN (1) | CN100490613C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102045941B (en) * | 2009-10-14 | 2013-01-16 | 欣兴电子股份有限公司 | Embedded type circuit board structure and manufacturing method thereof |
| CN104519666A (en) * | 2014-12-17 | 2015-04-15 | 上海蓝沛新材料科技股份有限公司 | Flexible die and production method for manufacturing flexible printed circuit boards |
| CN106034373A (en) * | 2015-03-10 | 2016-10-19 | 上海量子绘景电子股份有限公司 | High-density multilayer copper circuit board and preparation method thereof |
| WO2023241123A1 (en) * | 2022-06-16 | 2023-12-21 | 深圳Tcl新技术有限公司 | Flexible circuit board and manufacturing method therefor |
-
2006
- 2006-05-31 CN CNB2006100876707A patent/CN100490613C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102045941B (en) * | 2009-10-14 | 2013-01-16 | 欣兴电子股份有限公司 | Embedded type circuit board structure and manufacturing method thereof |
| CN104519666A (en) * | 2014-12-17 | 2015-04-15 | 上海蓝沛新材料科技股份有限公司 | Flexible die and production method for manufacturing flexible printed circuit boards |
| CN106034373A (en) * | 2015-03-10 | 2016-10-19 | 上海量子绘景电子股份有限公司 | High-density multilayer copper circuit board and preparation method thereof |
| CN106034373B (en) * | 2015-03-10 | 2018-09-25 | 上海量子绘景电子股份有限公司 | High-density multi-layered copper circuit board and preparation method thereof |
| WO2023241123A1 (en) * | 2022-06-16 | 2023-12-21 | 深圳Tcl新技术有限公司 | Flexible circuit board and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100490613C (en) | 2009-05-20 |
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