CN1858752A - Radio communication simulation device based on FPGA and USB storage device - Google Patents
Radio communication simulation device based on FPGA and USB storage device Download PDFInfo
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Abstract
This invention discloses a radio communication emulation device based on the FPGA and USB storage device, in which, the signal generation device of said device includes a USB storage device, a USB read-write device, a level conversion circuit, a SDRAM storage circuit and a function module with the FPGA chip as the main body, which realizes complicated emulation research with simple devices to speed up the scientific research.
Description
Technical field
The invention belongs to wireless communication technology field, relate to the simulator that the implementation and the algorithm thereof of radio communication are verified, particularly relate to a kind of wireless communication simulating apparatus based on FPGA and USB storage device.
Background technology
Wireless mobile telecommunication technology is the hot technology that human lives and social development is had significant impact, be the most active and development one of research topic the most rapidly in the current communications field, increasing research institution and scientific research resource are put into the technical research in this field.New communication technology from research and development, be sophisticated to practical application, need repeatedly in simulated environment, verify, and the method and apparatus that generates this simulated environment is called emulation platform.In order to guarantee to verify result's accuracy, require emulation platform can generate various signals and channel under the actual state, also comprise undesired signal, as much as possible the communication environment of simulating reality.For the processing speed that adapts to various checking demands and constantly promote, the construction cost of existing emulation platform has become expensive unusually, and for example, the signal generator of band spread-spectrum signal output is just up to units up to a million.High research cost and risk have become the bottleneck that restricts technological innovation.Particularly for vast medium and small research institution, many important research project are stagnated because of lacking funds, and research work can't be carried out smoothly.The inventor has carried out big quantity research at this problem, and a kind of wireless data communications emulation mode (application number: 200410051639.9) proposed, finishing at the utilization simple device and to have obtained phasic results aspect the complicated simulation work, is an important breakthrough.But, along with going deep into of research, find that this technology also exists the some shortcomings part, for example: processing power and speed is limited, can not show the duty of instant circuit intuitively, do not comprise the reset circuit that guarantees the entire circuit operate as normal, need two computers to use inconvenience.These problems have all limited the further application of this technology.
Summary of the invention
The objective of the invention is at the deficiencies in the prior art, a kind of platform of wireless communication sumulating cheaply is provided, use this platform that radio communication system and algorithm thereof complicated, at a high speed are verified exactly, reduce research cost significantly.
Purpose of the present invention is achieved by the following technical programs.
Wireless communication simulating apparatus based on FPGA and USB storage device of the present invention comprises: a signal generation device and a signal receiving and processing device, the signal receiving and processing device comprises circuit board and functional module of a computing machine, a band digital signal processing chip DSP, and computing machine is connected in series by the jtag interface of USB interface and circuit board; It is characterized in that: described signal generation device comprises a USB memory storage, USB read write line, level shifting circuit, SDRAM storage circuit and a functional module;
Described functional module is provided with a RJ45 interface and a chip that contains Low Voltage Differential Signal technology LVDS interface; Also be provided with an on-site programmable gate array FPGA chip in the described functional module, 5V external power supply interface, power circuit, FPGA configuration circuit, reset circuit, crystal resonator circuit and condition indication circuit;
In signal receiving and processing device part, fpga chip is electrically connected by the EMIF interface of I/O interface and dsp chip, the input end of power circuit and 5V external power supply interface are electrically connected, the power interface of all chips is electrically connected on the output terminal of power circuit and the functional module, the configuration interface of FPGA configuration circuit and fpga chip is electrically connected, the I/O interface of reset circuit and fpga chip is electrically connected, the global clock interface of crystal resonator circuit and fpga chip is connected in series, and the I/O interface of condition indication circuit and fpga chip is electrically connected; The input end of described LVDS interface chip is connected with the RJ45 interface, and the I/O interface of its output terminal and fpga chip is electrically connected;
In the signal generation device part, the input end of described USB read write line and USB memory storage are electrically connected, and the output terminal of USB read write line and the input end of level shifting circuit are electrically connected; The 5V power interface of the input end of power circuit, USB read write line and the 5V power interface of level shifting circuit and described 5V external power supply interface are electrically connected; Fpga chip is electrically connected by its I/O interface and level shifting circuit and SDRAM storage circuit respectively, the power interface of the power interface of all chips and level shifting circuit, SDRAM storage circuit is electrically connected on the output terminal of power circuit and the functional module, the configuration interface of FPGA configuration circuit and fpga chip is electrically connected, the I/O interface of reset circuit and fpga chip is electrically connected, the global clock interface of crystal resonator circuit and fpga chip is connected in series, and the I/O interface of condition indication circuit and fpga chip is electrically connected; The I/O interface of the input end of described LVDS interface chip and fpga chip is electrically connected, and its output terminal is connected with the RJ45 interface;
Described signal generation device and signal receiving and processing device are connected in series mutually by RJ45 interface separately.
Described USB memory storage is flash disk, portable hard drive, MP3 player, or other has the memory storage of USB interface, is used to store the signal number certificate that computing machine produces.
Described USB read write line is the CH375 type read write line of a band USB interface, is used for the data that connect USB memory storage are thereon read, and supplies with the level shifting circuit of back.
Described level shifting circuit is made of 74LVC164245 chip, triode and resistance, and the 5V voltage transitions that is used for the output of USB read write line is the 3.3V voltage that fpga chip is supported.
Described SDRAM storage circuit is made of the MT48LC8M16A2 chip, and its function is that the emulated data that will send stores by the frame structure of setting.
Described fpga chip is selected from the XC2V500 chip of U.S. XILINX company, main body as function module circuit, in the signal generation device part, to be the parallel data of will read from the USB memory storage carry out certain signal Processing by the signal flow of radio communication to its major function, converts parallel data to serial data then and send; At signal Return Reception Dept. branch, its major function is that the serial data that receives is read in, and serial data is converted to parallel data, sends to dsp chip in parallel mode after data being carried out necessary calculation process.
Described power circuit is made up of chip and peripheral components, chip is selected from the TPS767D301 chip, its function is that it is 3.3V and 1.5V with the 5V voltage transition of 5V external power supply interface input for entire circuit provides accurately and stable power, and the electric current fan-out capability is 1A.
Described FPGA configuration circuit is made up of chip, jtag interface and resistance, chip is selected from the XCF04S chip, its major function is that the internal circuit configuration to FPGA is configured when circuit powers on, to realize the set function of the present invention's design, simultaneously because the internal circuit of FPGA XC2V500 chip is to be stored by its inner SRAM, the data of original configuration will disappear after the power down, so XCF04S also plays the effect of preserving configuration data.
Described reset circuit is made up of chip, shift knob, electric capacity and resistance, chip is selected from MAX706S, its function is the function that reset signal, low pressure detection and house dog are provided for fpga chip, can when circuit is made mistakes, export reset signal automatically or produce reset signal, make circuit return to normal condition by pressing the reset switch button.
Described crystal resonator circuit is made of an active quartz oscillator, and its function is for entire circuit provides the stable clock signal, drives entire circuit and works chronologically.
Described condition indication circuit is made up of a plurality of light emitting diodes and resistance, is used for the various duties of indicating circuit, and as the power supply indication, signal sends indication, signal read-write indication or the like.
Described LVDS interface chip partly adopts the SN65LVDT41 chip at signal generation device, and its major function is that the serial signal with the output of FPGA is converted to Low Voltage Differential Signal and exports to the RJ45 interface, is convenient to signal and transmits with long distance; Partly adopt the SN65LVDT14 chip at the signal receiving and processing device, its major function is that the Low Voltage Differential Signal that the RJ45 interface is imported is converted to serial signal, is convenient to FPGA signal sampling is imported;
The circuit board of described band digital signal processing chip DSP is selected from a kind of among C6416DSK, C6711DSK or the C6701EVM.
The present invention compared with prior art has following beneficial effect:
1. the data that can make things convenient for and in time computing be produced are returned computing machine and tested and show, can draw eye pattern, planisphere, spectrogram, bit error rate figure etc., and are of many uses, easy and simple to handle.Just can finish complicated simulation study with simple equipment, the scientific research process of Jia Kuaiing has reduced experimentation cost greatly, efficiently solves the funding problems that perplexs the scientific research personnel for a long time;
2. owing to only adopted the circuit board of a computing machine and a band digital signal processing chip DSP, with respect in first to file, this simulator structure is more compact, uses also more flexibly and makes things convenient for;
3. the reception of signal is handled owing to adopted the FPGA circuit, has alleviated the workload of independent use dsp chip greatly, and with respect in first to file, this simulator can be handled wireless communication system more complicated and high speed;
4. owing to be provided with condition indication circuit and reset circuit, be convenient to understand in real time the duty of circuit, when mistake occurring, can take measures the normal function of restoring circuit timely.
5. the whole simulation device has mode of operation more flexibly.The researchist can arrive own interested algorithm configuration in the dsp chip of simulator or in the fpga chip, and then carry out experimental activity targetedly according to actual conditions.
Description of drawings
Fig. 1 is the structural representation block diagram that the present invention is based on the wireless communication simulating apparatus of FPGA and USB storage device;
Fig. 2 is the signal flow graph of signal generation device shown in Figure 1;
Fig. 3 is the signal flow graph of signal receiving and processing device shown in Figure 1;
Fig. 4 is the circuit theory diagrams of power circuit shown in Figure 1;
Fig. 5 is the block scheme of fpga chip configuration circuit shown in Figure 1;
Fig. 6 is the circuit theory diagrams of fpga chip configuration circuit shown in Figure 1;
Fig. 7 is the circuit theory diagrams of reset circuit shown in Figure 1;
Fig. 8 is the circuit theory diagrams of crystal resonator circuit shown in Figure 1;
Fig. 9 is the circuit theory diagrams of condition indication circuit shown in Figure 1;
Figure 10 is the circuit theory diagrams of signal generation device partial L VDS circuit shown in Figure 1;
Figure 11 is the circuit theory diagrams of signal receiving and processing device partial L VDS circuit shown in Figure 1;
Figure 12 is the circuit theory diagrams of the connecting circuit of fpga chip shown in Figure 1 and dsp chip;
Figure 13 is the circuit theory diagrams that flash disk shown in Figure 1, USB read write line, level shifting circuit are connected with fpga chip;
Figure 14 is the connecting circuit schematic diagram of fpga chip shown in Figure 1 and SDRAM chip;
Figure 15 is the eye pattern of the receiving end that draws of wireless communication simulating apparatus of the present invention;
Figure 16 is the planisphere of the receiving end that draws of wireless communication simulating apparatus of the present invention;
Figure 17 is the spectrogram of the receiving end that draws of wireless communication simulating apparatus of the present invention;
Figure 18 is the convergence curve comparison diagram of two kinds of adaptive algorithms of the receiving end that draws of wireless communication simulating apparatus of the present invention;
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing, but they are not the qualification to content of the present invention.
As shown in Figure 1, a kind of wireless communication simulating apparatus based on FPGA and USB storage device comprises a signal generation device 100 and a signal receiving and processing device 200.Signal generation device comprises CH375 type read write line 130, level shifting circuit 140, SDRAM storage circuit 150 and functional module 210 of a flash disk 120, a band USB interface.The signal receiving and processing device comprises a computing machine 201, a C6416DSK circuit board 202 and the functional module 210 that TIX produces, and circuit board 202 is provided with the TMS320C6416DSP chip; Computing machine 201 is connected in series by the jtag interface of USB interface and circuit board 202.
The functional module 210 of signal generation device 100 is provided with a RJ45 interface 270 and a SN65LVDT41 chip 180 that contains Low Voltage Differential Signal technology LVDS interface; Be provided with also on this functional module 210 that U.S. XILINX company produces, model is the on-site programmable gate array FPGA chip 211 of XC2V500, and 5V external power supply interface 215, power circuit 220, FPGA configuration circuit 230, reset circuit 240, crystal resonator circuit 250 and condition indication circuit 260; 5V external power supply interface 215 directly links to each other with the 5V power pins of input end, USB read write line 130 and the level shifting circuit 140 of power circuit 220.The power interface of the power interface of all chips and level shifting circuit 140, SDRAM storage circuit 150 is electrically connected on the output terminal of power circuit 220 and the functional module 210, FPGA configuration circuit 230 is electrically connected with the configuration interface of fpga chip, reset circuit 240 is electrically connected with the I/O interface of fpga chip, crystal resonator circuit 250 is connected in series with the global clock interface of fpga chip, and condition indication circuit 260 is electrically connected with the I/O interface of fpga chip; The I/O interface of the input end of described LVDS interface chip 180 and fpga chip 211 is electrically connected, and its output terminal is connected with RJ45 interface 270; Described flash disk 120 directly is inserted on the USB interface of USB read write line 130, and the input end of the output terminal of USB read write line and level shifting circuit 140 is electrically connected; The I/O interface of the output terminal of level shifting circuit 140 and fpga chip 211 is electrically connected, and the I/O interface of the address pin of SDRAM storage circuit 150 and data pin and fpga chip 211 is electrically connected.
The functional module 210 of signal receiving and processing device 200 is provided with a RJ45 interface 270 and a SN65LVDT14 chip 280 that contains Low Voltage Differential Signal technology LVDS interface; Be provided with also on this functional module 210 that U.S. XILINX company produces, model is the on-site programmable gate array FPGA chip 211 of XC2V500, and 5V external power supply interface 215, power circuit 220, FPGA configuration circuit 230, reset circuit 240, crystal resonator circuit 250 and condition indication circuit 260; 5V external power supply interface 215 directly links to each other with the input end of power circuit 220, the power interface of all chips is electrically connected on the output terminal of power circuit 220 and the functional module 210, FPGA configuration circuit 230 is electrically connected with the configuration interface of fpga chip, reset circuit 240 is electrically connected with the I/O interface of fpga chip, crystal resonator circuit 250 is connected in series with the global clock interface of fpga chip, and condition indication circuit 260 is electrically connected with the I/O interface of fpga chip; The input end of described LVDS interface chip 280 is connected with the RJ45 interface, and the I/O interface of its output terminal and fpga chip is electrically connected; Described fpga chip 211 is electrically connected by the EMIF interface of I/O interface and dsp chip.
As Fig. 1, shown in Figure 4, power circuit 220 is made up of TPS767D301 chip and some peripheral components, for entire circuit provides accurately and stable power.Its output voltage is respectively 3.3V and 1.5V, and the electric current fan-out capability is 1A.Two IN1 pins on the TPS767D301 chip link to each other with 5V external power supply voltage stabilizing interface with two IN2 pins, two capacitor C 1 in parallel and C2 between 5V external power supply interface and the ground; Two OUT1 pins link to each other and export the 1.5V power supply, connect by capacitor C 3 between 1.5V power output interface and the ground.The FB1 pin is connected with the 1.5V power output interface by resistance R 3, and the FB1 pin is by resistance R 4 ground connection simultaneously.Two OUT2 pins link to each other and export the 3.3V power supply, connect by capacitor C 4 between 3.3V power output interface and the ground.Reset pin RESET1# is connected with the 3.3V power output interface with R2 by resistance R 1 respectively with RESET2#.GND1, EN1#, GND2, EN2# pin ground connection.
As Fig. 5, shown in Figure 6, the configuration circuit 230 of FPGA adopts XCF04S chip 231, jtag interface 232 and resistance to form.The parallel port of computing machine 201 links to each other by the jtag interface 232 of JTAG simulated line 233 and 230 li of configuration circuits, and described jtag interface 232 is electrically connected with configuration interface, the FPGA configuring chip 231 of fpga chip 211 respectively.Wherein the TDI pin of the 1st pin of jtag interface 232 and XCF04S chip 231 links to each other, and the line between the B14 pin of the 2nd pin of jtag interface 232 and FPGA XC2V500 chip 211 and the TMS pin of XCF04S chip 231 links to each other; Line between the A15 pin of jtag interface the 3rd pin and FPGA XC2V500 chip 211 and the TCK pin of XCF04S chip 231 links to each other; The 4th pin of jtag interface links to each other with the C15 pin of FPGA XC2V500 chip 211; The 5th pin ground connection of jtag interface, the 6th pin links to each other with the 3.3V power interface.The P13 pin of FPGA XC2V500 chip 211 links to each other with the D0 pin of XCF04S chip 231.The C2 pin of FPGA XC2V500 chip 211 links to each other with the TD0 pin of XCF04S chip 231.The T13 pin of FPGAXC2V500 chip 211 links to each other with the OE/RESET# pin of XCF04S chip 231, and the line between them links to each other with the 3.3V power interface by resistance R 9 simultaneously.The R14 pin of FPGA XC2V500 chip 211 links to each other with the CE# pin of XCF04S chip 231, and the line between them links to each other with the 3.3V power interface by resistance R 10 simultaneously.The A2 pin of FPGA XC2V500 chip 211 links to each other with the CF# pin of XCF04S chip 231, and the line between them links to each other with the 3.3V power interface by resistance R 11 simultaneously.The P15 pin of FPGA XC2V500 chip 211 links to each other with the CLK pin of XCF04S chip 231.The T2 pin of FPGA XC2V500 chip 211 links to each other with ground by resistance R 12, and the P2 pin links to each other with ground by resistance R 13, and the R3 pin links to each other with ground by resistance R 14.The VCCINT pin of XCF04S chip 231, VCC0 pin and VCCI pin directly link to each other with the 3.3V power interface.The GND pin ground connection of XCF04S chip 231.
As shown in Figure 7, reset circuit 240 adopts MAX 706S chip 241, SW1 shift knob 242 and resistance to form.The WD0# pin of MAX706S chip 241, RESET# pin, WDI pin, PF0# pin directly link to each other with E6 pin, C8 pin, D7 pin, the B7 pin of described FPGA XC2V500 chip 211 respectively.The VCC pin of MAX706S chip 241 directly links to each other with the 3.3V power interface; The PFI pin of MAX706S chip 241 links to each other with the 5V power interface with ground with resistance R 6 by resistance R 5 respectively; The MR# pin of MAX706S chip 241 directly is connected in parallel with ground by capacitor C 5 and SW1 shift knob 242; The direct ground connection of GND pin of MAX706S chip 241.
As shown in Figure 8, crystal resonator circuit 250 is made of an active quartz oscillator, and its function is for entire circuit provides the stable clock signal, drives entire circuit and works chronologically.The OUT pin of crystal resonator circuit 250 directly links to each other with the A8 pin of described FPGA XC2V500 chip 211; The VCC pin of crystal resonator circuit 250 directly links to each other with the 3.3V power interface; The GND pin ground connection of crystal resonator circuit 250.
As shown in Figure 9, condition indication circuit 260 is made up of a plurality of light emitting diodes and resistance, and the B10 pin of FPGAXC2V500 chip 211 is by resistance R 15, light emitting diode D1 ground connection; The D10 pin of FPGA XC2V500 chip 211 is by resistance R 16, light emitting diode D2 ground connection; The E11 pin of FPGA XC2V500 chip 211 is by resistance R 17, light emitting diode D3 ground connection; The B11 pin of FPGA XC2V500 chip 211 is by resistance R 18, light emitting diode D4 ground connection; The D11 pin of FPGA XC2V500 chip 211 is by resistance R 19, light emitting diode D5 ground connection; The B12 pin of FPGA XC2V500 chip 211 is by resistance R 20, light emitting diode D6 ground connection; The D12 pin of FPGA XC2V500 chip 211 is by resistance R 21, light emitting diode D7 ground connection; The C13 pin of FPGA XC2V500 chip 211 is by resistance R 22, light emitting diode D8 ground connection; The 5V power interface is by resistance R 23, light emitting diode D9 ground connection.
As Figure 10, shown in Figure 11, described LVDS circuit, partly adopt SN65LVDT41 chip 180 at signal generation device, partly adopt SN65LVDT14 chip 280 at the signal receiving and processing device, two chips all are to be electrically connected with the I/O interface of fpga chip 211 on one side, and another side and RJ45 interface 270 are connected in series.Wherein in signal generation device 100 parts, the 1D of described SN65LVDT41 chip 180,2D, 3D, 4D pin directly link to each other with D9, C16, D16, the E13 pin of described FPGA XC2V500 chip 211 respectively; The 1Y of SN65LVDT41 chip 180,1Z, 2Y, 2Z, 3Y, 3Z, 4Y, 4Z pin directly link to each other with the 8th, 7,6,5,4,3,2,1 pin of described RJ45 interface 270 respectively; Two VCC pins of SN65LVDT41 chip 180 directly link to each other with the 3.3V power interface; Three GND pin ground connection of SN65LVDT41 chip 180; The 9th, 10 pin ground connection of described RJ45 interface 270.In signal receiving and processing device 200 parts, the 1R of described SN65LVDT14 chip 280,2R, 3R, 4R pin directly link to each other with D9, C16, D16, the E13 pin of described FPGA XC2V500 chip 211 respectively; The 1A of SN65LVDT14 chip 280,1B, 2A, 2B, 3A, 3B, 4A, 4B pin directly link to each other with the 8th, 7,6,5,4,3,2,1 pin of described RJ45 interface 270 respectively; Two VCC pin of SN65LVDT14 chip 280 directly link to each other with the 3.3V power interface; Three GND pin ground connection of SN65LVDT14 chip 280; The 9th, 10 pin ground connection of described RJ45 interface 270.
As shown in figure 12, the EMIF interface of the C6416DSK circuit board 202 of the I/O interface of described FPGA XC2V500 chip 211 and described band digital signal processing chip DSP is electrically connected.Specifically be that three ten two pins of C6416DSK circuit board 202 from AED31 to AED0 directly link to each other with C1, D1, D3, D2, E4, E3, E2, E1, F4, F3, F2, F1, F5, G5, G4, G3, G2, G1, H4, H3, H2, H1, J1, J2, J3, J4, K1, K2, K3, K4, K5, the L5 pin of described FPGAXC2V500 chip 211 respectively; Two ten pins of described C6416DSK circuit board 202 from AEA2 to AEA21 directly link to each other with P8, N8, T7, R7, P7, N7, M7, M6, T6, R6, P6, N6, T5, R5, P5, N5, R4, P4, T4, the T3 pin of described FPGA XC2V500 chip 211 respectively; The AARE# of described C6416DSK circuit board 202, AAWE#, AARDY, AAOE#, ACE3#, ACE2#, ABE3#, ABE2#, ABE1#, ABE0# directly link to each other with L3, L4, M1, M2, M3, M4, N2, N3, N1, the P1 pin of described FPGA XC2V500 chip 211 respectively;
As shown in figure 13, at signal generation device, described flash disk 120 directly is inserted on the USB interface of USB read write line CH375 module 130, the input end of the output terminal of CH375 module 130 and level shifting circuit 140 is electrically connected, and the I/0 interface of the output terminal of level shifting circuit 140 and XC2V500 chip 211 is electrically connected.Specifically be, the VCC pin of described CH375 module 130 directly links to each other with 5V external power supply interface, the 5V power supply is connected with ground by capacitor C 41, GND pin ground connection, eight pins from D0 to D7 of CH375 module 130 respectively with level shifting circuit 140 in eight pins from 1B1 to 1B8 of 74LVC164245 chip 141 directly link to each other, the A0 of CH375 module 130, RD#, WR#, STA#, five pins of CS# directly link to each other with five pins of 2B2,2B3,2B4,2B5,2B6 of described 74LVC164245 chip 141 respectively.Two VCCB-5V pins of described 74LVC164245 chip 141 directly link to each other with 5V external power supply interface.Two VCCA-3.3V pins of described 74LVC164245 chip 141 directly link to each other with the 3.3V power interface respectively with a DIR2 pin.Eight GND pin ground connection of described 74LVC164245 chip 141.Eight pins from 1A1 to 1A8 of described 74LVC164245 chip 141 directly link to each other with eight pins of J16, the J15 of described XC2V500 chip 211, J14, J13, K16, K15, K14, K13 respectively.Five pins of described 74LVC164245 chip 141 from 2A2 to 2A6 directly link to each other with five pins of L16, the L15 of described XC2V500 chip 211, L14, L13, M16 respectively.The OE1# of described 74LVC164245 chip 141, OE2# pin directly link to each other with the M14 pin of described XC2V500 chip 211 simultaneously.The DIR1 pin of described 74LVC164245 chip 141 directly links to each other with the N15 pin of described XC2V500 chip 211.The INT# pin of described CH375 module 130 links to each other with the base stage of triode Q1 by resistance R 7.The collector of described triode Q1 links to each other with the 3.3V power interface by resistance R 8 with when the N16 pin of described XC2V500 chip 211 directly links to each other.The grounded emitter of described triode Q1.
As shown in figure 14, at signal generation device, the pin of described SDRAM MT48LC8M16A2 chip 150 and the I/O interface of fpga chip 211 are electrically connected.Specifically be that three VDD pins of described MT48LC8M16A2 chip 150 directly link to each other with the 3.3V power interface with four VDDQ pins.Three VSS pins and four VSSQ pin ground connection of described MT48LC8M16A2 chip 150.13 pins from A0 to A12/NC of described MT48LC8M16A2 chip 150 directly link to each other with 13 pins of J1, the J2 of described XC2V500 chip 211, J3, J4, K1, K2, K3, K4, K5, L5, L1, L2, L3 respectively.Ten six pins of described MT48LC8M16A2 chip 150 from DQ0 to DQ15 directly link to each other with 16 pins of T3, the T4 of described XC2V500 chip 211, P4, R4, N5, P5, R5, T5, N6, P6, R6, T6, M6, M7, N7, P7 respectively.Ten pins of the WE# of described MT48LC8M16A2 chip 150, CAS#, RAS#, CS#, BA0, BA1, CKE, CLK, DQML, DQMH directly link to each other with ten pins of E1, the F4 of described XC2V500 chip 211, F3, F2, F1, F5, G5, G4, G3, G2 respectively.
As Fig. 2, shown in Figure 3, in this wireless communication simulating apparatus, signal generating apparatus 100 produces the cdma wireless communication signal by signal flow shown in Figure 2.Specifically: after computing machine 201 is handled by the step shown in the signal flow 510, the data that generate are stored by flash disk 120, and this signal flow 510 is that the first half among Fig. 2 comprises: source signal generation 500, spread spectrum 501, scrambling 502, coding 503, framing 504.By the signal flow 511 of latter half in the described FPGA XC2V500 chip service chart 2, this flow process 511 comprises: baseband modulation 505, channel 507, be superimposed with noise 506 and undesired signal 508 simultaneously.Signal receiving and processing equipment 200 is handled the cdma wireless communication signal that receives by signal flow shown in Figure 3.Specifically be that flow process 610 comprises: base band demodulating 600, Adaptive Signal Processing 601 by the signal flow 610 of first half in the described FPGA XC2V500 chip service chart 3.Signal flow 611 by latter half in described C6416DSK circuit board 202 service charts 3, flow process 611 comprises: decoding 602, descrambling 603, despreading 604, judgement 605, simultaneously the various data of handling are exported to the computing machine 201 of described signal receiving and processing equipment 200, drawn out various design sketchs such as planisphere, eye pattern, spectrogram, bit error rate figure.
Figure 15～Figure 18 is based on this wireless communication simulating apparatus, by Fig. 2 and the design sketch that signal processing flow drew shown in Figure 3, and the convergence curve comparison diagram of the eye pattern of the receiving end that drawn respectively, planisphere, spectrogram and two kinds of adaptive algorithms.
Embodiment 5～6
Claims (10)
1, a kind of wireless communication simulating apparatus based on FPGA and USB storage device, comprise a signal generation device and a signal receiving and processing device, the signal receiving and processing device comprises circuit board and functional module of a computing machine, a band digital signal processing chip DSP, and computing machine is connected in series by the jtag interface of USB interface and circuit board; It is characterized in that: described signal generation device comprises a USB memory storage, USB read write line, level shifting circuit, SDRAM storage circuit and a functional module; Described functional module is provided with a RJ45 interface and a chip that contains Low Voltage Differential Signal technology LVDS interface; Also be provided with an on-site programmable gate array FPGA chip in the described functional module, 5V external power supply interface, power circuit, FPGA configuration circuit, reset circuit, crystal resonator circuit and condition indication circuit;
In signal receiving and processing device part, fpga chip is electrically connected by the EMIF interface of I/O interface and dsp chip, the input end of power circuit and 5V external power supply interface are electrically connected, the power interface of all chips is electrically connected on the output terminal of power circuit and the functional module, the configuration interface of FPGA configuration circuit and fpga chip is electrically connected, the I/O interface of reset circuit and fpga chip is electrically connected, the global clock interface of crystal resonator circuit and fpga chip is connected in series, and the I/O interface of condition indication circuit and fpga chip is electrically connected; The input end of described LVDS interface chip is connected with the RJ45 interface, and the I/O interface of its output terminal and fpga chip is electrically connected;
In the signal generation device part, the input end of described USB read write line and USB memory storage are electrically connected, and the output terminal of USB read write line and the input end of level shifting circuit are electrically connected; The 5V power interface of the input end of power circuit, USB read write line and the 5V power interface of level shifting circuit and described 5V external power supply interface are electrically connected; Fpga chip is electrically connected by its I/O interface and level shifting circuit and SDRAM storage circuit respectively, the power interface of the power interface of all chips and level shifting circuit, SDRAM storage circuit is electrically connected on the output terminal of power circuit and the functional module, the configuration interface of FPGA configuration circuit and fpga chip is electrically connected, the I/O interface of reset circuit and fpga chip is electrically connected, the global clock interface of crystal resonator circuit and fpga chip is connected in series, and the I/O interface of condition indication circuit and fpga chip is electrically connected; The I/O interface of the input end of described LVDS interface chip and fpga chip is electrically connected, and its output terminal is connected with the RJ45 interface;
Described signal generation device and signal receiving and processing device are connected in series mutually by RJ45 interface separately.
2, wireless communication simulating apparatus according to claim 1 is characterized in that: described USB read write line is the CH375 type read write line of a band USB interface.
3, wireless communication simulating apparatus according to claim 1, it is characterized in that: described level shifting circuit is made of 74LVC164245 chip, triode and resistance, and the 5V voltage transitions that is used for the output of USB read write line is the 3.3V voltage that fpga chip is supported.
4, wireless communication simulating apparatus according to claim 1 is characterized in that: described fpga chip is selected from the XC2V500 chip of U.S. XILINX company.
5, wireless communication simulating apparatus according to claim 1 is characterized in that: described power circuit is made up of TPS767D301 chip and peripheral components, for entire circuit provides accurately and stable power; Its output voltage is set at 3.3V and 1.5V respectively, and output current is set at 1A.
6, wireless communication simulating apparatus according to claim 1, it is characterized in that: described reset circuit is made up of MAX 706S chip, shift knob, electric capacity and resistance, detect and watchdog function for fpga chip provides reset signal, low pressure, when circuit is made mistakes, make circuit return to normal condition.
7, wireless communication simulating apparatus according to claim 1 is characterized in that: described crystal resonator circuit is made of an active quartz oscillator, for entire circuit provides the stable clock signal, drives entire circuit and works chronologically.
8, wireless communication simulating apparatus according to claim 1 is characterized in that: described LVDS interface chip, partly adopt the SN65LVDT41 chip at signal generation device, and partly adopt the SN65LVDT14 chip at the signal receiving and processing device.
9, wireless communication simulating apparatus according to claim 1 is characterized in that: the circuit board of described band digital signal processing chip DSP is selected from a kind of among C6416DSK, C6711DSK or the C6701EVM.
10, wireless communication simulating apparatus according to claim 1, it is characterized in that: described FPGA configuration circuit is made up of XCF04S chip, jtag interface and resistance, internal circuit configuration to FPGA when circuit powers on is configured, and preserves configuration data; Described condition indication circuit is made up of a plurality of light emitting diodes and resistance, is used for the various duties of indicating circuit; Described SDRAM storage circuit is made of the MT48LC8M16A2 chip, and the emulated data that is used for sending stores by the frame structure of setting.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102567202A (en) * | 2011-12-22 | 2012-07-11 | 广州中大微电子有限公司 | Double-interface intelligent card simulator based on field programmable gata array (FPGA) |
| CN103217618A (en) * | 2013-04-16 | 2013-07-24 | 青岛中星微电子有限公司 | Device and method for testing field programmable gate array (FPGA) development board |
| CN103458254A (en) * | 2013-04-03 | 2013-12-18 | 厦门华侨电子股份有限公司 | System for adjusting TV white balance by using USB flash disk for replacing instrument and method thereof |
| CN105515927A (en) * | 2015-11-27 | 2016-04-20 | 武汉微创光电股份有限公司 | Remote serial port communication system and method based on Ethernet Cat.5 wiring framework |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| EP1164487B1 (en) * | 2000-06-16 | 2003-02-19 | Europe Technologies S.A. | Device for the functional reproduction of a specific intergrated circuit and its usage as an emulation device |
| CN2549537Y (en) * | 2002-06-04 | 2003-05-07 | 武汉大学 | High speed monochip system platform based on programmable logic elements |
| CN1204517C (en) * | 2003-01-15 | 2005-06-01 | 西安交通大学 | Restructurable hardware designing platform for intelligent electric equipment |
| CN100492996C (en) * | 2004-09-28 | 2009-05-27 | 中山大学 | Simulating method for radio data communication |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102567202A (en) * | 2011-12-22 | 2012-07-11 | 广州中大微电子有限公司 | Double-interface intelligent card simulator based on field programmable gata array (FPGA) |
| CN103458254A (en) * | 2013-04-03 | 2013-12-18 | 厦门华侨电子股份有限公司 | System for adjusting TV white balance by using USB flash disk for replacing instrument and method thereof |
| CN103458254B (en) * | 2013-04-03 | 2016-01-06 | 厦门厦华投资有限公司 | A kind of system and method thereof being replaced instrument adjustment TV white balance by USB flash disk |
| CN103217618A (en) * | 2013-04-16 | 2013-07-24 | 青岛中星微电子有限公司 | Device and method for testing field programmable gate array (FPGA) development board |
| CN103217618B (en) * | 2013-04-16 | 2015-09-09 | 青岛中星微电子有限公司 | A kind of apparatus and method of testing FPGA development board |
| CN105515927A (en) * | 2015-11-27 | 2016-04-20 | 武汉微创光电股份有限公司 | Remote serial port communication system and method based on Ethernet Cat.5 wiring framework |
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