CN1855733A - Convolution coding method and coder therefor - Google Patents
Convolution coding method and coder therefor Download PDFInfo
- Publication number
- CN1855733A CN1855733A CNA2005100345192A CN200510034519A CN1855733A CN 1855733 A CN1855733 A CN 1855733A CN A2005100345192 A CNA2005100345192 A CN A2005100345192A CN 200510034519 A CN200510034519 A CN 200510034519A CN 1855733 A CN1855733 A CN 1855733A
- Authority
- CN
- China
- Prior art keywords
- bit
- result
- output
- bits
- multinomial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Error Detection And Correction (AREA)
Abstract
The invention makes convolution code calculation for the inputted bits to generate multi outputting bits, and in term of the encoding speed and said multi outputting bits configures multi polynomials whose coefficient corresponds to each said outputting bit. The method comprises: receiving an inputted bit; combining the inputted bit with data saved in register, and outputting a first result; in term of the encoding speed and the sequence of outputting bit, selecting the polynomial coefficient, and then outputting a second result; making bit-by-bit AND operation for the first result and the second result, and outputting a third result; making bib nonequivalence operation for interior of bit of the third result, and outputting the encoding result. The invention can support all kinds of encoding speed and encoding format.
Description
Technical field
The invention belongs to moving communicating field, relate in particular to the convolutional coding method and the convolution coder that use in a kind of WCDMA communication system.
Background technology
When convolutional encoding has higher encoding process gain, have the better simply characteristics of realization of decoding, in various chnnel codings, obtained using widely.In WCDMA (Wideband Code DivisionMultiple Access, Wideband Code Division Multiple Access (WCDMA)), be used, be mainly used in handling the more sensitive business of time-delay, as speech business etc. as a kind of important coding method.
As shown in Figure 1, in 3G,PP2 25.212 agreements, convolutional encoding comprises 1/2 convolutional encoding and 1/3 convolutional encoding.1/2 convolutional encoding and 1/3 convolutional encoding are different to the processing time of each input bit, for 1/2 convolutional encoding, and 1 corresponding 2 output bit of input bit, for 1/3 convolutional encoding, 1 corresponding 3 output bit of input bit.
Each output bit of convolutional encoding is certain the several register in the shift register to be done mould 2 add (XOR) operation, and common way is that the register of corresponding tap position is directly done XOR.For example use D0 respectively, D1, D2......D7 represent the content of each register of shift register, for 1/2 convolutional encoding, 2 output bits can be expressed as respectively (MOD 2 of input+D1+D2+D3+D7) and (input ++ D0+D1+D2+D4+D6+D7) MOD 2.For 1/3 convolutional encoding, 3 output bits can be expressed as (MOD 2 of input+D1+D2+D4+D5+D6+D7), (MOD 2 of input+D0+D2+D3+D6+D7) and (MOD 2 of input+D0+D1+D4+D7) respectively.
Fig. 2 shows the structure of supporting the convolution coder of 1/2 and 1/3 convolutional encoding in the prior art simultaneously, the data that are input to shift register 201 add arithmetic unit 202 by mould 2 and carry out xor operation, in order to support 1/2 convolutional encoding and 1/3 convolutional encoding simultaneously, mould 2 adds has 5 cover dies 2 to add arithmetic element (1～5) in the arithmetic unit 202, finish the calculating of 1/2 convolutional encoding, 2 output bit and 3 output of 1/3 convolutional encoding bit respectively, MUX 203 selects certain fortune mould 2 of output to add the bit of arithmetic element according to the output bit order under coding mode (1/2 coding is 1/3 coding still) and the corresponding coding mode.
Therefore existing convolution coder needs many moulds 2 add arithmetic element, and each mould 2 adds arithmetic element and all solidify according to specific multinomial, if support other polynomial computation, needs to revise hardware.
Summary of the invention
The objective of the invention is to solve the more mould 2 of consumption that prior art exists and add arithmetic element in realizing the convolutional encoding process, and only can support particular polynomial, problem that can not flexible configuration.
To achieve these goals, the invention provides a kind of convolutional coding method, input bit is carried out the convolutional encoding computing, export a plurality of output bits, dispose a plurality of multinomials according to code rate and output number of bits, described polynomial coefficient is corresponding with each output bit;
Described method comprises the steps:
Receive input bit, the data in input bit and the register are merged, export first result;
Order according to code rate and output bit is selected corresponding multinomial coefficient, exports second result;
Described first result and second result are done step-by-step and computing, export the 3rd result;
Described the 3rd result's bit internal is done an XOR, the output encoder result.
Described code rate is 1/2 and 1/3 coding.
Described step-by-step and computing are for doing described first result and second result's Bit data the logical AND operation of corresponding bit.
Described multinomial coefficient is 9 bits, and lowest order is used to control input bit.
In order to realize goal of the invention better, the present invention further provides a kind of convolution coder, be used for input bit is carried out the convolutional encoding computing, export a plurality of output bits, described convolution coder comprises:
Dispose a plurality of polynomial multinomial memory cell according to code rate and output number of bits, described polynomial coefficient is corresponding with each output bit;
Receive input bit, the data in input bit and the register are merged, export first result's shift register;
Order according to code rate and output bit is selected corresponding multinomial coefficient, exports second result's multinomial selected cell;
Described first result and second result are done step-by-step and computing, export the 3rd result's position and arithmetic element; And
Described the 3rd result's bit internal is done an XOR, and output encoder result's mould 2 adds arithmetic element.
Described code rate is 1/2 and 1/3 coding.
Described shift register is 8 bits.
The logical AND operation of corresponding bit is done in described step-by-step and computing for the Bit data that the Bit data and the multinomial selected cell of shift register output are exported.
Described multinomial coefficient is 9 bits, and lowest order is used to control input bit.
The present invention can support 1/2 and 1/3 coding simultaneously, and can dispose multinomial by software flexible, supports the coding computing of various code rates, realizes simple.
Description of drawings
Fig. 1 is the general pie graph of 1/2 and 1/3 convolution coder;
Fig. 2 is the structure chart of convolution coder in the prior art;
Fig. 3 is the structure chart of convolution coder provided by the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The present invention is optimized convolutional encoding calculation process of the prior art, dispose corresponding multinomial according to different code rates and output number of bits, the corresponding specific output bit of each multinomial coefficient, multinomial is configured by software, supports the change of various multinomial coefficients flexibly.
When each output bit is encoded output, at first, select one with this output bit corresponding multinomial coefficient, do " step-by-step with " with the corresponding bit of the corresponding bit of this multinomial coefficient and shift register (comprising input bit) and operate, obtain intermediate object program.Secondly, all bits in the intermediate object program that the first step is obtained are done " mould 2 adds " (XOR) operation.Therefore, the present invention only needs 1 position and arithmetic element and 1 mould 2 to add the computing that arithmetic element just can be finished 1/2 or 1/3 convolutional encoding, has simplified the structure of existing convolution coder.
1/2 convolutional encoding and 1/3 convolutional encoding all are the result in the shift register to be carried out mould 2 add, and the register of just participating in computing in each output tap is different.For 1/2 convolutional encoding of stipulating in 3G,PP2 25.212 agreements, the register that computing is participated in first bit output is respectively 4 registers such as the 1st, 2,3,7; The register that computing is participated in second bit output is respectively 5 registers such as the 0th, 1,2,4,6,7.For 1/3 convolutional encoding, the register that computing is participated in the output of first bit is respectively 1,2,4,5,6,7; The register that computing is participated in the output of second bit is respectively 0,2,3,6,7; The register that computing is participated in the output of the 3rd bit is respectively 0,1,4,7.Therefore in the present invention, for 1/2 convolutional encoding and 1/3 convolutional encoding, be designed to shared same set of eight bit shift register.
Fig. 3 shows the structure of convolution coder provided by the invention, comprises that shift register 301, multinomial memory cell 302, multinomial selected cell 303, position add arithmetic element 305 with arithmetic element 304 and mould 2.
Shift register 301 comprises 8 registers, and input bit is carried out shifting function successively, every input one bit, and shift register 301 displacements are once.The data of shift register 301 outputs are the data that the content of input bit and 8 registers are merged into one 9 bit, input bit, No. 0 register, No. 1 register ... No. 7 registers are the 0th of corresponding dateouts respectively, the 1st, the 2nd ... and the 8th.
The a plurality of multinomials of multinomial memory cell 302 storages, multinomial coefficient is relevant with the register that computing is participated in bit output, comprise five multinomial coefficients (1～5), first bit output of first bit of corresponding 1/2 convolutional encoding output respectively, the output of second bit and 1/3 convolutional encoding, the output of second bit and the output of the 3rd bit.Multinomial coefficient has default value, 1/2 convolutional encoding of corresponding 3G,PP2 25.212 agreements regulation and the multinomial coefficient of 1/3 convolutional encoding, in the present invention simultaneously, multinomial can be configured by software, can supported protocol to the change of multinomial coefficient.
In order to support input bit also can add computing by selected participation mould 2, multinomial coefficient is designed to 9 bits, and lowest order is used to control input bit.Accordingly, output of first bit and the corresponding multinomial coefficient of second bit output for 1/2 convolutional encoding is respectively 200011201 and 120201111.The output of first bit, the output of second bit and the corresponding multinomial coefficient of the 3rd bit output for 1/3 convolutional encoding are respectively 111201201,120012011 and 200200111.Whether the corresponding register position of every value representation has tap in the multinomial coefficient, and 1 expression has tap, the no tap of 0 expression.The 0th bit represents whether the input bit place has tap, the 1st bit to represent whether the 0th register place in the shift register 301 has tap ... the 8th bit represents whether the 7th register place in the shift register 301 has tap.
Multinomial selected cell 303 is selected polynomial coefficients corresponding according to the order of current code rate (1/2 convolutional encoding still is 1/3 convolutional encoding) and output bit.In 1/2 convolutional encoding, if current output first bit that needs, the coefficient of selection multinomial 1; Export second bit if desired, select the coefficient of multinomial 2.In 1/3 convolutional encoding, if current output first bit that needs, the coefficient of selection multinomial 3; Export second bit if desired, select the coefficient of multinomial 4; Export the 3rd bit if desired, select the coefficient of multinomial 5.
The result of position and 304 pairs of shift registers of arithmetic element 301 output and the multinomial coefficient of multinomial selected cell 303 outputs are done " step-by-step and " computing, and operation result is outputed to mould 2 add arithmetic element 305.Here said " step-by-step with " computing is meant 9 Bit data A[8:0 to shift register 301 outputs] and 9 Bit data B[8:0 of multinomial selected cell 303 outputs] " logical AND " of doing corresponding bit operate, be the 0th bit A [0] of A and the 0th bit B[0 of B] do " logical AND ", the 1st bit A [1] of A and the 1st bit B[1 of B] do " logical AND " ... the 8th bit A [8] of A and the 8th bit B[8 of B] do " logical AND ".
The result that mould 2 adds arithmetic element 305 contrapositions and arithmetic element 304 outputs carries out " position XOR " operation of 9 bit internal, and operation result is exported.Here said " position XOR " operation is meant that 9 Bit datas are carried out mould 2 adds computing.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1, a kind of convolutional coding method carries out the convolutional encoding computing to input bit, exports a plurality of output bits, it is characterized in that, disposes a plurality of multinomials according to code rate and output number of bits, and described polynomial coefficient is corresponding with each output bit;
Described method comprises the steps:
Receive input bit, the data in input bit and the register are merged, export first result;
Order according to code rate and output bit is selected corresponding multinomial coefficient, exports second result;
Described first result and second result are done step-by-step and computing, export the 3rd result;
Described the 3rd result's bit internal is done an XOR, the output encoder result.
2, convolutional coding method as claimed in claim 1 is characterized in that, described code rate is 1/2 and 1/3 coding.
3, convolutional coding method as claimed in claim 1 is characterized in that, described step-by-step and computing are for doing described first result and second result's Bit data the logical AND operation of corresponding bit.
4, convolutional coding method as claimed in claim 1 is characterized in that, described multinomial coefficient is 9 bits, and lowest order is used to control input bit.
5, a kind of convolution coder is used for input bit is carried out the convolutional encoding computing, exports a plurality of output bits, it is characterized in that described convolution coder comprises:
Dispose a plurality of polynomial multinomial memory cell according to code rate and output number of bits, described polynomial coefficient is corresponding with each output bit;
Receive input bit, the data in input bit and the register are merged, export first result's shift register;
Order according to code rate and output bit is selected corresponding multinomial coefficient, exports second result's multinomial selected cell;
Described first result and second result are done step-by-step and computing, export the 3rd result's position and arithmetic element; And
Described the 3rd result's bit internal is done an XOR, and output encoder result's mould 2 adds arithmetic element.
6, convolution coder as claimed in claim 5 is characterized in that, described code rate is 1/2 and 1/3 coding.
7, convolution coder as claimed in claim 5 is characterized in that, described shift register is 8 bits.
8, convolution coder as claimed in claim 5 is characterized in that, the logical AND operation of corresponding bit is done in described step-by-step and computing for the Bit data that the Bit data and the multinomial selected cell of shift register output are exported.
9, convolution coder as claimed in claim 5 is characterized in that, described multinomial coefficient is 9 bits, and lowest order is used to control input bit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100345192A CN100477546C (en) | 2005-04-29 | 2005-04-29 | Convolution coding method and coder thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100345192A CN100477546C (en) | 2005-04-29 | 2005-04-29 | Convolution coding method and coder thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1855733A true CN1855733A (en) | 2006-11-01 |
| CN100477546C CN100477546C (en) | 2009-04-08 |
Family
ID=37195632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100345192A Expired - Fee Related CN100477546C (en) | 2005-04-29 | 2005-04-29 | Convolution coding method and coder thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100477546C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010000147A1 (en) * | 2008-07-03 | 2010-01-07 | 华为技术有限公司 | Method, apparatus and system for the random linear network coding |
| CN102265266A (en) * | 2011-06-01 | 2011-11-30 | 华为技术有限公司 | Method and apparatus for coding data address |
| CN102916707A (en) * | 2012-10-10 | 2013-02-06 | 北京邮电大学 | Compatible convolutional code generator polynomial determination method, coding method and coder |
| CN108011640A (en) * | 2016-11-01 | 2018-05-08 | 中国科学院沈阳自动化研究所 | One kind is used for the universal method of (2,1, N) convolutional encoding |
-
2005
- 2005-04-29 CN CNB2005100345192A patent/CN100477546C/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010000147A1 (en) * | 2008-07-03 | 2010-01-07 | 华为技术有限公司 | Method, apparatus and system for the random linear network coding |
| CN101621353B (en) * | 2008-07-03 | 2013-08-07 | 华为技术有限公司 | Method, device and system for random linear network encoding |
| US8553784B2 (en) | 2008-07-03 | 2013-10-08 | Huawei Technologies Co., Ltd. | Method, apparatus and system for random linear network coding |
| CN102265266A (en) * | 2011-06-01 | 2011-11-30 | 华为技术有限公司 | Method and apparatus for coding data address |
| WO2011157160A2 (en) * | 2011-06-01 | 2011-12-22 | 华为技术有限公司 | Method and device for encoding address of data |
| WO2011157160A3 (en) * | 2011-06-01 | 2012-04-19 | 华为技术有限公司 | Method and device for encoding address of data |
| US9442845B2 (en) | 2011-06-01 | 2016-09-13 | Huawei Technologies Co., Ltd. | Encoding a data address using XOR operation wherein address bits are transformed by multiple preset polynomials |
| CN102916707A (en) * | 2012-10-10 | 2013-02-06 | 北京邮电大学 | Compatible convolutional code generator polynomial determination method, coding method and coder |
| CN102916707B (en) * | 2012-10-10 | 2016-02-24 | 北京邮电大学 | Compatible convolutional code generator polynomial defining method, coding method and encoder |
| CN108011640A (en) * | 2016-11-01 | 2018-05-08 | 中国科学院沈阳自动化研究所 | One kind is used for the universal method of (2,1, N) convolutional encoding |
| CN108011640B (en) * | 2016-11-01 | 2021-01-12 | 中国科学院沈阳自动化研究所 | General method for (2,1, N) convolutional coding |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100477546C (en) | 2009-04-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1168221C (en) | Partitioned deinterleaver memory for MAP decoder | |
| CN1227816C (en) | Efficient trellis state metric normalization | |
| CN1272733A (en) | Rate match and channel interweaving of communication system | |
| US7043682B1 (en) | Method and apparatus for implementing decode operations in a data processor | |
| CN101079641A (en) | 2-dimensional interleaving apparatus and method | |
| CN101036299A (en) | A method of and apparatus for implementing a reconfigurable trellis-type decoding | |
| US20120147988A1 (en) | Encoding module, apparatus and method for determining a position of a data bit within an interleaved data stream | |
| US20040032347A1 (en) | Soft-output decoder with computation decision unit | |
| US6523146B1 (en) | Operation processing apparatus and operation processing method | |
| CN1168224C (en) | High-speed ACS unit for viterbi decoder | |
| CN1853350A (en) | Unified viterbi/turbo decoder for mobile communication systems | |
| US7170432B2 (en) | Addresses generation for interleavers in turbo encoders and decoders | |
| CN1855733A (en) | Convolution coding method and coder therefor | |
| CN1830151A (en) | Viterbi decoder | |
| US7200798B2 (en) | Unified serial/parallel concatenated convolutional code decoder architecture and method | |
| CN1466818A (en) | Decoder for trellis-based channel encoding | |
| JP2000353965A (en) | Method and device for interleaving, turbo encoding method and turbo encoder | |
| CN1140148C (en) | Method for executing Tebo decoding in mobile communication system | |
| CN1159933C (en) | Universal convolution encoder and viterbi decoder | |
| CN1335684A (en) | High-speed Turbo code decoder | |
| CN1147169C (en) | Decoding method and decoder for Turbo code | |
| CN1787386A (en) | Method for path measuring me mory of viterbi decoder | |
| CN115664429A (en) | Dual-mode decoder suitable for LDPC and Turbo | |
| CN100336305C (en) | High performance TURBO and VIRTERBI channel decoding in digital signal processors | |
| CN112804026B (en) | Frequency and time frequency interleaving method and system in OFDM system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090408 Termination date: 20180429 |