CN1851670A - Limited processor storage access method, system and accessible storage unit - Google Patents
Limited processor storage access method, system and accessible storage unit Download PDFInfo
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- CN1851670A CN1851670A CN 200610083306 CN200610083306A CN1851670A CN 1851670 A CN1851670 A CN 1851670A CN 200610083306 CN200610083306 CN 200610083306 CN 200610083306 A CN200610083306 A CN 200610083306A CN 1851670 A CN1851670 A CN 1851670A
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Abstract
The present invention includes restriction processor and addressable memory unit pre-engaging all classes of memory access command format, when restriction processor determined to access memory, transmitting memory access command to addressable memory, addressable memory according to restriction processor memory access command format to determine said memory access command type, then executing relevant operation to memory according to said memory access command. The present invention discloses a restriction processor access memory system, including restriction processor, addressable memory unit and memory. The present invention also discloses an addressable memory unit, including memory access command receiving module and memory access response transmitting module. The present invention realizes restriction processor accessing memory through addressable memory unit, greatly enlarging restriction processor application field.
Description
Technical field
The present invention relates to the memory access techniques field, be specifically related to method, system and the addressable memory unit of limited processor reference-to storage.
Background technology
At present, some processor since instruction restriction wait can't reference-to storage, for example: during a lot of network processing unit (NP) initial design based on using it for the consideration of transmitting and handling the Ethernet message, simultaneously in order to save resource and to improve and transmit and treatment effeciency, and not have for the function of its increase reference-to storage as the NP-1C/NP2 that EZCHIP company designs.But, development along with network security etc., under some applied environment as: carrying out IP reorganization or transmission control protocol (TCP) stream when recovering, need network processing unit can visit the storer of storing IP burst or IP bag, this just feasible range of application that does not possess the network processing unit of reference-to storage ability is restricted.Processor that can't reference-to storage is called limited processor.
Summary of the invention
In view of this, the present invention at first provides a kind of method of limited processor reference-to storage, makes that limited processor can reference-to storage, enlarges the range of application of limited processor;
The invention provides a kind of system of limited processor reference-to storage, realize the visit of limited processor storer;
The invention provides a kind of addressable memory unit, by this unit limited processor addressable memory.
For achieving the above object, technical scheme of the present invention is achieved in that
The make an appointment form of various types of memory visit order of a kind of method of limited processor reference-to storage, limited processor and addressable memory unit comprises:
A, limited processor determine to want reference-to storage, send memory access command to the addressable memory unit;
The form of the memory access command that B, addressable memory unit send according to limited processor is determined the type of this memory access command, then according to this memory access command, storer is carried out corresponding operation.
The described memory access command of steps A is: obtain the memory parameter order,
And, the described addressable memory of step B unit is carried out corresponding operation to storer and comprised: the addressable memory unit is according to the storage address information of memory parameter in storer of self preserving, from storer, read memory parameter, this memory parameter is returned to limited processor.
The described memory access command of steps A is: read command,
And, the rapid described addressable memory of B unit is carried out corresponding operation to storer and comprised: the addressable memory unit is according to the address information of carrying in this read command, reading of data in the space corresponding with described address information returns to limited processor with these data then from storer.
The described memory access command of steps A is: write order,
And the rapid described addressable memory of B unit is carried out corresponding operation to storer and comprised: the addressable memory unit is written to described data in the space corresponding with described address information in the storer according to address information of carrying in this write order and data.
The form of the described memory access command of steps A is: command id field, order length information field, address information field and data field,
And the described addressable memory of step B unit determines that according to the form of the memory access command that limited processor is sent the type of this memory access command is: the content of the command id field that the addressable memory unit hits according to this memory access is determined the type of this memory access command.
Further comprise after the described step B: the addressable memory unit returns the memory access response to limited processor.
The form of described memory access response comprises: visit successfully or fail identification field, response length information field and data field further comprise: the command sequence number field.
Described addressable memory unit is field programmable logic array (FPLA) FPGA unit or application-specific integrated circuit ASIC unit.
A kind of system of limited processor reference-to storage, this system comprises: limited processor, addressable memory unit and storer, wherein:
Limited processor is used for the form with addressable memory unit agreement various types of memory visit order, when determining to want reference-to storage, to addressable memory unit transmission memory access command;
The addressable memory unit, the form of the memory access command of sending according to limited processor is determined the type of this memory access command, according to this memory access command, storer is carried out corresponding operating;
Storer according to the operation of addressable memory unit, provides data or receives the data that the addressable memory unit writes to the addressable memory unit.
A kind of addressable memory unit, this unit comprises: memory access command receiver module and memory access response sending module, wherein:
The memory access command receiver module, be used for form with limited processor agreement various types of memory visit order, determine the type of the memory access command that limited processor is sent according to described form, storer is carried out corresponding operating according to this memory access command;
Memory access response sending module is used for the form with limited processor agreement various types of memory access response, and the operation of storer is finished, and operating result is carried in the described memory access response sends to limited processor.
Compared with prior art, the present invention is by the make an appointment form of various types of memory visit order of limited processor and addressable memory unit, after the memory access command that limited processor sends is received in the addressable memory unit, determine the type of this memory access command according to the form of this memory access command, then storer is carried out corresponding operating, make limited processor to have enlarged the range of application of limited processor greatly by the visit of addressable memory unit realization to storer.
Description of drawings
The process flow diagram of the limited processor reference-to storage that Fig. 1 provides for the embodiment of the invention;
The system chart one of the limited processor reference-to storage that Fig. 2 provides for the embodiment of the invention;
The system chart two of the limited processor reference-to storage that Fig. 3 provides for the embodiment of the invention.
Embodiment
Because field programmable logic array (FPLA) (FPGA) unit or special IC (ASIC) unit etc. can reference-to storage, and can carry out the transmission of signaling and data between limited processor and FPGA unit or ASIC unit.Therefore, core concept of the present invention is: when limited processor is wanted reference-to storage in decision, corresponding signaling or data are sent to the unit of addressable memories such as FPGA or ASIC unit earlier, the unit of addressable memory is according to the operation of storer that conducts interviews of described signaling or data, and makes the operation result and return to limited processor.
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
Fig. 1 is the process flow diagram of the limited processor reference-to storage that provides of the embodiment of the invention, and as shown in Figure 1, its concrete steps are as follows:
Step 101: limited processor and addressable memory unit are as FPGA or ASIC unit the make an appointment form of various types of memory visit order and various types of memory access response, and all preserve the corresponding relation of reservoir visit order form and memory access command type, and the corresponding relation of memory access response format and memory access respond style.
Step 102: limited processor determines to want reference-to storage, by the 4th generation small computer system interface parallel interface (SPI4) or the peripheral component interconnect standard interfaces such as (PCLe) of self, send the memory access command of corresponding types to the addressable memory unit.
The memory access command of limited processor and addressable memory unit agreement mainly contains three classes: obtain the memory parameter order, and read command and write order, dissimilar memory commands can be distinguished by command id.The form of memory access command is as follows:
Command id field: the type that is used for the id memory visit order.For example: obtaining the memory parameter order can represent by 0x000; Read command can be represented by 0x100; Write order can be represented by 0x200;
Order length information field: the length of representing this order.Order length does not comprise command id field and the shared length of order length information field;
The address information field: when order was read command or write order, this field was effective, and address or write address are read in expression;
Data field: when order was write order, this field was effective, the expression write data.
Step 103: after this memory access command is received in the addressable memory unit,, learn the type of this memory access command according to the memory access command form of self preserving and the corresponding relation of memory access command type.
Particularly, can learn the type of this memory access command by the content of the command id field in the memory access command.
Step 104: the addressable memory unit is carried out corresponding read or write according to the type of the memory access command of determining to storer.
Particularly, if what limited processor sent is to obtain the memory parameter order, the storage address information of the memory parameter that can preserve in advance according to self of addressable memory unit then, from the corresponding address of storer, read the parameter of storer, and this parameter returned to limited processor, here, the parameter of storer comprises: the storage size of storer, read-write time delay etc.; If what limited processor sent is read command, then the addressable memory unit can read the data in corresponding address space according to the address information of carrying in this read command from storer, and these data are returned to limited processor; If what limited processor sent is write order, then the addressable memory unit can be according to the address information of carrying in this write order, and the data of carrying in this write order are written to the corresponding address space of storer, and returns to limited processor and to write successfully response message; If the memory access command that addressable memory cell processing limited processor is sent failure is then returned the memory access response of carrying the visit failure information to limited processor.
Step 105: the end of operation of reference-to storage is carried out in the addressable memory unit, according to the memory access response format of self preserving and the corresponding relation of memory access respond style, return the memory access response of carrying operating result accordingly to limited processor.
Corresponding with three types of memory access command, the memory access response that the addressable memory unit sends to limited processor also mainly contains three classes: obtain the memory parameter response, read response and write response, the form of memory access response is as follows:
Visit successfully or the failure identification field: the expression memory access command runs succeeded or fails.For example: represent to visit successfully with 0x0, represent the visit failure with 0x1;
Response length information field: the length of representing this response.This response length is not wrapped order success or failure identification field and the shared length of response length information field;
Data field: when order when obtaining memory parameter order or read command, this field is effective, represents memory parameter or read data.
It is to be noted, if the addressable memory unit is that serial is carried out when the processing memory visit order, that is: only handle previous memory access command from limited processor, and after limited processor returns response at this order, just begin to handle next memory access command from limited processor, at this moment, owing to the memory access response is that order sends, so limited processor can not produce the situation of the corresponding relation that can't distinguish response and order; But, if the addressable memory unit adopts parallel mode processing memory visit order, then in order to distinguish response and the corresponding relation of ordering, in step 102, when limited processor sends memory access command to the addressable memory unit, need in this order, to carry command sequence number, simultaneously, in step 105, the addressable memory unit executes the operation of reference-to storage, and when limited processor returns the memory access response, need in this response, to carry corresponding command sequence number.
Fig. 2 is the system chart one of the limited processor reference-to storage that provides of the embodiment of the invention, and as shown in Figure 2, this system comprises: limited processor 21, addressable memory unit 22 and storer 23, wherein:
Limited processor 21: be used for and the make an appointment form of various types of memory visit order and various types of memory access response of addressable memory unit 22, and preserve the corresponding relation of memory access command form and memory access command type, and the corresponding relation of memory access response format and memory access respond style; When reference-to storage is wanted in decision, send the memory access command of corresponding types to addressable memory unit 22, and receive the memory access response of returning from addressable memory unit 22.
Addressable memory unit 22: be used for and the make an appointment form of various types of memory visit order and various types of memory access response of limited processor 21, and preserve the corresponding relation of memory access command form and memory access command type, and the corresponding relation of memory access response format and memory access respond style; After receiving the memory access command that limited processor 21 is sent,,, according to this memory access command storer 23 is carried out corresponding read or write then in the type that self finds this memory access command according to the form of this memory access command; End of operation returns the memory access response of carrying operating result to limited processor 21.
Storer 23: be used for operation, receive the data that addressable memory unit 22 is sent, or provide data to addressable memory unit 22 according to 22 execution of addressable memory unit.
Fig. 3 is the system chart two of the limited processor reference-to storage that provides of the embodiment of the invention, as shown in Figure 3, this figure compares with Fig. 2, and addressable memory unit 22 mainly comprises: memory access command receiver module 221 and memory access response sending module 222, wherein:
Memory access command receiver module 221: the corresponding relation that is used to preserve memory access command form and memory access command type, after receiving the memory access command that limited processor 21 is sent, according to described corresponding relation, determine the type of this memory access command, according to this memory access command, storer 23 is carried out corresponding read or write then.
Memory access response sending module 222: the corresponding relation that is used to preserve memory access response format and memory access respond style, after the read or write to storer 23 finished, the memory access response that will carry operating result according to described corresponding relation accordingly sent to limited processor 21.
The above only is process of the present invention and method embodiment, in order to restriction the present invention, all any modifications of being made within the spirit and principles in the present invention, is not equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1, a kind of method of limited processor reference-to storage is characterized in that, the make an appointment form of various types of memory visit order of limited processor and addressable memory unit, and this method comprises:
A, limited processor determine to want reference-to storage, send memory access command to the addressable memory unit;
The form of the memory access command that B, addressable memory unit send according to limited processor is determined the type of this memory access command, then according to this memory access command, storer is carried out corresponding operation.
2, the method for claim 1 is characterized in that, the described memory access command of steps A is: obtain the memory parameter order,
And, the described addressable memory of step B unit is carried out corresponding operation to storer and comprised: the addressable memory unit is according to the storage address information of memory parameter in storer of self preserving, from storer, read memory parameter, this memory parameter is returned to limited processor.
3, the method for claim 1 is characterized in that, the described memory access command of steps A is: read command,
And, the rapid described addressable memory of B unit is carried out corresponding operation to storer and comprised: the addressable memory unit is according to the address information of carrying in this read command, reading of data in the space corresponding with described address information returns to limited processor with these data then from storer.
4, the method for claim 1 is characterized in that, the described memory access command of steps A is: write order,
And the rapid described addressable memory of B unit is carried out corresponding operation to storer and comprised: the addressable memory unit is written to described data in the space corresponding with described address information in the storer according to address information of carrying in this write order and data.
5, the method for claim 1 is characterized in that, the form of the described memory access command of steps A is: command id field, order length information field, address information field and data field,
And the described addressable memory of step B unit determines that according to the form of the memory access command that limited processor is sent the type of this memory access command is: the content of the command id field that the addressable memory unit hits according to this memory access is determined the type of this memory access command.
6, the method for claim 1 is characterized in that, further comprises after the described step B: the addressable memory unit returns the memory access response to limited processor.
7, method as claimed in claim 6 is characterized in that, the form of described memory access response comprises: visit successfully or fail identification field, response length information field and data field further comprise: the command sequence number field.
8, the method for claim 1 is characterized in that, described addressable memory unit is field programmable logic array (FPLA) FPGA unit or application-specific integrated circuit ASIC unit.
9, a kind of system of limited processor reference-to storage is characterized in that, this system comprises: limited processor, addressable memory unit and storer, wherein:
Limited processor is used for the form with addressable memory unit agreement various types of memory visit order, when determining to want reference-to storage, to addressable memory unit transmission memory access command;
The addressable memory unit, the form of the memory access command of sending according to limited processor is determined the type of this memory access command, according to this memory access command, storer is carried out corresponding operating;
Storer according to the operation of addressable memory unit, provides data or receives the data that the addressable memory unit writes to the addressable memory unit.
10, a kind of addressable memory unit is characterized in that this unit comprises: memory access command receiver module and memory access response sending module, wherein:
The memory access command receiver module, be used for form with limited processor agreement various types of memory visit order, determine the type of the memory access command that limited processor is sent according to described form, storer is carried out corresponding operating according to this memory access command;
Memory access response sending module is used for the form with limited processor agreement various types of memory access response, and the operation of storer is finished, and operating result is carried in the described memory access response sends to limited processor.
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| CN116757260A (en) * | 2023-08-14 | 2023-09-15 | 北京向量栈科技有限公司 | Training method and system for large pre-training model |
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| JP2001154910A (en) * | 1999-11-29 | 2001-06-08 | Mitsubishi Electric Corp | Memory access system |
| KR100441608B1 (en) * | 2002-05-31 | 2004-07-23 | 삼성전자주식회사 | NAND flash memory interface device |
| JP2004258711A (en) * | 2003-02-24 | 2004-09-16 | Matsushita Electric Ind Co Ltd | Information processor and related assembler device |
| JP3835764B2 (en) * | 2005-03-16 | 2006-10-18 | 松下電器産業株式会社 | Processor and recording medium |
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| CN116757260A (en) * | 2023-08-14 | 2023-09-15 | 北京向量栈科技有限公司 | Training method and system for large pre-training model |
| CN116757260B (en) * | 2023-08-14 | 2024-03-19 | 北京向量栈科技有限公司 | Training method and system for large pre-training model |
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Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee after: Xinhua three Technology Co., Ltd. Address before: 310053 Hangzhou hi tech Industrial Development Zone, Zhejiang province science and Technology Industrial Park, No. 310 and No. six road, HUAWEI, Hangzhou production base Patentee before: Huasan Communication Technology Co., Ltd. |
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