CN1851579A - Efficiency execution method for load adjusting device - Google Patents
Efficiency execution method for load adjusting device Download PDFInfo
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- CN1851579A CN1851579A CNA2005100669473A CN200510066947A CN1851579A CN 1851579 A CN1851579 A CN 1851579A CN A2005100669473 A CNA2005100669473 A CN A2005100669473A CN 200510066947 A CN200510066947 A CN 200510066947A CN 1851579 A CN1851579 A CN 1851579A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present invention refers to method for adjusting load device executing efficiency, it contains one detecting device picking up actual load correspondent load signal, comparing said load signal with predetermined super-frequently critical value or lower frequently critical value, and then according to compared result to control load device time-pulse signal and operating voltage input, for adjusting load device dynamical overvoltage super-frequently or lower frequently reduction voltage executing efficiency, to make total system more stabilizing, duo the critical configuration, to make system load device capable of making correspondent regulation when being in super-frequently or lower frequently regulation. Therefore the present invention not only can exert maximal executing efficiency and reduce system energy source wastage, but also raise system dynamical overvoltage super-frequently/lower frequently reduction voltage stability.
Description
Technical field
The invention relates to a kind of system and method thereof that load device is carried out usefulness of adjusting, it can make system can dynamically adjust the execution usefulness of load device under steady state (SS) according to load signal.
Background technology
As shown in Figure 1, carry out in the circuit for detecting of usefulness at the known load device, power supply unit 17 is in order to the accurate position of input high voltage () alternating current for example: 110 volts, and the accurate position of output LOW voltage () direct current for example: 12 volts, with the supply load device (for example: central processing unit 11) when running required electric power, because the voltage quasi position that central processing unit 11 consumes the required voltage quasi position (for example: 1.3 volts) of electric power to be provided than power supply unit 17 is low, so energy storage capacity by energy storage inductor 18 and storage capacitor 19, and cooperate the PWM controller 15 high gate control signal Ugate of control and hang down gate control signal Lgate, opened/closed state with difference gauge tap device 16 and derailing switch 162 makes power supply unit 17 can provide electrical power to central processing unit 11.Wherein, the electric power that derailing switch 161 drew is provided by power supply unit 17, PWM controller 15 can be adjusted the switch speed of derailing switch 161 and derailing switch 162 according to electric power that central processing unit 11 drew size, to satisfy the power consumption of central processing unit 11 under heavy duty or underload.
Because the execution usefulness of central processing unit 11 is all directly exchanged a little devices 12 via BIOS and is done setting, this adjusting gear 12 can be frequency adjuster or voltage adjuster, and then go to control the execution usefulness adjustment action that clock pulse generator 13 and 14 pairs of central processing units of voltage controller 11 carry out superpressure overclocking or frequency reducing step-down, shown in Fig. 2 a, when the known technology desire is carried out overclocking to central processing unit 11, because in order to cooperate central processing unit 11 itself to need to stablize the characteristic of overclocking, so must carry out superpressure and then overclocking to this central processing unit 11 earlier, therefore known technology often just is set at superpressure by BIOS when system begins, the demand that cooperates follow-up overclocking with this action of superpressure in advance, but because its voltage promptly is in the superpressure state behind the system boot, thereby this known way can cause unnecessary power consumption, even and if this central processing unit 11 does not carry out the action of overclocking, the not state of superpressure still can't fall back in voltage, moreover this known technology way is a single pressure overclocking pattern, so can't be under same system, system according to central processing unit 11 different times carries out demand and changes its execution usefulness, except that causing the consumption that can't reduce the energy, and the easier damage car of central processing unit 11 that causes of superpressure rises for a long time, causes the inconvenience in the use in fact.
Fig. 2 b is described to be that known technology is behind the load condition of detecting central processing unit 11; desire is carried out the usefulness adjustment action of frequency reducing to its central processing unit 11; and stablize the characteristic of frequency reducing for cooperating central processing unit 11; so necessary first frequency reducing step-down again; but known technology can be stablized execution for system before protecting not frequency reducing; therefore often in system boot; then can not do any adjustment via the BIOS setting voltage; because if after the step-down; central processing unit 11 is not frequency reducing or fixed when just carrying out frequency reducing as yet; may cause system's instability or work as machine; and can't reach the demand that keeps system stability; therefore known technology can't carry out the action of dynamic frequency reducing step-down to central processing unit 11; and if only reach the power saving purpose in the mode of frequency reducing; its effect is also limited, and then can't satisfy the demand in user's use, and causes the puzzlement in the use.
Summary of the invention
The purpose of this invention is to provide a kind of method that load device is carried out usefulness of adjusting, be according to actual loading a corresponding load signal and dynamically adjust the execution usefulness of load device,
The present invention is a kind of to adjust the method that load device is carried out usefulness, be according to an actual loading corresponding load signal and dynamically adjust the execution usefulness of this load device, it is characterized in that the method comprising the steps of:
(A) detect the load condition of this load device, and record this load signal according to the load condition of this load device;
(B) whether judge this load signal greater than an overclocking critical value, represent then that as setting up this load device desire carries out the action of overclocking, and execution in step (C);
(C) provide a control signal to control a voltage controller, so that this load device is boosted, and control a clock pulse generator stop supplies clock signal to this load device with this control signal;
(D) provide an overclocking to carry out signal, so that this clock pulse generator is carried out the action of overclocking to this clock pulse generator; And
(E) detect the action whether this clock pulse generator has finished overclocking, then transmit a startup clock pulse suppling signal to this clock pulse generator, to supply clock signal again to this load device as setting up.
Wherein, this load device is to comprise a central processing unit, a shows wafer, a north and south bridge wafer or a storer.
Wherein, in step (A), a PWM controller is to hold time in the high/low accurate position of adjusting a pwm signal according to the change of the load condition of this load device, and this pwm signal is to be this load signal.
Wherein, in step (A), one PWM controller is adjusted the high/low accurate position of a pwm signal and is held time according to the change of the load condition of this load device, a snubber assembly is imported this pwm signal and exported a high gate control signal, and this high gate control signal is to be this load signal.
Wherein, in step (A), one PWM controller is to hold time in the high/low accurate position of adjusting a pwm signal according to the change of the load condition of this load device, and a snubber assembly is imported this pwm signal and exported a low gate control signal, and this low gate control signal is to be this load signal.
Wherein, in step (A), a current-sensing circuit be this load device of detecting draw electric current, and draw the load condition that electric current records this load device with what this recorded.
Wherein, in step (A), a voltage detection circuit is the operating voltage of this load device of detecting, and records the load condition of this load device with this operating voltage.
The present invention is a kind of to adjust the method that load device is carried out usefulness, be according to actual loading a corresponding load signal and dynamically adjust the execution political affairs energy of this load device, it is characterized in that it comprises step:
(A) detect the load condition of this load device, and record this load signal according to the load condition of this load device;
(B) whether judge this load signal less than a frequency reducing critical value, represent then that as setting up this load device desire carries out the action of frequency reducing, and execution in step (C);
(C) provide a control signal to be controlled to a clock pulse generator, with the stop supplies clock signal to this load device;
(D) provide a frequency reducing to carry out signal, so that this clock pulse generator is carried out the action of frequency reducing to this clock pulse generator;
(E) detect the action whether this clock pulse generator has finished frequency reducing, then transmit a startup clock pulse suppling signal to this clock pulse generator, to supply clock signal again to this load device as setting up; And
(F) provide a step-down to carry out signal, to control a voltage controller carries out step-down to this load device action.
Wherein, this load device is to comprise a central processing unit, a shows wafer, a north and south bridge wafer or a storer.
Wherein, in step (A), a PWM controller is to hold time in the high/low accurate position of adjusting a pwm signal according to the change of the load condition of this load device, and this pwm signal is to be this load signal.
Wherein, in step (A), one PWM controller is to hold time in the high/low accurate position of adjusting a pwm signal according to the change of the load condition of this load device, and a snubber assembly is imported this pwm signal and exported a high gate control signal, and this high gate control signal is to be this load signal.
Wherein, in step (A), one PWM controller is to hold time in the high/low accurate position of adjusting a pwm signal according to the change of the load condition of this load device, and a snubber assembly is imported this pwm signal and exported a low gate control signal, and this low gate control signal is to be this load signal.
Wherein, in step (A), a current-sensing circuit be this load device of detecting draw electric current, and draw the load condition that electric current records this load device with what this recorded.
Wherein, in step (A), a voltage detection circuit is the operating voltage of this load device of detecting, and records the load condition of this load device with this operating voltage.
Description of drawings
For further specifying concrete technology contents of the present invention, below in conjunction with embodiment and accompanying drawing describes in detail as after, wherein:
Fig. 1 is the system block diagrams of known technology.
Fig. 2 a, Fig. 2 b are the view of known technology.
Fig. 3 is the process flow diagram of the present invention's first preferred embodiment.
Fig. 4 is the view of the present invention's first preferred embodiment.
Fig. 5 is the system block diagrams of the present invention's first preferred embodiment.
Fig. 6 is the functional block diagram of current loading arrangement for detecting of the present invention.
Fig. 7 is the synoptic diagram of load quantized value of the present invention, critical value, operating voltage and anti-magnetic hysteresis value.
Fig. 8 is system's block schematic diagram of the present invention's second preferred embodiment.
Fig. 9 is system's block schematic diagram of the present invention's the 3rd preferred embodiment.
Figure 10 is system's block schematic diagram of the present invention's the 4th preferred embodiment.
Figure 11 is system's block schematic diagram of the present invention's the 5th preferred embodiment.
Embodiment
Relevant adjustment load device of the present invention is carried out first preferred embodiment of the method for usefulness, please be earlier with reference to system block diagrams shown in Figure 3, it is to be used for arranging in pairs or groups method use of the present invention, as shown in Figure 3, current loading arrangement for detecting 32 can be according to load signal, as: the PWM working period signal, high gate control signal Ugate, or load device is adjusted in the variation of low gate control signal Lgate, and (for example: usefulness central processing unit 311) is carried out, present embodiment is to be example with the PWM working period signal, 35 meetings of PWM controller are according to the change of the load condition of central processing unit 311, and export a PWM working period signal to current loading arrangement for detecting 32, in present embodiment, this PWM working period signal is by the change of PWM controller 35 according to the load condition of central processing unit 311, get and adjust high/low accurate the institute that holds time of pwm signal, moreover current loading arrangement for detecting 32 can be according to the variation of PWM working period signal, and then the running of adjustment clock pulse generator 33 and voltage controller 34, it can be used to increase or reduce the clock signal and the operating voltage of central processing unit 311.In addition, in order to strengthen the driving force of high gate control signal Ugate and low gate control signal Lgate, the user also can add snubber assembly 38 in the rear end of the PWM controller 35 in the power supply unit 37, wherein, snubber assembly 38 can be the combination of forward device, reverser, impact damper or said elements.
As shown in Figure 4, current loading arrangement for detecting 32 is made up of accurate position sampler 321, frequency generator 322, timer 323, counter 324, working storage 325 and comparer 326.Frequency generator 322 is to be used for producing a high-frequency signal, for example: and the high-frequency signal of 100KHz, and the output high-frequency signal is to timer 323.Accurate position sampler 321 can be used to the PWM working period signal is taken a sample, and the output sampled signal is to counter 324.Timer 323 is due to the number of times of unit interval inside counting high-frequency signal, for example: count 100 high-frequency signals, and the output unit time signal is to counter 324.Counter 324 can be in order to the number of times of accumulative total sampled signal, and in the time of recruiting unit's time signal, the output cumulative signal is to comparer 326.When comparer 326 receives the cumulative signal that counter 324 transmits, then this cumulative signal and the critical value that is stored in the working storage 325 can be compared, in present embodiment, working storage 325 stores an overclocking critical value and a frequency reducing critical value, and this overclocking critical value territory frequency reducing critical value is removed in this example can be stored in working storage 325, it also can be stored in SRAM, in the storage devices such as storer, wherein, the corresponding usefulness of overclocking critical value is greater than the corresponding usefulness of frequency reducing critical value, and control 34 runnings of clock pulse generator 33 and voltage controller according to comparison result (overclocking or frequency reducing), to reach the execution usefulness of dynamic adjustment central processing unit 311.
Relevant implementation method of the present invention, please refer to process flow diagram shown in Figure 5 also in the lump with reference to system block diagrams shown in Figure 3, at first, in step S501, PWM controller 35 can be detected the load condition of central processing unit 311, and export the PWM working period signal to current loading arrangement for detecting 32 according to the load condition of central processing unit 311, the load condition synoptic diagram please refer to shown in Figure 6,32 of current loading arrangement for detecting can judge that whether the PWM working period signal is greater than overclocking critical value A1 at this moment, A2 or frequency reducing critical value B1, B2 (step S502), the determination methods of overclocking and frequency reducing is as described below in present embodiment, the execution usefulness of central processing unit 311 is distinguished into plural usefulness class, and sets each pairing frequency of operation of usefulness class, operating voltage, critical value and anti-magnetic hysteresis value.As shown in Figure 7, the execution usefulness that is preferably central processing unit 311 is distinguished into five usefulness classes, be respectively EHP I rank, high-effect II rank, normal usefulness III rank (preset value), low usefulness IV rank, and ultralow usefulness V rank, and its frequency of operation is respectively predeterminated frequency and promotes 10%, predeterminated frequency promotes 6%, predeterminated frequency, predeterminated frequency reduces by 6%, and predeterminated frequency reduces by 10%, operating voltage is respectively 1.4v, 1.35v, 1.3v, 1.25v and 1.20v, critical value is preferable to be respectively 45,35,25 and 15, anti-magnetic hysteresis value is preferable to be respectively 47,37,23 and 18.By in above-mentioned as can be known, if the frequency of operation promotee, then its anti-magnetic hysteresis value will be greater than critical value; On the contrary, if the frequency of operation person of being lowered, then its anti-magnetic hysteresis value will be less than critical value, this is to change because the frequency of operation of central processing unit 311 changes the execution usefulness that will cause central processing unit 311, and this change of carrying out usefulness listens the load of generation and central processing unit 311 to have nothing to do because of the load that calculation process (for example: carry out large-scale application program) is produced, for the switching of the execution usefulness that makes central processing unit 311 places on the identical comparison basis, so need to make the switching of the execution usefulness of central processing unit 311 more meet realistic state with of the comparison of anti-magnetic hysteresis value to be correlated with.Well imagine ground, the usefulness class number that the user can will carry out usefulness according to its demand is increased or is reduced, or changes the value of critical value and anti-magnetic hysteresis value, or changes each the pairing frequency of operation of usefulness class or operating voltage, does not exceed with above-mentioned.
Please in the lump with reference to overclocking and frequency reducing related elements view shown in Figure 6, the critical value of in present embodiment, operating as overclocking with critical value A1, its critical value A2 judgment mode is identical with critical value A1, then do not add to describe at this, for example the load condition of overclocking critical value A1 is 35%, then when the load condition degree of central processing unit 311 surpasses 35%, represent that then central processing unit 311 need carry out the superpressure overclocking and carry out usefulness to adjust, then 32 of current loading arrangement for detecting can be exported a control signal and control voltage controller 34, central processing unit 311 is boosted, and with this control signal control clock pulse generator 33 stop supplies clock signals to central processing unit 311 (step S503), because of the frequency of clock signal if be in make under the situation of change reach the frequency of overclocking the time, cause the machine of working as of other each element easily, therefore waiting for that clock pulse generator 33 is in the time that the target frequency of desiring overclocking rises, must give central processing unit 311 or other related elements by first stop supplies clock signal, and provide an overclocking to carry out signal to clock pulse generator 33, to allow clock pulse generator 33 that the frequency of clock signal is transferred to the target frequency (step S504) of desiring overclocking, and lasting detecting decides not arrived overclocking desired value (step S505) in the jail frequently, when the clock signal frequency of clock pulse generator 33 has reached the target frequency of overclocking, then transmit one start the clock pulse suppling signal to clock pulse generator 33 to supply clock signal again to central processing unit 311 (step S506), so just finish the action (step S512) of central processing unit 311 overclockings.
Moreover, in step S502, the critical value of in present embodiment, operating as frequency reducing with critical value B2, its critical value B1 judgment mode is identical with critical value B2, then do not add to describe at this, when and for example the load condition of central processing unit 311 is lower than frequency reducing critical value B2, for example critical value B2 is 18% o'clock, represent that then central theorem device 311 must carry out the execution usefulness adjustment of frequency reducing step-down, this moment is for preventing central processing unit 311 as if continue to receive the clock signal that clock pulse generator 33 is exported during frequency reducing, easily cause situation to produce when machine, then current loading arrangement for detecting 33 can provide one to control signal to clock pulse generator 33, to control clock pulse generator 33 stop supplies clock signals to central processing unit 311 (step S507), current loading arrangement for detecting 32 can provide a frequency reducing to carry out signal to clock pulse generator 33 more then, carry out the action (step S508) that the clock signal frequency descends with control clock pulse generator 33, whether and it is modulated to frequency reducing desired value (step S509) to continue the detecting frequency, and when the clock signal frequency of clock pulse generator 33 has reached the desired value of frequency reducing frequency, then current loading arrangement for detecting 32 can transmit a startup clock pulse suppling signal to clock pulse generator 33, to supply clock signal again to central processing unit 311 (step S510), when central processing unit 311 receives clock signal again, then current loading arrangement for detecting 32 can then provide a step-down to carry out signal and control the action (step S511) that 34 pairs of central processing units of voltage controller 311 carry out step-down, the execution usefulness of so just finishing central processing unit 311 step-downs/frequency reducing is adjusted (step, rapid S512).
Current loading arrangement for detecting 32 is except that being received the PWM working period signal by PWM controller 35, as shown in Figure 8, more can be earlier importing the high/low accurate position that PWM controller 35 adjusts according to the change of the load condition of central processing unit 311 by a snubber assembly 38 holds time, and this snubber assembly 38 receives behind the pwm signal and exports a high gate control signal Ugate, then current loading arrangement for detecting 32 also this high gate control signal Ugate of fechtable be the PWM working period signal, this embodiment only signal acquisition point is different with the foregoing description, its mode of operation is same as the previously described embodiments, so no longer describe in detail.And for example shown in Figure 9, after snubber assembly 38 receives pwm signal, also exportable one low gate control signal Lgate, and current loading arrangement for detecting 32 also this low gate control signal Lgate of fechtable is a PWM work accent phase signal, this mode of operation of this embodiment is not then added to describe at this with to reach effect all same as the previously described embodiments.
Moreover, the load condition of central processing unit 311 is except being recorded by pwm signal, as shown in figure 10, the load condition of central processing unit 311 also can be detected the electric current that draws of central processing unit 311 by current-sensing circuit 91, and draw electric current and learn the load condition of central processing unit 311 with measured, and and then adjust the execution usefulness of central processing unit 311, this mode of operation of this embodiment is not then added to describe at this with to reach effect all same as the previously described embodiments.And for example shown in Figure 11, the load condition of central processing unit 311 also can be detected the operating voltage of central processing unit 311 by voltage detection circuit 92, and learn the load condition of central processing unit 311 with this operating voltage, and and then adjust the execution usefulness of central processing unit 311, this mode of operation of this embodiment is not then added to describe at this with to reach effect all same as the previously described embodiments.
As mentioned above, the present invention utilizes load signal to detect to make load device can stably carry out the execution usefulness adjustment of dynamic overpressure overclocking or frequency reducing step-down, and reach the purpose that usefulness is carried out in dynamic adjustment with the setting of overclocking and frequency reducing critical value, make system when carrying out overclocking or frequency reducing adjustment, load device all has and carries out corresponding adjustment, remove the execution usefulness that makes load device can bring into play maximum, more can reduce the consume of the energy.
The foregoing description only is to give an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (14)
1. adjust the method that load device is carried out usefulness for one kind, be according to an actual loading corresponding load signal and dynamically adjust the execution usefulness of this load device, it is characterized in that the method comprising the steps of:
(A) detect the load condition of this load device, and record this load signal according to the load condition of this load device;
(B) whether judge this load signal greater than an overclocking critical value, represent then that as setting up this load device desire carries out the action of overclocking, and execution in step (C);
(C) provide a control signal to control a voltage controller, so that this load device is boosted, and control a clock pulse generator stop supplies clock signal to this load device with this control signal;
(D) provide an overclocking to carry out signal, so that this clock pulse generator is carried out the action of overclocking to this clock pulse generator; And
(E) whether oneself finishes the action of overclocking to detect this clock pulse generator, then transmits a startup clock pulse suppling signal to this clock pulse generator, to supply clock signal again to this load device as setting up.
2. adjustment load device as claimed in claim 1 is carried out the method for usefulness, it is characterized in that wherein, this load device is to comprise a central processing unit, a shows wafer, a north and south bridge wafer or a storer.
3. adjustment load device as claimed in claim 1 is carried out the method for usefulness, it is characterized in that, wherein, in step (A), one PWM controller is to hold time in the high/low accurate position of adjusting a pwm signal according to the change of the load condition of this load device, and this pwm signal is to be this load signal.
4. adjustment load device as claimed in claim 1 is carried out the method for usefulness, it is characterized in that, wherein, in step (A), one PWM controller is adjusted the high/low accurate position of a pwm signal and is held time according to the change of the load condition of this load device, one snubber assembly is imported this pwm signal and is exported a high gate control signal, and this high gate control signal is to be this load signal.
5. adjustment load device as claimed in claim 1 is carried out the method for usefulness, it is characterized in that, wherein, in step (A), one PWM controller is to hold time in the high/low accurate position of adjusting a pwm signal according to the change of the load condition of this load device, one snubber assembly is imported this pwm signal and is exported a low gate control signal, and this low gate control signal is to be this load signal.
6. adjustment load device as claimed in claim 1 is carried out the method for usefulness, it is characterized in that, wherein, in step (A), one current-sensing circuit be this load device of detecting draw electric current, and draw the load condition that electric current records this load device with what this recorded.
7. adjustment load device as claimed in claim 1 is carried out the method for usefulness, it is characterized in that, wherein, in step (A), a voltage detection circuit is the operating voltage of this load device of detecting, and records the load condition of this load device with this operating voltage.
8. adjust the method that load device is carried out usefulness for one kind, be according to actual loading a corresponding load signal and dynamically adjust the execution political affairs energy of this load device, it is characterized in that it comprises step:
(A) detect the load condition of this load device, and record this load signal according to the load condition of this load device;
(B) whether judge this load signal less than a frequency reducing critical value, represent then that as setting up this load device desire carries out the action of frequency reducing, and execution in step (C);
(C) provide a control signal to be controlled to a clock pulse generator, with the stop supplies clock signal to this load device;
(D) provide a frequency reducing to carry out signal, so that this clock pulse generator is carried out the action of frequency reducing to this clock pulse generator;
(E) detect the action whether this clock pulse generator has finished frequency reducing, then transmit a startup clock pulse suppling signal to this clock pulse generator, to supply clock signal again to this load device as setting up; And
(F) provide a step-down to carry out signal, to control a voltage controller carries out step-down to this load device action.
9. adjustment load device as claimed in claim 8 is carried out the method for usefulness, it is characterized in that wherein, this load device is to comprise a central processing unit, a shows wafer, a north and south bridge wafer or a storer.
10. adjustment load device as claimed in claim 8 is carried out the method for usefulness, it is characterized in that, wherein, in step (A), one PWM controller is to hold time in the high/low accurate position of adjusting a pwm signal according to the change of the load condition of this load device, and this pwm signal is to be this load signal.
11. adjustment load device as claimed in claim 8 is carried out the method for usefulness, it is characterized in that, wherein, in step (A), one PWM controller is to hold time in the high/low accurate position of adjusting a pwm signal according to the change of the load condition of this load device, one snubber assembly is imported this pwm signal and is exported a high gate control signal, and this high gate control signal is to be this load signal.
12. adjustment load device as claimed in claim 8 is carried out the method for usefulness, it is characterized in that, wherein, in step (A), one PWM controller is to hold time in the high/low accurate position of adjusting a pwm signal according to the change of the load condition of this load device, one snubber assembly is imported this pwm signal and is exported a low gate control signal, and this low gate control signal is to be this load signal.
13. adjustment load device as claimed in claim 8 is carried out the method for usefulness, it is characterized in that, wherein, in step (A), one current-sensing circuit be this load device of detecting draw electric current, and draw the load condition that electric current records this load device with what this recorded.
14. adjustment load device as claimed in claim 8 is carried out the method for usefulness, it is characterized in that, wherein, in step (A), a voltage detection circuit is the operating voltage of this load device of detecting, and records the load condition of this load device with this operating voltage.
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| CNB2005100669473A CN100426196C (en) | 2005-04-22 | 2005-04-22 | Efficiency execution method for load adjusting device |
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| CNB2005100669473A CN100426196C (en) | 2005-04-22 | 2005-04-22 | Efficiency execution method for load adjusting device |
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| CN101876845B (en) * | 2009-04-30 | 2012-05-23 | 华硕电脑股份有限公司 | Control method and overclocking control method of central processing unit |
| CN102549523A (en) * | 2009-09-24 | 2012-07-04 | 高通股份有限公司 | Apparatus and methods for optimizing power consumption in a wireless device |
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| US8296597B2 (en) | 2008-08-22 | 2012-10-23 | Asustek Computer Inc. | Computer system capable of dynamically modulating operation voltage and frequency of CPU |
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| CN103597689A (en) * | 2011-04-08 | 2014-02-19 | 艾思玛太阳能技术股份公司 | Optimized load management |
| CN105353863A (en) * | 2015-09-25 | 2016-02-24 | 联想(北京)有限公司 | Control method and system and electronic device |
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| CN114115500A (en) * | 2021-10-09 | 2022-03-01 | 北京比特大陆科技有限公司 | Working voltage processing method and device, electronic equipment and storage medium |
| CN114281180A (en) * | 2021-12-21 | 2022-04-05 | 海光信息技术股份有限公司 | Integrated circuit load adjusting method and related device |
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| DE69022555T2 (en) * | 1989-04-06 | 1996-05-30 | Fuji Electric Co Ltd | DEVICE FOR DETECTING THE DISCONNECTION OF A DISTRIBUTED POWER SUPPLY SYSTEM. |
| CN1130000C (en) * | 1999-01-22 | 2003-12-03 | 松下电器产业株式会社 | Switching power supply |
| US6433525B2 (en) * | 2000-05-03 | 2002-08-13 | Intersil Americas Inc. | Dc to DC converter method and circuitry |
| TW535050B (en) * | 2001-01-02 | 2003-06-01 | Winbond Electronics Corp | Adjustment method and apparatus of execution efficiency for electronic device |
| US6643128B2 (en) * | 2001-07-13 | 2003-11-04 | Hewlett-Packard Development Company, Lp. | Method and system for controlling a cooling fan within a computer system |
| JP3673245B2 (en) * | 2002-06-28 | 2005-07-20 | 株式会社東芝 | Information processing apparatus and power control method for the same |
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| US8296597B2 (en) | 2008-08-22 | 2012-10-23 | Asustek Computer Inc. | Computer system capable of dynamically modulating operation voltage and frequency of CPU |
| US8296596B2 (en) | 2008-08-22 | 2012-10-23 | Asustek Computer Inc. | Computer system capable of dynamically modulating core-voltage and clock frequency of CPU |
| CN101876845B (en) * | 2009-04-30 | 2012-05-23 | 华硕电脑股份有限公司 | Control method and overclocking control method of central processing unit |
| US8448011B2 (en) | 2009-07-27 | 2013-05-21 | Asustek Computer Inc. | Increasing processor operating frequency when monitored loading level pattern of program matches recorded pattern of target program |
| CN102549523A (en) * | 2009-09-24 | 2012-07-04 | 高通股份有限公司 | Apparatus and methods for optimizing power consumption in a wireless device |
| CN102549523B (en) * | 2009-09-24 | 2016-01-20 | 高通股份有限公司 | For optimizing the apparatus and method of the power consumption of wireless device |
| US9195296B2 (en) | 2009-09-24 | 2015-11-24 | Qualcomm Incorporated | Apparatus and methods for optimizing power consumption in a wireless device |
| CN102570399B (en) * | 2010-12-14 | 2014-08-20 | 华硕科技（苏州）有限公司 | Power supply circuit as well as circuit board and electronic device adopting same |
| CN102570399A (en) * | 2010-12-14 | 2012-07-11 | 华硕科技（苏州）有限公司 | Power supply circuit as well as circuit board and electronic device adopting same |
| CN103597689A (en) * | 2011-04-08 | 2014-02-19 | 艾思玛太阳能技术股份公司 | Optimized load management |
| CN103597689B (en) * | 2011-04-08 | 2016-08-17 | 艾思玛太阳能技术股份公司 | The load management optimized |
| CN103544062A (en) * | 2012-07-12 | 2014-01-29 | 华为技术有限公司 | Processing method and device of processor |
| CN103544062B (en) * | 2012-07-12 | 2017-11-28 | 华为技术有限公司 | The treating method and apparatus of processor |
| CN105353863A (en) * | 2015-09-25 | 2016-02-24 | 联想(北京)有限公司 | Control method and system and electronic device |
| CN105353863B (en) * | 2015-09-25 | 2018-03-27 | 联想(北京)有限公司 | Control method, system and electronic equipment |
| CN110758051A (en) * | 2019-10-31 | 2020-02-07 | 广东美的制冷设备有限公司 | Power supply method, power supply device, vehicle-mounted air conditioner and computer-readable storage medium |
| CN114115500A (en) * | 2021-10-09 | 2022-03-01 | 北京比特大陆科技有限公司 | Working voltage processing method and device, electronic equipment and storage medium |
| CN114281180A (en) * | 2021-12-21 | 2022-04-05 | 海光信息技术股份有限公司 | Integrated circuit load adjusting method and related device |
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