CN1838315A - Graded temperature compensation refreshing method and circuit thereof - Google Patents
Graded temperature compensation refreshing method and circuit thereof Download PDFInfo
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- CN1838315A CN1838315A CN200610076279.7A CN200610076279A CN1838315A CN 1838315 A CN1838315 A CN 1838315A CN 200610076279 A CN200610076279 A CN 200610076279A CN 1838315 A CN1838315 A CN 1838315A
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Abstract
This invention relates to a graded temperature compensation refreshing method and circuit thereof. Wherein, producing a reference voltage free to temperature by a band-gap reference voltage source and a working voltage with inverse proportion to temperature by a parasitic triode; comparing by a staged controller the two former voltages to product the selection information for every stage temperature control; according to the selection signal, producing different-frequency refresh clock by a controllable clock generator. This invention controls refresh frequency, and has no dc loop when on lock condition to reduce power consumption greatly.
Description
Technical field
The invention belongs to MOS transistor integrated circuit (IC) design technical field, particularly storage unit is compensated the circuit design that refreshes.
Background technology
The dynamic storage that uses CMOS technology to make, utilize electric capacity as the cell stores electric charge to reach the function of canned data.Owing to the electric capacity stored charge can be lost because of electric leakage, correct in order to guarantee canned data, need compensate storage unit and refresh.The speed of storage unit electric leakage has determined the frequency that storer need refresh.Electric leakage speed is big more, and required refreshing frequency is high more.
The leakage current of storage unit and temperature exponent function relation: (Eg/kT), Is is a leakage current to Is=Io EXP in the formula; Io is the constant relevant with semiconductor material; Eg is being with of silicon; K is a Boltzmann constant; T is a temperature.Therefore temperature is high more, and leakage current is just big more, and required refreshing frequency is just high more.
At present, general storage unit adopts the temperature compensated self refresh circuit, and it is formed structure and adopts responsive to temperature oscillator and control circuit to form current source, and pierce circuit produces the frequency that control refreshes pierce circuit.The output signal clock period of responsive to temperature pierce circuit increases along with the rising of temperature.The output signal control control circuit of responsive to temperature pierce circuit, this control circuit is the current source that refreshes pierce circuit and source node.The responsive oscillator of this circuit temperature has DC loop, and power consumption is higher.
Another kind of not temperature compensated whole refresh circuit, the whole refreshing frequency of storage unit will remain on the higher level, to guarantee that device at high temperature can operate as normal.And when the device working temperature was low, same refreshing frequency then caused the waste of energy.
Summary of the invention
The objective of the invention is to propose a kind of graded temperature compensation refreshing method and circuit thereof for overcoming the weak point of prior art, can produce the refresh clock of different frequency under different temperatures, control refreshes clock frequency; Be at circuit and latch holding state, no DC loop can reduce power consumption greatly.
A kind of graded temperature compensation refreshing method that the present invention proposes is characterized in that this method may further comprise the steps:
1) produces a temperature independent reference voltage;
2) produce the operating voltage that is inversely proportional to temperature;
3) reference voltage and operating voltage are compared, produce the selection information of each grade control of temperature at different levels;
4) basis and the different refresh clock of the corresponding selection signal of temperature generated frequency.
A kind of graded temperature compensation refreshing circuit that the present invention proposes is characterized in that, comprising:
One band-gap voltage reference is used to produce temperature independent reference voltage;
One parasitic triode is used to produce the operating voltage that is inversely proportional to temperature;
One sorter controller is used for reference voltage and operating voltage are compared, and produces the analog-to-digital selection signal of each grade control of temperature at different levels;
One controlled clock generator is used for basis and the different refresh clock of the corresponding selection signal of temperature generated frequency.
Technical characterstic of the present invention and effect:
The present invention utilizes band-gap voltage reference to produce temperature independent reference voltage, and the parasitic triode that forms with CMOS technology produces the operating voltage that is inversely proportional to temperature.Utilize amplifier that reference voltage and operating voltage are compared, produce the analog to digital conversion from the temperature to the step control.Select signal controlling compensation refresh clock generator with the corresponding numeral of temperature, thereby realize graded temperature compensation refreshing.
The present invention can produce the refresh clock of different frequency under different temperatures, control refreshes clock frequency;
This circuit itself has idle function simultaneously, and under standby mode (beginning, energy control signal en was 0 o'clock), circuit is in and latchs holding state, and no DC loop greatly reduces power consumption.
Description of drawings
Fig. 1 is level Four temperature compensation refreshing circuit embodiments theory of constitution figure of the present invention.
Fig. 2 is the specific implementation synoptic diagram of the level Four temperature compensation refreshing circuit of present embodiment.
Embodiment
The graded temperature compensation refreshing circuit that the present invention proposes reaches embodiment in conjunction with the accompanying drawings and is described in detail as follows:
A kind of graded temperature compensation refreshing method that the present invention proposes is characterized in that this method may further comprise the steps:
1) produces a temperature independent reference voltage;
2) produce the operating voltage that is inversely proportional to temperature;
3) reference voltage and operating voltage are compared, produce the selection information of each grade control of temperature at different levels;
4) basis and the different refresh clock of the corresponding selection signal of temperature generated frequency.
The present invention realizes that the circuit of said method comprises:
One band-gap voltage reference is used to produce temperature independent reference voltage;
One parasitic triode is used to produce the operating voltage that is inversely proportional to temperature;
One sorter controller is used for reference voltage and operating voltage are compared, and produces the analog-to-digital selection signal of each grade control of temperature at different levels;
One controlled clock generator is used for basis and the different refresh clock of the corresponding selection signal of temperature generated frequency.
The main composition of the realization circuit embodiments of the graded temperature compensation refreshing method that the present invention proposes, as shown in Figure 1, comprise: band-gap voltage reference 1, PMOS pipe 2, parasitic triode 3 is by operational amplifier 4, voltage comparator 5,6,7,8, register 9, the level Four controller that code translator 10 is formed, controlled clock generator 11.The annexation of each device is: the input signal VDD of circuit connects the source electrode of PMOS pipe 2, the output offset voltage end Vibias of the grid tape splicing crack reference voltage source 1 of PMOS pipe 2, the drain electrode of PMOS pipe 2 connects the emitter-base bandgap grading of parasitic triode 3 and the in-phase input end of operational amplifier 4, and the base stage of parasitic triode PNP 3 and collector are with the place of working voltage VSS of connection circuit.The reference voltage end VT0 that band-gap voltage reference 1 produces, VT1, VT2, VT3 connects the input end of voltage comparator 5,6,7,8 respectively, the output terminal of voltage comparator 5,6,7,8 inserts the input end of register 9, the input end of the output termination code translator 10 of register 9, the input end of the controlled clock generator 11 of output termination of code translator 10, produce refresh clock by controlled clock 11, the refresh clock of control dynamic storage unit.Beginning can signal en beginning of connecing operational amplifier 4, voltage comparator 5,6,7,8 and register 9 respectively can hold.
The input signal of circuit of the present invention has VDD, VSS, and en.Wherein VDD is the working power voltage of circuit, and VSS is the place of working voltage of circuit, and en is an enable signal.The output signal of circuit is a refresh clock.
The principle of work of foregoing circuit is:
Among Fig. 1, band-gap circuit 1 produces temperature-independent reference voltage VT0, VT1, VT2, VT3 and pmos bias voltage Vibias.
Bias voltage VBIAS control PMOS2 produces bias current control parasitic triode PNP 3.
Triode PNP 3 produces the VD that varies with temperature and change.
VD produces operating voltage VT by operational amplifier 4.Because operational amplifier 4 unit's of being configured to amplifiers cause VT to equate with VD.Therefore, VT is inversely proportional to temperature and changes.
As VT during greater than VT0, voltage comparator 5 output comp0 are " 1 "; Otherwise be " 0 ".
As VT during greater than VT1, voltage comparator 6 output comp1 are " 1 "; Otherwise be " 0 ".
As VT during greater than VT2, voltage comparator 7 output comp2 are " 1 "; Otherwise be " 0 ".
As VT during greater than VT3, voltage comparator 8 output comp3 are " 1 "; Otherwise be " 0 ".
So from high to low, comp[3:0 with temperature] be output as: 0000,0001,0011,0111,1111.
All voltage comparators are all controlled by en.Work is awaited orders when " 0 " and is blocked all DC channel to reduce power consumption when equaling " 1 " at en.
Comp[3:0] signal storage is in 4 bit registers 9.Register 9 storages were upgraded when en equals " 0 " when en equaled " 1 ".It exports D[3:0] with comp[3:0] corresponding one by one.
Controlled clock generator 11 is an output signal of the present invention according to selecting the different refresh clock of signal generated frequency.
Above-mentioned level Four temperature specific implementation as shown in Figure 2, among the figure, horizontal ordinate is represented T, ordinate is represented voltage V, when the beginning can signal en when being high, the voltage VT0 that operating voltage VT is changed with varying with temperature, VT1, VT2 and VT3 compare, and produce the analog to digital conversion from the temperature to the step control.Select signal controlling compensation refresh clock generator with the corresponding numeral of temperature, thereby realize graded temperature compensation refreshing.
When temperature 0＜T＜T0, VT＞VT0, VT1, VT2, VT3, voltage comparator 5,6,7,8 export " 1 ", " 1 ", " 1 ", " 1 ", this signal comp[3:0 successively]-(1111) can signal en be stored in the register 9 when being high in the beginning.It exports D[3:0] with comp[3:0] corresponding one by one, code translator input (1111) produces and selects signal S＜4:0 〉=(00001), the different clock of frequency of selecting controlled clock generator 11 to produce, this output clock are that refresh clock is controlled the DRAM unit.
When temperature T 0＜T＜T1, VT1, VT2, VT3＜VT＜VT0, voltage comparator 5,6,7,8 export " 0 ", " 1 ", " 1 ", " 1 ", this signal comp[3:0 successively]-(0111) can signal en be stored in the register 9 when being high in the beginning.It exports D[3:0] with comp[3:0] corresponding one by one, code translator input (0111) produces and selects signal S＜4:0 〉=(00010), the different clock of frequency of selecting controlled clock generator 11 to produce, this output clock are that refresh clock is controlled the DRAM unit.
When temperature T 1＜T＜T2, VT2, VT3＜VT＜VT0, VT1,, voltage comparator 5,6,7,8 is exported " 0 ", " 0 ", " 1 ", " 1 ", this signal comp[3:0 successively]-(0011) can signal en be stored in the register 9 when being high in the beginning.It exports D[3:0] with comp[3:0] corresponding one by one, code translator input (0011) produces and selects signal S＜4:0 〉=(00100), the different clock of frequency of selecting controlled clock generator 11 to produce, this output clock are that refresh clock is controlled the DRAM unit.
When temperature T 2＜T＜T3, VT3＜VT＜VT0, VT1, VT2, voltage comparator 5,6,7,8 export " 0 ", " 0 ", " 0 ", " 1 ", this signal comp[3:0 successively]-(0001) can signal en be stored in the register 9 when being high in the beginning.It exports D[3:0] with comp[3:0] corresponding one by one, code translator input (0001) produces and selects signal S＜4:0 〉=(01000), the different clock of frequency of selecting controlled clock generator 11 to produce, this output clock are that refresh clock is controlled the DRAM unit.
When temperature T＞T3, VT＞VT0, VT1, VT2, VT3 voltage comparator 5,6,7,8 export " 0 ", " 0 ", " 0 ", " 0 ", this signal comp[3:0 successively]-(0000) can signal en be stored in the register 9 when being high in the beginning.It exports D[3:0] with comp[3:0] corresponding one by one, code translator input (0000) produces and selects signal S＜4:0 〉=(10000), the different clock of frequency of selecting controlled clock generator 11 to produce, this output clock are that refresh clock is controlled the DRAM unit.
Because in the circuit of the present invention, the duty that the beginning can signal en control circuit, as en when being high, control circuit is in the sampling work state, when en when low, circuit is in the standby latch mode, so this circuit do not have DC loop, power consumption is very low.
The universal integrated circuit device that circuit of the present invention adopts CMOS technology to realize is formed by connecting.
Claims (9)
1, a kind of graded temperature compensation refreshing method is characterized in that, this method may further comprise the steps:
1) produces a temperature independent reference voltage;
2) produce the operating voltage that is inversely proportional to temperature;
3) reference voltage and operating voltage are compared, produce the selection information of each grade control of temperature at different levels;
4) basis and the different refresh clock of the corresponding selection signal of temperature generated frequency.
2, the method for claim 1 is characterized in that, described reference voltage is produced by a band-gap voltage reference.
3, the method for claim 1 is characterized in that, described operating voltage is produced by a parasitic triode.
4, the method for claim 1 is characterized in that, described selection signal is produced by a sorter controller.
5, a kind of graded temperature compensation refreshing circuit is characterized in that, this circuit comprises:
One band-gap voltage reference is used to produce temperature independent reference voltage;
One parasitic triode is used to produce the operating voltage that is inversely proportional to temperature;
One sorter controller is used for reference voltage and operating voltage are compared, and produces the analog-to-digital selection signal of each grade control of temperature at different levels;
One controlled clock generator is used for basis and the different refresh clock of the corresponding selection signal of temperature generated frequency.
6, graded temperature compensation refreshing circuit as claimed in claim 5 is characterized in that, described sorter controller is by operational amplifier, N voltage comparator, and register and code translator are formed; The annexation of each device is: the input signal end VDD of circuit connects the source electrode of PMOS pipe, the output offset voltage end Vibias of the grid tape splicing crack reference voltage source of metal-oxide-semiconductor, the drain electrode of PMOS pipe connects the emitter-base bandgap grading of parasitic triode and the in-phase input end of operational amplifier, and the base stage of parasitic triode PNP and collector are with the place of working voltage VSS of connection circuit; The reference voltage end VT0 of band-gap voltage reference, VT1, VT2, VTN links to each other with the input end of N voltage comparator respectively, the output terminal of N voltage comparator all links to each other with the input end of register, the input end of the output termination code translator of register, the input end of the controlled clock generator of output termination of code translator, by controlled clock generating refresh clock, the refresh clock of control dynamic storage unit; Energy signal en can hold with the beginning of operational amplifier, a N voltage comparator and register respectively and link to each other beginning.
7, graded temperature compensation refreshing circuit as claimed in claim 5 is characterized in that, described metal-oxide-semiconductor is the PMOS pipe.
8, graded temperature compensation refreshing circuit as claimed in claim 5 is characterized in that, described parasitic triode is the PNP parasitic triode.
9, as claim 5,6,7 or 8 described graded temperature compensation refreshing circuit, it is characterized in that the universal integrated circuit device that described each device all adopts CMOS technology to realize.
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Cited By (6)
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| CN103426465A (en) * | 2013-08-26 | 2013-12-04 | 郑君 | Memory comparison and refresh circuit module |
| CN103544987A (en) * | 2012-07-09 | 2014-01-29 | 晶豪科技股份有限公司 | Semiconductor memory element with self-refreshing sequence circuit |
| CN103618524A (en) * | 2013-11-27 | 2014-03-05 | 中国航空工业集团公司第六三一研究所 | Circuit and method for processing general discrete magnitudes |
| CN103745743A (en) * | 2013-12-25 | 2014-04-23 | 苏州宽温电子科技有限公司 | SRAM (static random access memory) sense amplifier based on temperature compensation |
| CN103853695B (en) * | 2013-12-10 | 2016-11-02 | 中国航空工业集团公司第六三一研究所 | A kind of power-on self-test circuit of discrete magnitude |
| CN113364451A (en) * | 2021-06-28 | 2021-09-07 | 南京英锐创电子科技有限公司 | Clock frequency calibration method, system, computer device and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281760B1 (en) * | 1998-07-23 | 2001-08-28 | Texas Instruments Incorporated | On-chip temperature sensor and oscillator for reduced self-refresh current for dynamic random access memory |
| US6865136B2 (en) * | 2003-06-24 | 2005-03-08 | International Business Machines Corporation | Timing circuit and method of changing clock period |
| US20050036380A1 (en) * | 2003-08-14 | 2005-02-17 | Yuan-Mou Su | Method and system of adjusting DRAM refresh interval |
| US20050162215A1 (en) * | 2004-01-22 | 2005-07-28 | Winbond Electronics Corporation | Temperature sensing variable frequency generator |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103544987A (en) * | 2012-07-09 | 2014-01-29 | 晶豪科技股份有限公司 | Semiconductor memory element with self-refreshing sequence circuit |
| CN103426465A (en) * | 2013-08-26 | 2013-12-04 | 郑君 | Memory comparison and refresh circuit module |
| CN103426465B (en) * | 2013-08-26 | 2016-09-07 | 郑君 | Memory comparing brushes novel circuit module |
| CN103618524A (en) * | 2013-11-27 | 2014-03-05 | 中国航空工业集团公司第六三一研究所 | Circuit and method for processing general discrete magnitudes |
| CN103618524B (en) * | 2013-11-27 | 2016-02-24 | 中国航空工业集团公司第六三一研究所 | A kind for the treatment of circuit of general discrete amount and method |
| CN103853695B (en) * | 2013-12-10 | 2016-11-02 | 中国航空工业集团公司第六三一研究所 | A kind of power-on self-test circuit of discrete magnitude |
| CN103745743A (en) * | 2013-12-25 | 2014-04-23 | 苏州宽温电子科技有限公司 | SRAM (static random access memory) sense amplifier based on temperature compensation |
| CN113364451A (en) * | 2021-06-28 | 2021-09-07 | 南京英锐创电子科技有限公司 | Clock frequency calibration method, system, computer device and storage medium |
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| CN100474444C (en) | 2009-04-01 |
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Effective date of registration: 20100713 Address after: 100084 B building, Tsinghua research building, Tsinghua Science Park, Beijing, Haidian District 301 Patentee after: GIGADEVICE SEMICONDUCTOR Inc. Address before: 100084 B building, Tsinghua research building, Tsinghua Science Park, Beijing, Haidian District 301 Patentee before: GigaDevice Semiconductor Inc. |
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |
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