CN1835238A - Semiconductor device with gate insulating film and manufacturing method thereof - Google Patents
Semiconductor device with gate insulating film and manufacturing method thereof Download PDFInfo
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- CN1835238A CN1835238A CN 200610059663 CN200610059663A CN1835238A CN 1835238 A CN1835238 A CN 1835238A CN 200610059663 CN200610059663 CN 200610059663 CN 200610059663 A CN200610059663 A CN 200610059663A CN 1835238 A CN1835238 A CN 1835238A
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Abstract
A MISFET includes: a p type substrate having a channel region with an impurity concentration C; an insulating film made of SiO<SUB>2 </SUB>and formed on the channel region; and an insulating film made of HfSiON and formed on the gate insulating film. When there is a postulated MISFET including a postulated substrate having a channel region with the impurity concentration C and made of a material identical to the substrate and an insulating film made solely of SiON formed on the channel region, said impurity concentration C of channel region is set so that a maximum value of mobility of electrons in said channel region is higher than a maximum value of mobility of electrons in the postulated channel region. Thus, the power supply voltage can be reduced and the power consumption can be reduced.
Description
Technical field
The present invention relates to have the semiconductor device and the manufacture method thereof of gate insulating film, relate to semiconductor device and manufacture method thereof especially with the gate insulating film that constitutes by high dielectric constant material.
Background technology
(metal-insulator semiconductor: metal-insulator layer-semiconductor) (field-effecttransistor: field-effect transistor), former bi-directional scaling principle has realized highly integrated FET at the MIS as the basic structure circuit of large scale integrated circuit (LSI).In MISFET, use silicon dioxide (SiO as grid oxidation film always
2).But, be considered to use SiO
2The thickness of gate insulating film about 2.0nm arrive boundary.That is, will use SiO
2Gate insulating film when making than thickness thin about 2.0nm, cause the problem that power consumption increases with the increase of tunnel leakage current.In addition, cause the problem of the reliability reduction of gate insulating film.Have again, cause that the diffusion barrier at impurity dies down, the problem of omitting from the impurity of gate electrode.And, in order to produce thin SiO in batches with having good uniformity
2Film and need strict production control.
Therefore, for the microminiaturization and the high speed that further make element and deposit, break this bi-directional scaling restriction, even carrying out comparing SiO
2Form and Bao Yeneng obtains the exploitation of high-k (high-K) material of above on an equal basis field effect performance.As competitive candidate material is zirconia (ZrO
2), hafnium oxide (HfO
2) wait IV family oxide, aluminium oxide (Al
2O
3), yittrium oxide (Y
2O
3) wait III family oxide and silicate.IV family oxide and III family oxide are the materials that is used as gate insulating film at the semi-conductive initial stage of Si.But, SiO
2The formation technology of gate insulating film be established after because its excellent characteristic, and used SiO specially
2
But, make Al
2O
3Be applied to Deng high dielectric constant material have following problem points under the situation of MISFET of gate insulating film.Because will cause pinning (effect) under the gate insulating film of combination high dielectric constant material and the situation of polysilicon electrode, so the flat band voltage of the MI SFET of N channel-type is drifted about about 0.3V to positive voltage side, the threshold voltage of MISFET also changes.In addition, the mobility of electronics is little, with SiO
2The pervasive curve of film (universal curve) is compared, and is about 1/4, so source electrode, the electric current between the drain electrode when making the MISFET action can not increase like that according to expectation.One of reason that the mobility of electronics is little is considered to because the fixed charge that exists in dielectric film makes the electronics in the raceway groove that cause at random take place.
Herein, so-called pervasive curve provides the curve of generality of the effective electric field dependence of mobility of charge carrier rate, is to define to have by SiO on experience
2The peaked curve of carrier mobility among the MISFET of the dielectric film that constitutes.Pervasive curve is extensive use of in the mobility of charge carrier rate in comparing MISFET.At S.Takagi et al., " On theUniversality of Inversion Layer Mobility in Si MOSFETs:PartI-Effects of Substrate Impurity Concentration ", IEEETrans.Electron Devices. has put down in writing among the Vol.41 No.12 pp.2357-2362.1994 and has had by SiO
2The pervasive curve of the MISFET of the gate insulating film that constitutes.This pervasive curve shown in Figure 16.The face orientation that Figure 16 illustrates the first type surface of silicon substrate is the effective electric field variation of (100), the electron mobility when underlayer temperature is 77K and 300K.With reference to Figure 16, the electron mobility under certain underlayer temperature, certain substrate concentration NA has maximum under certain effective electric-field intensity.
About improving the mobility of electronics, the spy opens and discloses a kind of semiconductor device in the 2003-69011 communique, forms by Al on Si (silicon) substrate
2O
3The gate insulating film that constitutes forms silicon oxide layer or silicon nitride film on the zone of Si substrate and metal oxide clamping.Thus, can be suppressed at Al
2O
3/ Si interface forms the AlOX bonding state of metal, can suppress can reduce Al because of the AlOX bonding state produces electronics
2O
3The fixed charge of/Si substrate interface.Consequently, the mobility of electronics is brought up to and SiO among the MISFET of N channel-type
2The pervasive curve of film is compared about mobility of about 3/4.
Using under the situation of high dielectric constant material as gate insulating film, the mobility of the electronics in the channel region is lower.Therefore, the electric current that flows through between source electrode, the drain electrode reduces, and can not obtain required conducting electric current, so, need to improve supply voltage.Consequently, the problem that exists power consumption to increase.In addition, can not realize high speed motion.Even use the spy to open disclosed technology in the 2003-69011 communique, the mobility of electronics still is no more than pervasive curve, and the mobility of charge carrier rate is insufficient.
Summary of the invention
One object of the present invention is to provide a kind of semiconductor device and manufacture method thereof that reduces power consumption.
In addition, another object of the present invention provides a kind of semiconductor device and manufacture method thereof that realizes high speed motion.
Semiconductor device of the present invention comprises: the Semiconductor substrate with channel region of impurity concentration C; Comprise silicon and oxygen and be formed on the 1st gate insulating film on the described channel region; Comprise hafnium and oxygen and be formed on the 2nd gate insulating film on described the 1st gate insulating film.Imagine second half conductor means, this second half conductor means comprises: second half conductive substrate, and it has another channel region of impurity concentration C, is made of the material identical with described Semiconductor substrate; Another gate insulating film, be formed on described another channel region and only constitute by SiON (silicon oxynitride), set the impurity concentration C of described channel region, so that the maximum of electron mobility in the described channel region is become than the maximum height of the electron mobility in described another channel region.
The manufacture method of semiconductor device of the present invention comprises following steps: the channel region that forms impurity concentration C on Semiconductor substrate; On described channel region, form the 1st gate insulating film that comprises silicon and oxygen; On described the 1st gate insulating film, form the 2nd gate insulating film that comprises hafnium and oxygen.In the step that forms channel region, set impurity concentration C, so that the maximum height that makes the maximum of electron mobility in the channel region become electron mobility in the channel region when on the channel region of impurity concentration C, only forming the gate insulating film that constitutes by silicon oxynitride.
The application's inventors find, even comprise in use under the situation of high dielectric constant material as gate insulating film of hafnium and oxygen, also the impurity concentration C of the channel region in the Semiconductor substrate can be set at suitable value, thus, can improve the electron mobility in the channel region tremendously.That is, imagine second half conductor means, this second half conductor means comprises: second half conductive substrate, have another channel region of impurity concentration C, and constitute by the material identical with described Semiconductor substrate; Another gate insulating film is formed on described another channel region and only is made of SiON.In semiconductor device of the present invention and manufacture method thereof, set the impurity concentration C of described channel region, so that the maximum of the electron mobility in the described channel region is than the maximum height of electron mobility in this another channel region.Thus, can improve the mobility of electronics.
In addition, by forming the 1st gate insulating film, the 2nd gate insulating film and Semiconductor substrate can be separated.Thus, fixed charge and the channel region that exists on the 2nd gate insulating film can be separated.Consequently, can improve the mobility of electronics.
By improving the mobility of electronics, increase the electric current that flows through between source electrode, the drain electrode, so voltage capable of reducing power source.Consequently, can reduce power consumption.In addition, can realize high speed motion.
The meaning of so-called " high electric field region " is, with the electric field strength of semiconductor substrate surface vertical direction in the channel region zone more than or equal to 0.8 (MV/cm).
In addition, the meaning of so-called EOT is, the physical thickness of High-k film is scaled and SiO
2The value of the electric property thickness of film equivalence.
Of the present invention above-mentioned and other purpose, feature, aspect and advantage can from understand in conjunction with the accompanying drawings, about further clear and definite the detailed description below of the present invention.
Description of drawings
Fig. 1 is the profile of one of the structure of expression semiconductor device of the present invention example.
Fig. 2 is the section of structure that second half contemplated among the present invention conductor means is represented on pattern ground.
Fig. 3 is the graph of a relation of the physics thickness of expression mobility of the present invention and gate insulating film.
Fig. 4～Figure 11 is that order is represented the amplification profile of manufacture method of the semiconductor device of embodiment of the present invention 1 set by step.
Figure 12 is the amplification profile of manufacture method of the semiconductor device of expression embodiment of the present invention 2.
Figure 13 is the figure that is illustrated in electron mobility of measuring among sample A1～A4 and the electron mobility of measuring in sample C1～C4.
Figure 14 is the figure that is illustrated in the electron mobility of the electron mobility measured among sample B1～B4 and the mensuration in sample C1～C4.
Figure 15 is the figure that the maximum μ max of the electron mobility μ that will measure in each sample is drawn as curve.
Figure 16 is illustrated in S.Takagi et al., " On the Universality ofInversion Layer Mobility in Si MOSFET ' s:Part I-Effects ofSubstrate Impurity Concentration ", IEEE Trans.ElectronDevices., the figure of the pervasive curve of putting down in writing among the Vol.41 No.12 pp.2357-2362.1994.
Embodiment
Below, based on accompanying drawing embodiments of the present invention are described.
With reference to Fig. 1, (Shallow Trench Isolation: shallow trench isolation) 5a, 5b carry out the electricity isolation, form MISFET10 on substrate 1 surface after being isolated by electricity with each STI on substrate 1 surface.MISFET10 mainly has substrate 1 as Semiconductor substrate, as the dielectric film 11 of the 1st gate insulating film, as the dielectric film 12 of the 2nd gate insulating film.Substrate 1 has the channel region 20 of impurity concentration C in the presumptive area on surface.On channel region 20, form dielectric film 11, on dielectric film 11, form dielectric film 12.
With reference to Fig. 2, as the MISFET110 of second half conductor means have substrate 101 as second half conductive substrate, as the dielectric film 111 of another gate insulating film.Substrate 101 is the p N-type semiconductor N substrates that are made of silicon, forms the dielectric film 111 that is made of SiON on the precalculated position of substrate 101, forms gate electrode 113 on dielectric film 111.In addition, substrate 101 has the channel region 120 as another channel region on the zone under dielectric film 111 vertical.
With reference to Fig. 1 and Fig. 2, in the present embodiment, set the impurity concentration C of channel region 20 so that in the channel region 20 of MISFET10 the maximum of electron mobility than the maximum height of the electron mobility of the channel region 120 of MISFET110.Impurity concentration C is for example more than or equal to 2 * 10
17/ cm and smaller or equal to 1 * 10
20/ cm
3
With reference to Fig. 1, dielectric film 11 is for example by SiON or SiO
2Any one formation, still, also can constitute by the material beyond these, get final product so long as comprise the dielectric film of silicon and oxygen at least.SiON and SiO
2Be difficult to and dielectric film 12 reactions, have thermal endurance, and have higher dielectric constant, so, be suitable as the material of dielectric film 11.In addition, the EOT of dielectric film 11 for example for more than or equal to 0.55nm smaller or equal to 1.0nm.Be made into 0.55nm or more than the 0.55nm by thickness, can fully dielectric film 12 and substrate 1 be separated, and can improve the mobility of electronics dielectric film 11.In addition, be made into 1.0nm or below the 1.0nm, can guarantee can be used as the thickness level that gate insulating film works by thickness dielectric film 11.
In addition, MISFET10 also has the gate electrode 13 that forms on dielectric film 12.Gate electrode 13 for example is made of polysilicon, still, also can be made of the material beyond this.
In the semiconductor device of Fig. 1, the application's inventors are set at 0.30nm, 0.55nm, 0.75nm, 0.85nm respectively with the EOT of dielectric film 11 (boundary layer), study the physics thickness of the dielectric film 12 that the HfSiON under the various situations constitutes and the relation between the electron mobility.With effective electric-field intensity E
OffBe made as 0.8MV/cm.Its result shown in Figure 3.With reference to Fig. 3, along with the physics thickness attenuation of dielectric film 12, the mobility of electronics reduces.But, under the situation of the EOT of dielectric film 11 more than or equal to 0.55nm, compare less than the situation of 0.55nm with the EOT of dielectric film 11, kept higher mobility.
With reference to Fig. 1, continue the structure of the semiconductor device beyond described is described.On the surface of substrate 1, form sidewall 14, make it cover each side of dielectric film 11, dielectric film 12 and gate electrode 13.In addition, on the surface of substrate 1, form source region and drain region, make its clamping channel region 20.The source region is by n
+ Extrinsic region 4a and n type extrinsic region 3a constitute, and the drain region is by n
+ Extrinsic region 4b and n type extrinsic region 3b constitute.In addition, each p type extrinsic region 2a, 2b on each border of source region and drain region and substrate 1, have been formed.
With with n
+ Extrinsic region 4a is adjacent and that extend towards channel region 20, and mode forms n type extrinsic region 3a.N type extrinsic region 3a is formed on the zone under inside, sidewall 14 vertical of p type extrinsic region 2a.Equally, with n
+ Extrinsic region 4b is adjacent and that extend towards channel region 20, and mode forms n type extrinsic region 3b.N type extrinsic region 3b is formed on the zone under inside, sidewall 14 vertical of p type extrinsic region 2b.
Herein, n is compared in formation
+ Extrinsic region 4a, the zone that the 4b impurity concentration is low, promptly n type extrinsic region 3a, 3b thus, can relax the electric field of the near interface of drain region and channel region, can reduce the cut-off current value.In addition, on the border of source region and drain region and substrate 1, form p type extrinsic region 2a, 2b, thus, can prevent punch-through.
On the surface of substrate 1, form interlayer dielectric 7 in the mode that covers MISFET10.On interlayer dielectric 7, leave a plurality of holes that reach substrate 1 surface, form each contact 8a～8c in the mode of the inside of filling these holes respectively.And, on interlayer dielectric 7, form each wiring 9a～9c.Wiring 9a is by contact 8a and n
+ Extrinsic region 4a is electrically connected, and wiring 9b is electrically connected with gate electrode 13 by contact 8b, and wiring 9c is by contact 8c and n
+ Extrinsic region 4b is electrically connected.
Then, use Fig. 4～Figure 11 that the manufacture method of the semiconductor device of present embodiment is described.And,, near the enlarged drawing of channel region is shown about Fig. 4～Figure 11.
At first, with reference to Fig. 4, the substrate 1 that preparation is made of monocrystalline silicon forms each STI5a, 5b (Fig. 1) on substrate 1 surface.Then, be that 3keV, injection rate are 1 * 10 for example at acceleration energy
15/ cm
2Condition under, inject B from the direction ion of relative substrate 1 Surface Vertical.Thus, formation for example has more than or equal to 2 * 10
17/ cm
3And smaller or equal to 1 * 10
20/ cm
3The p type channel region 20 of impurity concentration C.
Then, with reference to Fig. 5, for example utilize and use HfCl
4And SiH
4As unstrpped gas, use H
2(Chemical Vapor Depositong: method chemical vapor deposition), the thickness with 0.7nm on substrate 1 forms the dielectric film 12a that is made of HfSiO to O as the CVD of oxidizing gas.In addition, except the CVD method, also can adopt the sputtering method of oxide target to form dielectric film 12a.
Then, with reference to Fig. 6, for example in partial pressure of oxygen more than or equal to 25Pa in the atmosphere smaller or equal to 100kPa, more than or equal to 1000 ℃ under less than 1100 ℃ temperature to substrate 1 heat treatment 20～40 seconds.Thus, the oxygen in the atmosphere carries out oxidation to substrate 1 surface after seeing through dielectric film 12a, forms by SiO on the surface of substrate 1
2The dielectric film 11a that constitutes.In addition, by heat-treating under the high temperature on 1000 ℃ or 1000 ℃, the Hf among the dielectric film 12a can spread in dielectric film 11a, improves the mobility of electronics.Then, dielectric film 12a is carried out pecvd nitride.Thus, dielectric film 12a is formed the dielectric film 12a that is made of HfSiON by nitrogenize.Like this, by HfSiO is nitrided into HfSiON, can make dielectric film 12 be difficult to crystallization.Nitriding method as HfSiO preferably uses pecvd nitride.By using pecvd nitride, thereby can reduce import volume, prevent the reduction of mobility the nitrogen of boundary layer (dielectric film 11).
Then, with reference to Fig. 7, for example form the conducting film 13a that constitutes by TaN (tantalum nitride) by the reactive sputtering method.As conducting film 13a, can use TiN (titanium nitride), WN (tungsten nitride), MoN (molybdenum nitride), ZrN (zirconium nitride) or HfN (hafnium nitride) etc. to replace TaN.And, can use sputtering method or CVD method to form the conducting film 13a that constitutes by W (tungsten).
Then,, form not shown photoresist with reference to Fig. 8, with this photoresist as mask with reservation shape etching dielectric film 11a, dielectric film 12a and conducting film 13a.Thus, formation is as dielectric film 11 and 12, the gate electrode 13 of gate insulating film.Then, remove photoresist.
Then, with reference to Fig. 9, be that 3keV, injection rate are 1 * 10 for example at acceleration energy
15/ cm
2Condition under, inject As (arsenic) from the direction ion of relative substrate 1 Surface Vertical, form n type extrinsic region layer 3a, 3b.Then, to surround the mode of each n type extrinsic region layer 3a, 3b, be that 10keV, injection rate are 4 * 10 for example at acceleration energy
13/ cm
2Condition under, inject B from the vertical direction ion on relative substrate 1 surface, form p type extrinsic region layer 2a, 2b.
Then,, for example use the plasma ion assisted deposition method under 400 ℃ temperature, on substrate 1, form the SiO of 50nm thickness in the mode that covers dielectric film 11 and 12, gate electrode 13 with reference to Figure 10
2And, optionally only on the side wall portion of gate electrode 13, keep SiO by anisotropic dry etch
2, form sidewall 14.Then, as mask, be that 30keV, injection rate are 2 * 10 with sidewall 14 for example at acceleration energy
15/ cm
2Condition under, inject As from the direction ion of relative substrate 1 Surface Vertical, form n
+ Extrinsic region 4a, 4b.Then, for example in blanket of nitrogen, under 1000 ℃ temperature, substrate 1 was annealed for 5 seconds, activate and inject ion.Finish MISFET10 thus.
Tetraethyl orthosilicate), SiO then, with reference to Figure 11, for example on substrate 1, form (Tetra Ethyl Or tho Silicate: by TEOS in the mode that covers MISFET10
2The perhaps interlayer dielectric 7 that constitutes such as SiOC.Then, on interlayer dielectric 7, form each n of arrival by common photomechanical process technology and lithographic technique
+Extrinsic region 4a, gate electrode 13 and n
+Hole 7a～7c of extrinsic region 4b.
Then, with reference to Fig. 1, on interlayer dielectric 7, form the conducting film that for example constitutes in the mode of filling each hole 7a～7c by W, Al (aluminium) or Cu (copper) etc.Then, remove conducting film unnecessary on the interlayer dielectric 7, form each contact 8a～8c.Then, on the interlayer dielectric 7 9a～the 9c that respectively connects up that is electrically connected on each contact 8a～8c is being carried out composition.Finish the semiconductor device of present embodiment by above step.
In semiconductor device of the present invention and manufacture method thereof, set the impurity concentration C of channel region 20 so that in the channel region 20 of MISFET10 the maximum of electron mobility than the maximum height of the electron mobility in the channel region 120 of MISFET110.Impurity concentration in the channel region of prior art is about 5 * 10
16/ cm
3, still, impurity concentration C of the present invention specifically, for example is more than or equal to 2 * 10 than the impurity concentration height of prior art
17/ cm
3And smaller or equal to 1 * 10
20/ cm
3Thus, can improve the mobility of electronics.
In addition, by forming dielectric film 11, the dielectric film 12 that the HfSiON as high dielectric constant material can be constituted separates with substrate 1.Thus, fixed charge and the channel region that exists in the dielectric film 12 can be separated.Consequently, can improve the mobility of electronics.
By improving electron mobility, can increase the electric current that flows through between source electrode, the drain electrode, reduce power consumption.In addition, can realize high speed motion.
And according to the semiconductor device of present embodiment, the electric field strength of channel region 20 is under the situation in high electric field strength zone, and the mobility that can improve electronics is to reach the degree that surpasses pervasive curve.
Semiconductor device of the present invention also has and comprises polysilicon, is formed on the gate electrode 13 on the dielectric film 12.
On the gate insulating film that constitutes by high-k, form the semiconductor device of the gate electrode that constitutes by polysilicon, compare with the semiconductor device that on the gate insulating film that only constitutes, forms the gate electrode that constitutes by polysilicon of prior art, for the impurity concentration that obtains the required channel region of same threshold value becomes low concentration (this phenomenon is called " pinning effect ") by SiON.For this reason, on the gate insulating film that constitutes by high dielectric constant material, form in the semiconductor device of the gate electrode that constitutes by polysilicon, even the impurity concentration of channel region is made into the concentration lower than prior art, also can obtains the required higher thresholds of practical application.Consequently, when comparing under the situation that applies identical supply voltage, it is lower than the effective electric field of SiON that the effective electric field of HfSiON becomes.Therefore, the semiconductor device that can be improved mobility and have the required higher thresholds of practical application.
In the manufacture method of present embodiment, substrate 1 is made of silicon, in the oxygen containing atmosphere of bag, more than or equal to 1000 ℃ under less than 1100 ℃ temperature to Semiconductor substrate oxidation 20 seconds～40, thus, form dielectric film 11a.Like this, can obtain by membranous good SiO
2The dielectric film 11 that constitutes.In addition, by under more than or equal to 1000 ℃ high temperature, heat-treating, thereby the Hf among the dielectric film 12a is spread in dielectric film 11a, improve the mobility of electronics.
In the manufacture method of execution mode 1, show formation by SiO
2The situation of the dielectric film 11 that constitutes.In the present embodiment, replace SiO to forming
2And the manufacture method the during dielectric film 11 that is made of SiON describes.
At first, with reference to Figure 12, at N
2In the O atmosphere substrate 1 that is made of silicon is carried out oxynitriding, thus, form the dielectric film 11a that constitutes by SiON.And, can be at N
2Carry out in the O atmosphere before the oxynitriding substrate 1 being carried out pecvd nitride.Then, with reference to Fig. 6, for example use mocvd method to form the dielectric film 12a that constitutes by HfSiO.
And, the manufacture method of the semiconductor device after this through with the identical manufacturing of manufacture method of the execution mode 1 of Fig. 1 and Fig. 7～shown in Figure 11.Therefore, omit its explanation.
In the manufacture method of the semiconductor device of present embodiment, substrate 1 is made of silicon, at N
2In the O atmosphere substrate 1 is carried out oxynitriding, form dielectric film 11a.Thus, can obtain the membranous good dielectric film 11 that constitutes by SiON.
In the present embodiment, with the material of gate insulating film, in the channel region impurity concentration combination mutually different modes design, produce semiconductor device shown in Figure 1, be made into sample A1～A4 and sample B1～B4.In addition, design, produce semiconductor device shown in Figure 2, be made into sample C1～C4 in the mutual different mode of the impurity concentration in the channel region.The material of the gate insulating film among each sample A1～A4, sample B1～B4 and the sample C1～C4 and the impurity concentration in the channel region are shown in following table 1.
Table 1
| The material of gate insulating film | Impurity concentration (/cm in the channel region 3) | | ||
| Dielectric film | ||||
| 12 | | |||
| Sample A1 | HfSiON/ | SiO 2 | 3.0×10 16 | Non-the present invention's product |
| Sample A2 | 4.0×10 17 | The present invention's product | ||
| Sample A3 | 9.0×10 17 | The present invention's product | ||
| Sample A4 | 1.5×10 18 | The present invention's product | ||
| Sample B1 | HfSiON | SiON | 3.0×10 18 | Non-the present invention's product |
| Sample B2 | 4.0×10 17 | The present invention's product | ||
| Sample B3 | 9.0×10 17 | The present invention's product | ||
| Sample B4 | 1.5×10 18 | The present invention's product | ||
| The material of gate insulating film 111 | Impurity concentration (/cm in the channel region 3) | Estimate | ||
| Sample C1 | SiON | 3.0×10 16 | Non-the present invention's product | |
| Sample C2 | 4.0×10 17 | |||
| Sample C3 | 9.0×10 17 | |||
| Sample C4 | 1.5×10 18 | |||
In described each sample A1～A4, sample B1～B4 and sample C1～C4, make electric field strength E perpendicular to the semiconductor substrate surface direction of channel region
EffChange, measure the electron mobility in the channel region.In Figure 15, line A connects the maximum μ that each sample A1～A4 is measured
MaxLine, line B connects the maximum μ that each sample B1～B4 is measured
MaxLine, line C connects the maximum μ that each sample C1～C4 is measured
MaxLine.
With reference to Figure 13～15, in the impurity concentration of channel region more than or equal to 2.0 * 10
17/ cm
3Regional center line A surpass line C.Specifically, between the sample of identical impurity concentration, compare each sample A1～A4 and each sample C1～C4, the maximum μ of the electron mobility among each sample A2～A4
MaxThe maximum μ that surpasses the electron mobility among each sample C2～C4
Max
In addition, the impurity concentration in channel region is more than or equal to 6.0 * 10
17/ cm
3Regional center line B ultrasonic cross line C.Specifically, between the sample of identical impurity concentration, compare each sample B1～B4 and each sample C1～C4, the maximum μ of the electron mobility among each sample B2～B4
MaxThe maximum μ that surpasses the electron mobility among each sample C2～C4
Max
And the electron mobility μ among sample A2～A4 and the sample B2～B4 surpasses the line X as pervasive curve in high electric field region.Therefore, from as can be known, can improve the mobility of electronics as the sample A2～A4 of product of the present invention and sample B2～B4.
By semiconductor device of the present invention being applied to especially thus, can expect the tremendous raising of device properties such as conducting electric current in the device below the 65nm node.
Describe the present invention in detail, still, this is for the purpose of illustration only, and is not to limit, and clearly, the spirit and scope of invention are only limited by additional claim scope.
Claims (10)
1. semiconductor device, comprise: have the channel region of impurity concentration C Semiconductor substrate, comprise silicon and oxygen and be formed on the 1st gate insulating film on the described channel region, comprise hafnium and oxygen and be formed on the 2nd gate insulating film on described the 1st gate insulating film, it is characterized in that
Imagine a kind of second half conductor means, this second half conductor means has: second half conductive substrate, and it has another channel region of impurity concentration C, is made of the material identical with described Semiconductor substrate; Another gate insulating film is formed on described another channel region and only is made of SiON,
Set the impurity concentration C of described channel region, so that the maximum of the electron mobility in the described channel region is become than the maximum height of the electron mobility in described another channel region.
2. as the semiconductor device of record in the claim 1, it is characterized in that,
Described impurity concentration C is more than or equal to 2 * 10
17/ cm
3And smaller or equal to 1 * 10
20/ cm
3
3. as the semiconductor device of record in the claim 1, it is characterized in that,
Described the 1st gate insulating film is by SiON or SiO
2In any one formation.
4. as the semiconductor device of record in the claim 1, it is characterized in that,
Described the 2nd gate insulating film is made of HfSiON.
5. as the semiconductor device of record in the claim 1, it is characterized in that,
When the electric field strength of described channel region was in high electric field strength zone, the electron mobility in the described channel region surpassed pervasive curve.
6. as the semiconductor device of record in the claim 1, it is characterized in that,
The equivalent oxide thickness of described the 1st gate insulating film more than or equal to 0.5nm smaller or equal to 1.0nm.
7. as the semiconductor device of record in the claim 1, it is characterized in that,
Also have and comprise polysilicon and be formed on gate electrode on described the 2nd gate insulating film.
8. the manufacture method of a semiconductor device is characterized in that,
Comprise following steps: the channel region that on Semiconductor substrate, forms impurity concentration C;
On described channel region, form the 1st gate insulating film that comprises silicon and oxygen; With
On described the 1st gate insulating film, form the 2nd gate insulating film that comprises hafnium and oxygen,
In the step that forms described channel region, set described impurity concentration C, so that make become electron mobility height in the channel region when on the channel region of impurity concentration C, only forming the gate insulating film that constitutes by silicon oxynitride of electron mobility in the described channel region.
9. as the manufacture method of the semiconductor device of record in the claim 8, it is characterized in that,
Described Semiconductor substrate is made of silicon,
The bag oxygen containing atmosphere in, more than or equal to 1000 ℃ under less than 1100 ℃ to 20～40 second time of described Semiconductor substrate oxidation, thus, form described the 1st gate insulating film.
10. as the manufacture method of the semiconductor device of record in the claim 8, it is characterized in that,
Described Semiconductor substrate is made of silicon,
By at N
2In the O atmosphere described Semiconductor substrate is carried out oxynitriding, thereby form described the 1st gate insulating film.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005077498 | 2005-03-17 | ||
| JP2005077498 | 2005-03-17 | ||
| JP2006038918 | 2006-02-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1835238A true CN1835238A (en) | 2006-09-20 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101986421A (en) * | 2009-07-28 | 2011-03-16 | 佳能安内华股份有限公司 | Dielectric film, method of manufacturing semiconductor device using dielectric film, and semiconductor manufacturing apparatus |
| CN102201447A (en) * | 2011-05-13 | 2011-09-28 | 湖北大学 | Gate medium field effect transistor with high dielectric constant and manufacturing method thereof |
-
2006
- 2006-03-17 CN CN 200610059663 patent/CN1835238A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101986421A (en) * | 2009-07-28 | 2011-03-16 | 佳能安内华股份有限公司 | Dielectric film, method of manufacturing semiconductor device using dielectric film, and semiconductor manufacturing apparatus |
| CN101986421B (en) * | 2009-07-28 | 2013-08-28 | 佳能安内华股份有限公司 | Dielectric film, method of manufacturing semiconductor device using dielectric film, and semiconductor manufacturing apparatus |
| CN102201447A (en) * | 2011-05-13 | 2011-09-28 | 湖北大学 | Gate medium field effect transistor with high dielectric constant and manufacturing method thereof |
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