CN1832042A - Program verification for non-volatile memory - Google Patents
Program verification for non-volatile memory Download PDFInfo
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- CN1832042A CN1832042A CNA2005101353995A CN200510135399A CN1832042A CN 1832042 A CN1832042 A CN 1832042A CN A2005101353995 A CNA2005101353995 A CN A2005101353995A CN 200510135399 A CN200510135399 A CN 200510135399A CN 1832042 A CN1832042 A CN 1832042A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0409—Online test
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/804—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout to prevent clustered faults
Abstract
A non-volatile memory device includes page buffers arranged in groups, each group being coupled to a corresponding data output line so that data from more than one of the page buffers in each group may be simultaneously represented on the corresponding data output line during a program verification operation. Page buffers may be arranged in repair units with data from more than one page buffer simultaneously coupled to a data output line during a column scan operation.
Description
According to 35U.S.C § 119, the non-temporary patent application of this US requires the right of priority of the korean patent application No.2004-116840 of submission on Dec 30th, 2004, and its content is in this combination, as a reference.
Technical field
The present invention relates to a kind of program verification of nonvolatile memory.
Background technology
Semiconductor memory is the critical elements such as the microelectronics system of computing machine and other application based on microprocessor (its scope is from the artificial satellite to the consumption electronic product).Therefore, advancing in the semiconductor memory manufacture process comprises by processing enhancing and technical development for the more calibration of high density and faster speed, promoted to set up more high-performance standard for other electronic logic series.
Semiconductor memory is usually expressed as volatibility or non-volatile.In volatile memory,, perhaps, come canned data by in for example static RAM (DRAM), capacitor being charged by in for example static RAM (SRAM), setting the logic state of trigger flip-flop.Under any circumstance, then store data and it can being read as long as apply power supply, but when cutting off the power supply obliterated data then.
Such as mask ROM (MROM), programmable read-only memory (prom), EPROM (Erasable Programmable Read Only Memory) (EPROM) and EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) though nonvolatile memory the time also can store data in outage.According to the manufacturing process that is adopted, the data of nonvolatile storage memory module can be permanent or reprogrammable.Nonvolatile memory is used for program and microcode storage in various application such as computing machine, avionics, telecommunications and consumption electronic product industry.Needs fast, use in the system of reprogrammable nonvolatile memory, such as the device of Nonvolatile sram (nvRAM) in the combination of also available single-chip volatibility and nonvolatile memory stores pattern.In addition, many particular memory structures are developed, and it comprises accessory logic circuit, be used for optimization they for the performance of application-specific task.
The nonvolatile semiconductor memory member of some type such as MROM, PROM and EPROM, all is or can not be wiped free of and rewrites, and perhaps must remove so that be wiped free of and reprogramming from system.Electricity can be wiped and can write when EEPROM was mounted in the system, and needing in the application of continuous reprogramming, such as system programming or auxiliary storage device to be widely used in.A kind of EEPROM that is called flash-EEPROM (" flash memory ") is advantageously used in the mass memory in the additional device, has high density of integration because it is compared with traditional EEPROM.The flash memory of two kinds of common type is NAND type (having higher integration density usually) and NOR type.
NAND type flash memory device comprises the memory cell array zone that is used for canned data.Memory cell array is formed by a plurality of unit strings that are known as the NAND string.Page buffer circuit is used for data storage to the memory cell array of flash memory or from the memory cell array reading of data of flash memory.Utilize known F-N (Fowler-Nordheim) channel current technology the storage unit in the NAND type flash memory is wiped and to programme.This U.S. patent No.5 that is disclosed in " NONVOLATILE SEMICONDUCTOR MEMORY " by name with programmed method that wipes, 473,563 and the U.S. patent No.5 of by name " NONVOLATILE INTEGRATED CIRCUIT MEMORY DEVICESHAVING ADJUSTABLE ERASE/PROGRAM THRESHOLD VOLTAGEVERIFICATION CAPABILITY ", in 696,717.
For with data storage in memory cell array, the Data Loading order at first is applied to flash memory.Then, address and data are input to flash memory successively.The data that will be programmed are that unit is sent to page buffer circuit in proper order with byte or word usually.In case page buffer circuit has expired, then all data in the page buffer circuit are programmed into memory cell array (in the storage unit corresponding to chosen page) simultaneously in response to program command.Wherein cycle (also being known as " program loop ") of being programmed of data comprises a plurality of program loop.Each program loop is divided into two parts, for example, and program part and program verification part.During program part, under given bias condition, storage unit is programmed in mode as known in the art.During the program verification part, storage unit access has been programmed into predetermined threshold value voltage so that verify them.Repeat said procedure circulation and be verified as up to all storage unit and programme, reach the maximum time amount.In program verification operating period, except the data that read only are used for the described programming operation of internal verification, with the mode visit data identical with normal running.
In order to determine whether storage unit is programmed into the threshold voltage of wanting, and has advised multiple verification method.A typical example is the U.S. patent No.5 that is disclosed in " NONVOLATILE SEMICONDUCTORMEMORY DEVICE AND AN OPTIMIZING PROGRAMMING METHODTHEREOF " (" ' 162 patent ") by name, 299, wired OR in 162 (wired-OR) type scheme, its content is hereby expressly incorporated by reference.Fig. 1 is the block scheme that is presented at disclosed memory device in ' 162 patents.Memory device comprises programming state testing circuit PS, and it is received in the data of storing among the latch LT of page buffer zone and detects whether instruction program data value of input data values during program verification part.For example, when the storage unit of all selections is programmed with optimum state, program state testing circuit PS output conventional sense signal.If the storage unit of at least one selection is not fully programmed, program state testing circuit PS output abnormality detection signal then.
In wired OR type program verification method, the state of selected storage unit is detected simultaneously, so the program verification time is short.Yet when having physical imperfection (for example, the adjacent page buffer zone is electrically connected) in page buffer zone, the program verification operation is subjected to the influence of defect pages buffer zone.In other words, even page buffer zone is replaced, the output of program state testing circuit PS instruction program failure always.In order to overcome these problems, introduced column scan type program verification method (being also referred to as " Y-scanning " type) in recent years.The example of the memory device of employing column scan type program verification method is disclosed the U.S. patent No.6 of " FLASH MEMORY DEVICE WITH PROGRAM STATUS DETECTIONCIRCUITRY AND THE METHOD THEREOF " (" ' 121 patent ") by name, 282, in 121, its content is hereby expressly incorporated by reference.Fig. 2 shows the block scheme that is disclosed in the memory device in ' 121 patents.
The memory device of Fig. 2 comprises program state testing circuit 190.In program verification operating period, the data bit that page buffer circuit 110 reads with default unit, is a unit with byte or word by column selection circuit passband 140 for example, is sent to program state testing circuit 190.Program state testing circuit 190 detects all input data bit and whether has been programmed to correct data value.According to described testing result, program state testing circuit 190 adds 1 with address counter 120.Therefore, the described read data bit in the page buffer circuit 110 is not detected simultaneously, and they are sent to program state testing circuit 190 by column selection circuit passband 140 with default unit.That is, the described reading of data in the page buffer circuit 110 is scanned so that verification of programming with default unit.
Except only internally utilizing the described reading of data in program verification operating period, the program verification operation of adopting above-mentioned Y-scanning technique is with the mode access data identical with conventional read operation.Comprise several program loop program loop, each program loop comprises program part and program verification part.Thereby the whole procedure time is subjected to the required time quantitative limitation of program verification operation.
Summary of the invention
In an example embodiment according to this patent invention disclosed principle, nonvolatile semiconductor memory member can comprise: comprise the page buffer circuit of a plurality of page buffer set, each page buffer set has a plurality of page buffer zones; A plurality of DOL Data Output Line, each output line are coupled to the page buffer zone in the respective page buffer set; And control circuit, control described page buffer circuit so that can on the corresponding data output line, represent simultaneously from the data in each page buffer set more than a page buffer zone according to operator scheme.
In another example embodiment according to this patent invention disclosed principle, a kind of method that is used for the program verification of nonvolatile semiconductor memory member can comprise: with the state of the storage unit of programming as data storage in the page buffer zone of arranging with page buffer set; And will be coupled to corresponding data output line simultaneously from the data in each page buffer set more than a page buffer zone for each page buffer set.
In another example embodiment according to this patent invention disclosed principle, a kind of nonvolatile semiconductor memory member can comprise: the first group of page buffer zone that is coupled to first DOL Data Output Line; And the second group of page buffer zone that is coupled to second DOL Data Output Line; Wherein forming more than a page buffer zone in each page buffer set repaired the unit; And wherein be coupled to the corresponding data output line simultaneously from each data more than a page buffer zone of repairing in unit in program verification operating period.
In another example embodiment according to this patent invention disclosed principle, a kind of method that is used for the program verification of nonvolatile semiconductor memory member can comprise: in page buffer set stored programme verification msg; To be sent to the corresponding data output line from the program verification data of page buffer set by carrying out the column scan operation; And the data of at least two page buffer zones in column scan operating period simultaneously will be from a group are sent to the corresponding data output line.
Description of drawings
Fig. 1 is the block scheme that shows the memory device that adopts wired OR prior art program verification method.
Fig. 2 is the block scheme that shows the memory device of the Y-scan type program verification method that adopts prior art.
Fig. 3 is the schematic block diagram according to the embodiment of the NAND type flash memory device of this patent invention disclosed principle.
Fig. 4 shows according to the page buffer circuit of inventive principle disclosed by the invention and selects circuit
The block scheme of embodiment.
Fig. 5 is the circuit diagram of demonstration according to the embodiment of the page buffer zone of this patent invention disclosed principle.
Fig. 6 is the circuit diagram of demonstration according to the embodiment of the column decoder of this patent invention disclosed principle.
Fig. 7 is the sequential chart of explanation according to the embodiment of the program verification operation of the nonvolatile semiconductor memory member of this patent invention disclosed principle.
Embodiment
By describing preferred embodiment with reference to the accompanying drawings hereinafter in detail according to this patent invention disclosed principle.Yet the principle of the invention can embody with different forms, and the embodiment that is not limited to herein illustrate.On the contrary, provide these embodiment so that the disclosure will be thorough more and comprehensive, and will pass on scope of the present invention fully to those skilled in the art.
Fig. 3 is the schematic block diagram of demonstration according to the embodiment of the nonvolatile semiconductor memory member of this patent invention disclosed principle.Illustrate the embodiment of Fig. 3 from the angle of NAND type flash memory device.Yet the principle of the invention also can be applicable to the nonvolatile memory of other types.
With reference to figure 3, nonvolatile semiconductor memory member 1000 comprises the memory cell array 1100 that is used to store data.Described memory cell array 1100 comprises a plurality of unit strings, is the NAND string in this example.Each unit strings selects a plurality of flashing storage units between the transistor to form by being connected in series to first and second.One is selected transistor is string select transistor (string selection transistor), and another selection transistor is that ground connection is selected transistor (ground selection transistor).String and ground connection select transistor respectively by string and the control of ground connection selection wire.The flashing storage unit of each unit strings forms with the floating gate transistor.Transistorized control gate is connected respectively to control signal corresponding (for example, word line).
Row decoder circuit (being represented by " X-DEC " in Fig. 3) 1200 bases are selected word line from the row address RA of address generating circuit 1300, and word line voltage are applied to the word line and the unselected word line of selection according to corresponding operator scheme.For example, row selects circuit 1200 that programm voltage is applied to the word line of selecting and will be applied to unselected word line by voltage (being lower than programm voltage) during program operation mode.In addition, row is selected circuit 1200 that ground voltage is applied to the word line of selecting during read operation and will read voltage (be lower than by voltage but voltage) above Ground to be applied to unselected word line.Described program, by with read voltage usually above supply voltage, so they are to utilize known charge pump technology to be produced by high voltage generating circuit.
Address generating circuit 1300 is by steering logic 1400 controls and generate row and column address RA and CA.Column decoder circuit (in Fig. 3 by " Y-DEC " expression) 1500 is in response to operating from the control signal YSCAN_EN of steering logic 1400 and YA_EN, and the described column address CA that decodes selects signal Ypi, Yqj and Yrj (wherein, i and j are positive integers) to produce first to the 3rd.As control signal YSCAN_EN when being invalid, promptly, except any operating period of program verification operation (for example, read, program and erase operation etc.), column decoder circuit 1500 only activates first in response to control signal YA_EN and column address CA and selects one of signal YPi.When control signal YSCAN_EN is activated, that is, in program verification operating period, column decoder circuit 1500 can activate two or more first simultaneously and select signal YPi in response to control signal YA_EN and column address CA, as will be described in detail below.
Arrangement is electrically connected to page buffer circuit 1600 by the bit line BL0-BLm and the RBL0-RBLx of memory cell array 1100.Page buffer circuit 1600 reading/verification operation during sensing from the data of the storage unit of the word line that is coupled to selection by bit line BL0-BLm and RBL0-RBLx.During procedure operation, page buffer circuit 1600 is according to will data programmed supply voltage (or program inhibition voltage) or ground voltage (or programm voltage) being applied to bit line BL0-BLm and RBL0-RBLx.Page buffer circuit 1600 comprises and bit line BL0-BLm and the corresponding page buffer zone of RBL0-RBLx.In certain embodiments, but page buffer zone share bit lines.Page buffer circuit 1600 selects signal Ypi that reading of data is outputed to local data output line LDOLn in response to first.A plurality of page buffer zones (being known as " page buffer set ") are connected to one of each DOL Data Output Line jointly.Page buffer zone in the page buffer set selects signal Ypi to select by first respectively.For example, when activating one when selecting signal, be coupled to corresponding local data output line from the data of a page buffer zone of each page buffer set.When signal is selected in activation all or some, from data reflection jointly in their corresponding local data output lines of whole or some page buffer zones in each page buffer set.Because all or some first select signal Ypi to be activated in program verification operating period, from the reading of data value of two or more page buffer zones can be reflected in simultaneously with the corresponding local data output line of each page buffer set on.And page buffer circuit 1600 selects signal Ypi to latch from data local data incoming line LDILn, that will be programmed into memory cell array in response to first.
In an example embodiment, in program verification operating period, such as (Yp0, Yp1), (Yp2, Yp3), (Yp4 Yp5) waits and activates first in couples and select signal Ypi.In some embodiment according to the nonvolatile semiconductor memory member of this patent invention disclosed principle, when determining that a page buffer zone has defective (determining that perhaps a page buffer zone will be connected to the defective bit line), repair page buffer zone with defective by replacing other one or more page buffer zones.In this case, repair page buffer zone with defective and adjacent page buffer zone by replacing two other page buffer zones simultaneously.Therefore, two page buffer zones comprise that is repaired a unit in this embodiment.To comprise simultaneously that in program verification operating period the reading of data value of two page buffer zones repairing the unit is reflected on the local data output line.Similarly, the reading of data value of other page buffer zones of arranging in the reparation unit also is reflected on the corresponding local data output line simultaneously.
Select circuit 1700 to select signal (Yqj, Yrj) operation in response to the second and the 3rd.Reading/verification operation during, select circuit 1700 to select signal (Yqj in response to the second and the 3rd, Yrj) (for example with predetermined unit, x8, x16, x32 etc.) select local data output line LDOLn, and respectively the data on the local data output line of selecting are sent to corresponding global data output line GDOLx.Be written into operating period in data, select circuit 1700 to select signal (Yqj in response to the second and the 3rd, Yrj) (for example with predetermined unit, x8, x16, x32 etc.) select local data incoming line LDILn, and respectively will be from the Data In-Line that will data programmed be sent to selection of global data incoming line GDILn.Global data incoming line GDILn is electrically connected to data input/output circuit 1800, will data programmed to receive.Global data output line GDOLn is electrically connected to data input/output circuit 1800 during read operation, with the output reading of data.Be electrically connected to global data output line GDOLn by/failure checking circuit 1900 in program verification operating period, to receive by the data of selecting circuit 1700 to select.Data input/output circuit 1800 is imported data and is exported reading of data with the reception program by steering logic 1400 controls.
Although be not shown among Fig. 3, can in data input/output circuit 1800, provide the device that for example is used for precharge global data input/output line.
Whether has correct value by all data on/failure checking circuit 1900 check global data output line GDOLn.If all data values are correct, then arrive steering logic 1400 by pass through of passing through of/failure checking circuit 1900 output instruction programs/failure signal PF.If any one input data values is incorrect, arrive steering logic 1400 by pass through of/failure checking circuit 1900 output instruction programs failure/failure signal.Steering logic 1400 is the parts that comprise the overall control circuit of address generating circuit 1300 and column decoder circuit 1500.Steering logic 1400 is constructed to control the operation of nonvolatile semiconductor memory member 1000.Steering logic 1400 program verification operating period in response to by/failure signal PF and control address generative circuit 1300 and column decoder circuit 1500.For example, when by/failure signal PF instruction program by the time, steering logic 1400 control address generative circuits 1300 increase suitable amount with column address CA, for example 1, simultaneously, activation control signal YSCAN_EN continuously.In other words, carry out the Y-scan operation continuously.When by the failure of/failure signal PF instruction program, steering logic 1400 invalid control signal YSCAN_EN, the operation of halt address generative circuit 1300 simultaneously.That is, the Y-scan operation is stopped, and comprises that then another program loop of procedure operation is performed under the control of steering logic 1400.In this case, address generating circuit 1300 is not initialised.Alternatively, in the program verification operating period of next program loop, the previous column address that generates is used as the initial column address.
As mentioned above, because a plurality of first select signal Ypi to be activated simultaneously, be reflected in simultaneously in the local data output line in program verification operating period from the data value of at least two page buffer zones.By/failure checking circuit 1900 based on the information trace routine that in the local data output line, reflects by/failure.Therefore, the execution Y-required time of scan operation can reduce, and as its result, can reduce the whole procedure time.
Fig. 4 is the page buffer circuit and the block scheme of selecting embodiment of circuit that shows according to the inventive principle of this patent disclosure.
With reference to figure 4, page buffer circuit 1600 is formed by a plurality of page buffer set PBG0-PGBy.Each page buffer set PBG0-PBGy for example is to be formed by 8 page buffer zone PB0-PB7.The corresponding page buffer zone PB0-PB7 that selects signal Yp0-Yp7 to be applied to each page buffer set.For example, select signal Yp0 to be applied to page buffer zone PB0, and select signal Yp1 to be applied to page buffer zone PB1.The number of page buffer set PBG0-PBGy equates with the number of local data output line LDOL0-LDOLy.The page buffer zone of page buffer set is connected to corresponding local data output line jointly.For example, the page buffer zone PB0-PB7 of page buffer set PBG0 is connected to local data output line LDOL0 jointly.The page buffer zone PB0-PB7 of page buffer set PBG1 is connected to local data output line LDOL1 jointly.(for example, when YP0) being activated, the page buffer zone PB0 that has wherein applied the page buffer set PBG0-PBGy of the selection signal Yp0 that activates outputs to corresponding local data output line LDOL0-LDOLy with data value when one that selects signal Yp0-Yp7.
Page buffer set PBG0-PBGy also is connected respectively to local data incoming line LDIL0-LDILy.The local data incoming line is connected to the page buffer zone of respective page buffer set jointly.For example, the page buffer zone PB0-PB7 of page buffer set PBG0 is connected to local data incoming line LDIL0 jointly.When (for example activate selecting one of signal Yp0-Yp7, Yp0) time, the data value that will become on the corresponding local data incoming line LDIL0-LDILy is sent to the page buffer zone PB0 of the page buffer set PBG0-PBGy that has wherein applied the selection signal Yp0 that activates respectively.It is right that each local data incoming line LDIL0-LDILy can form differential, so that transmit complementary data signal, but only shows a local data incoming line for convenience.Similarly, unclear in order to prevent accompanying drawing, final data incoming line LDILy among Fig. 4 is shown as all page buffer zone PB0-PB7 that are connected to page buffer set PBGy, but other Data In-Lines also are construed as and will be coupled to all page buffer zones that they are organized separately.
With reference to figure 4, select circuit 1700 to comprise demoder 1710, input switch SWIN0-SWINy and output switch SW OUT0-SWOUTy.Signal is selected in demoder 1710 decodings, and (Yqj is Yrj) to produce switch controlling signal S0-Sy.Switch controlling signal SO-Sy is activated so that connect the I/O switch with predetermined unit (for example x8, x16, and x32).Data in program schema are written into operating period, input switch SWIN0-SWINy selects local data incoming line LDIL0-LDILy in response to the respective switch control signal, and will be from global data incoming line GDILx will data programmed optionally be sent to incoming line.Reading/verification operation during, output switch SW OUT0-SWOUTy optionally is connected to local data output line LDOL0-LDOLy in response to the respective switch control signal with global data output line GDOLx.
Fig. 5 is the circuit diagram of demonstration according to the embodiment of the page buffer zone of this patent invention disclosed principle.
The page buffer zone of Fig. 5 is corresponding to a page buffer zone of page buffer circuit 1600, and remaining page buffer zone is basic identical with the page buffer zone of Fig. 5.Page buffer zone PB0 comprises register REG and data output unit DOP.Register REG is constructed to during procedure operation to latch in response to selecting signal Yp0 the data from local data incoming line LDIL0.In addition, register REG is constructed to latch the data from storage unit by bit line BL0 during read operation.During read operation, data output unit DOP is according to the value of storing in register REG and select signal Yp0 ground connection DOL Data Output Line LDOL0.Data output unit DOP comprises first switch SW 1 and second switch SW2.First switch SW 1 is by the value control that is stored among the register REG, and second switch SW2 is by selecting signal Yp0 control.
Reading/verification operation during, if the storage unit of selecting is a switching units (off-cell) (programmed cells), register REG is constructed to the output logic low level.In other words, if the storage unit of selecting is switching units (programmed cells), then first switch SW 1 of data output unit DOP is disconnected.On the contrary, if the storage unit of selecting is an on-unit (on-cell) (erase unit), register REG is constructed to the output logic high level.That is, if the storage unit of selecting is an on-unit, then first switch SW 1 of data output unit DOP is connected.
Will data programmed be sent to register REG by following processing.Will data programmed be sent to the local data incoming line (for example, LDIL0) by data input/output circuit 1800 and selection circuit 1700.If data are " 0 ", then local data incoming line LDIL0 is low.If will data programmed be " 1 ", then local data incoming line LDIL0 be high.When selecting signal Yp0 to be activated (being driven to logic high), the data on the local data incoming line LDIL0 are written into register REG.During procedure operation, according to the data that are written into register REG, bit line BL0 is set to supply voltage or ground voltage, and the storage unit that is connected to the selection in the unit strings of bit line BL0 is programmed in known manner.
The state of the storage unit of programming is read and the following register REG that is sent to.Register REG passes through the state of the storage unit of bit line BL0 sensing selection, and temporarily stores the state of sensing.If the storage unit of selecting is switching units (programmed cells), then register REG outputs to first switch SW 1 with low level signal.Even select signal Yp0 to be activated, local data output line LDOL0 is in pre-charge state, for example, and logic high.This is because first switch SW 1 is disconnected.If the storage unit of selecting is on-unit (erase unit), then register REG outputs to first switch SW 1 with high level signal.When selecting signal Yp0 to be activated, connect first switch SW 1, so that by connecting switch SW 1 and SW2 with local data output line LDOL0 ground connection.Data on the local output line LDOL0 are sent to by/failure checking circuit 1900 by selecting circuit 1700.
Fig. 6 is the circuit diagram of demonstration according to the embodiment of the column decoder circuit of this patent invention disclosed principle.
With reference to figure 6, column decoder circuit 1500 comprises first demoder 1510 and second demoder 1520.First demoder 1510 is in response to control signal YSCAN_EN and the YA_EN first column address CA0-CA2 that decodes, and produces first according to decoded result and select signal Yp0-Yp7.Second demoder 1520 is in response to control signal YA_EN and YA_EN decoding secondary series address CA3-CAz, and according to decoded result produce the second and the 3rd select signal (Yqj, Yrj).First demoder, 1510 decoding column address signal CA1 and CA2 activate first and select signal Yp0-Yp7, and do not consider column address signal CA0 when being activated into logic high with convenient control signal YSCAN_EN.This means between the active period of control signal YSCAN_EN, activate two simultaneously in response to column address signal and select signal.
In Fig. 6, first demoder 1510 is constructed to select signal so that activate two simultaneously, but can activate the selection signal (for example, 4 or all selection signals) of any other number simultaneously.
Fig. 7 is the sequential chart of explanation according to the program verification operation of the nonvolatile semiconductor memory member of this patent invention disclosed principle.When nonvolatile semiconductor memory member entered program operation mode, address generating circuit 1300 generated column address in proper order according to the input column address under the control of steering logic 1400.Column decoder circuit 1500 in response to the column address that generates produce first to the 3rd select signal (Ypi, Yqi, Yrj).At this moment, because control signal YSCAN_EN is not activated, only first select one of signal Yp0-Yp7 to be activated.That is, only select among the page buffer zone PB0-PB7 in each page buffer set one.(Yqj Yrj) selects some local data incoming lines to select circuit 1700 to select signal in response to the second and the 3rd.In this case, will data programmed be sent to global data incoming line GDILx by data input/output circuit 1800.Will be sent to the local data incoming line of selecting circuit 1700 to select in the data programmed position.Will be written into the respective page buffer zone in the data programmed position, described page buffer zone is connected to the local data incoming line of selection and receives the first selection signal that activates.By this process, will be written into page buffer circuit 1600 in the data programmed position.
When utilizing supply voltage or ground voltage to drive bit line according to line of input address selection word line and according to the data bit that is written into, the storage unit that is coupled to the word line of selection is programmed in pre-set programs cycling time.In case carry out the procedure operation of first program loop, then whether the program verification operation reaches required threshold voltage with the threshold voltage of the storage unit of definite programming.In order to measure threshold voltage, in aforesaid identical mode, read the storage unit of selection and with their state storage in the register REG of page buffer circuit 1600.After the state of the storage unit of selecting was stored in the page buffer circuit 1600, steering logic 1400 activated the control signal YSCAN_EN of the beginning of indication Y-scan operation.Then, in page buffer circuit 1600 storage data value utilize the Y-scanning technique be sent in proper order by/failure checking circuit 1900.At this moment, address generating circuit 1300 generates column address CA under the control of steering logic 1400.
The logic level of local data output line is by selecting circuit 1700 to be sent to the global data output line.Whether be programmed into the threshold voltage that needs by/failure checking circuit 1900 in response to the storage unit that the logic level of global data output line detects the column address of current generation.If storage unit is programmed into the threshold voltage that needs, then steering logic 1400 is in response to making address generating circuit 1300 produce next column address by/failure signal PF.To carry out next Y-scan operation in the same manner as described above subsequently.In addition, steering logic 1400 is in response to making control signal YA_EN and YSCAN_EN lose efficacy, so that finish the present procedure verification operation by/failure signal PF.Next then program loop is repetitive routine/proving period in an identical manner.
As mentioned above, in program verification operating period, can be in a local data output line data value of the two or more at least page buffer zones of reflection simultaneously.As a result, can reduce the time of carrying out the Y-scan operation, reduce the whole procedure time thus.
Although the present invention describes with reference to its specific preferred embodiment, this patent invention disclosed principle is not limited to this.But it should be appreciated by those skilled in the art, under the situation that does not break away from the principle of the invention, can carry out various replacements, modification and change it.
Claims (32)
1. nonvolatile semiconductor memory member comprises:
The page buffer circuit that comprises a plurality of page buffer set, each page buffer set has a plurality of page buffer zones;
A plurality of DOL Data Output Line, each DOL Data Output Line are coupled to the page buffer zone in the respective page buffer set; And
Control circuit, control page buffer circuit is so that will show simultaneously on the corresponding data output line from the data more than a page buffer zone of each page buffer set according to operator scheme.
2. nonvolatile semiconductor memory member as claimed in claim 1, wherein control circuit can be controlled page buffer circuit, so that, will show simultaneously on the corresponding data output line from the data more than a page buffer zone of each page buffer set in program verification operating period.
3. nonvolatile semiconductor memory member as claimed in claim 1, wherein control circuit can be controlled page buffer circuit, so that in program verification operating period, the data more than a page buffer zone of the reparation unit of self-forming page buffer set show on the corresponding data output line simultaneously in the future.
4. nonvolatile semiconductor memory member as claimed in claim 1, wherein control circuit can be controlled page buffer circuit, so that during read operation, will be from the present corresponding data output line of the tables of data more than a page buffer zone of each page buffer set.
5. nonvolatile semiconductor memory member as claimed in claim 1 also comprises:
Select circuit, select DOL Data Output Line with predetermined unit; And
By/failure checking circuit, in program verification operating period, from the DOL Data Output Line of selecting receive data with determine program by or failure.
6. nonvolatile semiconductor memory member as claimed in claim 5, wherein control circuit be constructed in response to by/failure checking circuit output come the control program verification operation.
7. nonvolatile semiconductor memory member as claimed in claim 5 also comprises a plurality of Data In-Lines that are coupled to the respective page buffer set.
8. nonvolatile semiconductor memory member as claimed in claim 7 is wherein selected circuit to be written into operating period in data and is selected Data In-Line with predetermined unit, and will data programmed being sent on the selected incoming line.
9. nonvolatile semiconductor memory member as claimed in claim 8, wherein control circuit can be controlled page buffer circuit, so that latch the data value of the transmission that will programme.
10. nonvolatile semiconductor memory member as claimed in claim 1, wherein
Page buffer zone in each page buffer set is selected signal in response to first and is operated;
Control circuit comprises decoder circuit, activate simultaneously according to operator scheme, in response to first column address all or some first select signal; And
When activating all or some first when selecting signal simultaneously, shown simultaneously in the corresponding DOL Data Output Line from the data of all or some page buffer zone of each page buffer set.
11. nonvolatile semiconductor memory member as claimed in claim 10, wherein control circuit comprises the steering logic that is configured to the control program verification operation.
12. nonvolatile semiconductor memory member as claimed in claim 11 also comprises:
Select circuit, select DOL Data Output Line with predetermined unit; And
By/failure checking circuit, program verification operating period from the DOL Data Output Line of selecting receive data with determine program by or failure.
13. nonvolatile semiconductor memory member as claimed in claim 12, wherein decoder circuit produces second and selects signal in response to the secondary series address.
14. nonvolatile semiconductor memory member as claimed in claim 13, wherein select circuit to be written into operating period and select signal to select to be coupled to the Data In-Line of respective page buffer set with predetermined unit in response to second in data, and will data programmed being sent on the selected Data In-Line.
15. nonvolatile semiconductor memory member as claimed in claim 14 is wherein selected signal in response to first and second, will data programmed being stored in the respective page buffer set.
16. nonvolatile semiconductor memory member as claimed in claim 1, wherein each page buffer zone comprises:
Be configured to store the register of data; And
The data output unit is constructed to when signal is selected in activation corresponding first according to the data-driven corresponding data output line of storing in register.
17. nonvolatile semiconductor memory member as claimed in claim 16, wherein:
Each register is constructed to when respective memory unit is programmed cells first logic level be outputed to the corresponding data output unit; And
Each register is constructed to when respective memory unit is erase unit second logic level be outputed to the corresponding data output unit.
18. nonvolatile semiconductor memory member as claimed in claim 16, wherein: each data output unit comprises:
First switch is arranged to by corresponding registers and controls; And
Second switch with the first switch series coupled, and is arranged to the Be Controlled in response to the corresponding first selection signal.
19. nonvolatile semiconductor memory member as claimed in claim 12 also comprises the address generating circuit that generates column address.
20. a method that is used for the program verification of nonvolatile semiconductor memory member comprises:
With the state of storage unit of programming as in the page buffer zone of data storage in being arranged in page buffer set; And
To be coupled to the corresponding data output line of each page buffer set from the data in each page buffer set simultaneously more than a page buffer zone.
21. method as claimed in claim 21 wherein selects signal that the data in first page buffer zone in each page buffer set are coupled to the corresponding data output line in response to first.
22. method as claimed in claim 22 wherein selects signal that the data in second page buffer zone in each page buffer set are coupled to the corresponding data output line in response to second.
23. method as claimed in claim 23 wherein activates the first and second selection signals simultaneously in response to scan enable signals and column address information.
24. method as claimed in claim 21, wherein forming more than a page buffer zone in each page buffer set repaired the unit.
25. a nonvolatile semiconductor memory member comprises:
Be coupled to first group of page buffer zone of first DOL Data Output Line; And
Be coupled to second group of page buffer zone of second DOL Data Output Line;
Wherein forming more than a page buffer zone in each page buffer set repaired the unit; And
Wherein, be coupled to corresponding DOL Data Output Line simultaneously from each data more than a page buffer zone of repairing in unit in program verification operating period.
26. nonvolatile semiconductor memory member as claimed in claim 26 is wherein in response to selecting signal that data are sent to the corresponding data output line from page buffer zone.
27. nonvolatile semiconductor memory member as claimed in claim 27, wherein each selects signal to be coupled to more than the page buffer zone in the group.
28. nonvolatile semiconductor memory member as claimed in claim 28 wherein produces the selection signal in response to scan enable signals and column address information.
29. a method that is used for the program verification of nonvolatile semiconductor memory member comprises:
Stored programme verification msg in page buffer set;
To be sent to the corresponding data output line from the program verification data of page buffer set by carrying out the column scan operation; And
In column scan operating period, will be sent to the corresponding data output line simultaneously from the data of at least two page buffer zones in the group.
30. method as claimed in claim 30 wherein selects signal to carry out scan operation in response to column address information by activating successively.
31. method as claimed in claim 31 wherein in column scan operating period, activates at least two simultaneously and selects signals.
32. forming, method as claimed in claim 32, the page buffer zone that wherein receives the selection signal that activates simultaneously in the group repair the unit.
Applications Claiming Priority (2)
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| KR116840/04 | 2004-12-30 | ||
| KR1020040116840A KR100648277B1 (en) | 2004-12-30 | 2004-12-30 | Flash memory device capable of reducing program time |
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| CN1832042A true CN1832042A (en) | 2006-09-13 |
| CN100585739C CN100585739C (en) | 2010-01-27 |
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| US (1) | US7719897B2 (en) |
| JP (1) | JP4942991B2 (en) |
| KR (1) | KR100648277B1 (en) |
| CN (1) | CN100585739C (en) |
| DE (1) | DE102005063166B4 (en) |
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| CN102081972B (en) * | 2009-11-27 | 2015-05-20 | 上海华虹集成电路有限责任公司 | Test circuit for EEPROM device and test method thereof |
| CN108122588A (en) * | 2016-11-30 | 2018-06-05 | 三星电子株式会社 | Non-volatile memory devices and the storage device for including it |
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| JP4510060B2 (en) * | 2007-09-14 | 2010-07-21 | 株式会社東芝 | Read / write control method for nonvolatile semiconductor memory device |
| KR100947480B1 (en) | 2007-10-08 | 2010-03-17 | 세메스 주식회사 | Spin head, chuck pin used in the spin head, and method for treating a substrate with the spin head |
| US8098532B2 (en) | 2007-11-20 | 2012-01-17 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device with address search circuit used when writing |
| KR101160172B1 (en) | 2008-11-26 | 2012-06-28 | 세메스 주식회사 | Spin head |
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| US8325534B2 (en) * | 2010-12-28 | 2012-12-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Concurrent operation of plural flash memories |
| KR102083450B1 (en) | 2012-12-05 | 2020-03-02 | 삼성전자주식회사 | Nonvolatile memory device comprising page buffer and operation method thereof |
| KR20150106145A (en) * | 2014-03-11 | 2015-09-21 | 삼성전자주식회사 | Method for performing program operation and read operation in memory device |
| KR20160071769A (en) | 2014-12-12 | 2016-06-22 | 삼성전자주식회사 | Semiconductor memory device and memory system including the same |
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| KR950000273B1 (en) * | 1992-02-21 | 1995-01-12 | 삼성전자 주식회사 | Non-volatile semiconductor memory device and optimal write method |
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2005
- 2005-12-07 US US11/297,779 patent/US7719897B2/en active Active
- 2005-12-13 JP JP2005359407A patent/JP4942991B2/en active Active
- 2005-12-27 CN CN200510135399A patent/CN100585739C/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102081972B (en) * | 2009-11-27 | 2015-05-20 | 上海华虹集成电路有限责任公司 | Test circuit for EEPROM device and test method thereof |
| CN108122588A (en) * | 2016-11-30 | 2018-06-05 | 三星电子株式会社 | Non-volatile memory devices and the storage device for including it |
| CN108122588B (en) * | 2016-11-30 | 2023-06-27 | 三星电子株式会社 | Nonvolatile memory device and memory device including the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100585739C (en) | 2010-01-27 |
| US7719897B2 (en) | 2010-05-18 |
| JP2006190448A (en) | 2006-07-20 |
| US20060155896A1 (en) | 2006-07-13 |
| JP4942991B2 (en) | 2012-05-30 |
| DE102005063166A1 (en) | 2006-11-09 |
| KR20060078142A (en) | 2006-07-05 |
| KR100648277B1 (en) | 2006-11-23 |
| DE102005063166B4 (en) | 2017-04-06 |
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