CN102081972B - Test circuit for EEPROM device and test method thereof - Google Patents
Test circuit for EEPROM device and test method thereof Download PDFInfo
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- CN102081972B CN102081972B CN200910199595.7A CN200910199595A CN102081972B CN 102081972 B CN102081972 B CN 102081972B CN 200910199595 A CN200910199595 A CN 200910199595A CN 102081972 B CN102081972 B CN 102081972B
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Abstract
The invention relates to a test circuit for EEPROM device and a test method thereof. The test circuit comprises a main controller, a test unit which is connected with a first IO port data line of the main controller, and a decoding circuit which is connected with a second IO port control line of the main controller. On one hand the main controller outputs a test starting signal to the test unit, on the other hand, the main controller receives the test data which is output by the test unit, and generates and storages corresponding statistical and analytic information; the decoding circuit receives decoding signals from the main controller, and decodes the second IO port control line into addresses of row-and-column control lines, and sets the addresses of row-and-column control lines to high or low levels. The invention effectively enhances the test efficiency, reduces the test cost, realizes real-time test of every device to be tested, and simultaneously enables test data to be abundant and visual.
Description
Technical field
The present invention relates to a kind of EEPROM device detection circuit and method of testing thereof.
Background technology
Eeprom memory has a wide range of applications and prospect in the production, life of people.Along with the continuous lifting of the improving constantly of memory span, memory product tempo of development, product test ability fast and efficiently becomes vital link in whole product development process gradually.How to find in memory product exploitation a kind of fast, the method for testing of low cost, can meet product development needs and can support various different testing requirement flexibly again, be put the major issue that must solve in face of memory product developer to complete the test of more complicated and higher batch.
All the method utilizing on I/O port line parallel chip or connect a chips on an IO line to realize batch testing in traditional EEPROM test, traditional eeprom memory functional test circuit as shown in Figure 1, n the measured device 2 ' that circuit comprises a controller 1 ' and is connected on the I/O port line of this controller 1 ', and at most can 8 measured devices 2 ' in parallel on every root I/O port line of controller 1 ', namely the I/O port of 8 measured devices 2 ' shares a data line and is connected with controller 1 '.But because the restriction of controller 1 ' driving force, more measured device 2 ' can not be tested simultaneously; In addition, because measured device 2 ' might not have chip select address line, therefore, controller 1 ' can not monitor the state of each measured device 2 ' constantly; Although and existing one single chip is tested the mode adopted and is achieved real-time control, cannot realize batch testing, thus considerably increase testing cost.
Summary of the invention
In order to solve above-mentioned prior art Problems existing, the present invention aims to provide a kind of EEPROM device detection circuit and method of testing thereof, effectively to improve testing efficiency, to reduce testing cost, realize the detection constantly of each measured device, make test data abundant directly perceived simultaneously.
A kind of EEPROM device detection circuit that one of the present invention is described, it comprises a master controller, a test cell be connected with the data line of the first I/O port of this master controller and a decoding scheme be connected with the control line of the second I/O port of described master controller,
Described master controller exports test enable signals to described test cell on the one hand, receives the test data that this test cell exports on the other hand, generates and stores corresponding statistical study information;
Described decoding scheme receives decoded signal from described master controller, the address decoding of the control line of this master controller second I/O port to be embarked on journey the address of control line and row control line, and the address of described row control line and row control line is set to high level or low level;
Described test cell is connected with decoding scheme with row control line by described row control line.
In above-mentioned EEPROM device detection circuit,
First I/O port of described master controller comprises the capable data line of N root and N root column data line, and described row data line and column data line are arranged in a reticulate texture by the form of intersecting in length and breadth;
Described test cell comprises N
2the individual measured device pressing the array format of N*N;
The quantity of described row control line and row control line is N root, and every capable control line of root and every root row control line are parallel with N number of row transmission gate and the row transmission gate all with a control gate and two signal grids respectively, and the control gate of described row transmission gate is connected with row control line, the control gate of described row transmission gate is connected with row control line;
One signal grid of described each row transmission gate and a signal grid of a described row transmission gate are connected on same described measured device, the row transmission gate be connected with same described measured device and the control gate of row transmission gate anti-phase each other, another signal grid of this row transmission gate is connected with described data line line, another signal grid of this row transmission gate is connected with a described column data line, and is connected with different row data lines respectively from the row transmission gate that the row transmission gate be connected on same described column data line is connected;
Wherein, N is natural number.
In above-mentioned EEPROM device detection circuit, described test circuit also comprises a display module be connected with described master controller, the test data described in display.
A kind of method of testing based on above-mentioned EEPROM device detection circuit described in two of the present invention, it is characterized in that, described method of testing comprises the following steps,
Step one, master controller sends test starting order to test cell, sends decoding order to decoding scheme simultaneously, and controls the capable control line address of N root that the control line address of master controller second I/O port produces by decoding scheme after decoding and be set to low level;
Step 2, after test cell receives the test starting order described in step one, each measured device in test cell returns test data to master controller in real time;
Step 3, if the arbitrary measured device described in step 2 breaks down, column data line in the first I/O port P1 that row transmission gate then by being connected with this measured device connects contains the test data of failure message to master controller output packet, and returns to the address of this column data line to master controller; If measured device does not break down, then return step 2;
Step 4, after master controller receives the test data described in step 3, sends decoding order to decoding scheme, and controls the N root row control line address that the control line address of master controller second I/O port produces by decoding scheme after decoding and be set to low level;
Step 5, master controller scans the row transmission gate of connecting with the transmission gate of row described in step 3 one by one, until after master controller detects the measured device described in step 3, the address of the row data line in the first I/O port P1 connected by the row transmission gate be connected with this measured device turns back to master controller;
Step 6, master controller is according to the address of the column data line described in step 3 and step 5 and the address of row data line and the test data comprising failure message, generate, store and shown the statistical study information of the measured device of fault by display module, and this information comprises failure cause and the coordinate information of measured device;
Wherein, N is natural number.
Owing to have employed above-mentioned technical solution, the present invention utilizes the mode of matrix-scanning to achieve the location of measured device, so just on the basis of concurrent testing, achieve real-time units test, make the significant data such as state, fault occurrence type, time of failure that can obtain each device in test in test process in time; Can confirm state that defective device problem occurs, time, stage in the quality tests such as high/low temperature test, life test in time, this is for analytic product yield, ensures that product quality is significant.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of traditional eeprom memory functional test circuit;
Fig. 2 is the structured flowchart of a kind of EEPROM device detection circuit of the present invention;
Fig. 3 is the structured flowchart of a kind of implementation column of test cell in a kind of EEPROM device detection circuit of the present invention.
Embodiment
Below in conjunction with accompanying drawing, embodiments of the invention are described in detail.
Refer to Fig. 2 to Fig. 3, a kind of EEPROM device detection circuit of the present invention, comprise decoding scheme 2 and a display module 4 be connected with master controller 1 that test cell 3, that a master controller 1, is connected with the data line of the first I/O port P1 of master controller 1 is connected with the control line of the second I/O port P2 of master controller 1, wherein
First I/O port P1 of master controller 1 comprises the capable data line of N root and N root column data line, and row data line and column data line are arranged in a reticulate texture by the form of intersecting in length and breadth, master controller 1 one aspect exports test enable signals to test cell 2, receive the test data that test cell 2 exports on the other hand, generate and store corresponding statistical study information;
Decoding scheme receives decoded signal from described master controller, the address of embarked on journey by the address decoding of the control line of this master controller second I/O port control line and row control line, and the address of described row control line and row control line is set to high level or low level;
Decoding scheme 2 receives decoded signal from master controller 1, embarked on journey by the address decoding of the control line of master controller 1 second I/O port the P2 address of control line and the address of row control line, and the address of row control line and row control line is set to high level or low level; The quantity of row control line and row control line is N root, and every capable control line of root and every root row control line are parallel with N number of row transmission gate 6 and the row transmission gate 5 all with a control gate and two signal grids respectively, and the control gate of row transmission gate 6 is connected with row control line, the control gate of row transmission gate 5 is connected with row control line;
Test cell 3 is connected with decoding scheme 2 by row control line, row control line, and specifically, test cell 3 comprises N
2the individual measured device pressing the array format of N*N; One signal grid of each row transmission gate 6 and a signal grid of a row transmission gate 5 are connected on same measured device, the row transmission gate 6 be connected with same measured device and the control gate of row transmission gate 5 anti-phase each other, another signal grid of this row transmission gate 6 is connected with data line line, another signal grid of this row transmission gate is connected with a column data line, and is connected with different row data lines respectively from the row transmission gate 6 that the row transmission gate 5 be connected on same column data line is connected;
Display module 4 shows the test data received from master controller 1.
N in the present invention is natural number; As shown in Figure 3, in the present embodiment, the value of N is 4, namely, first I/O port P1 of master controller 1 comprises 8 data lines P1<0:7>, and wherein, transversely arranged row data line P1.0 to P1.3 is as monitoring data line, the column data line P1.4 to P1.7 of longitudinal arrangement, as test main data line, realizes command transfer and data receiver; Second I/O port P2 of master controller 1 comprises 2 control line P2<0:1>, obtains 4 row control line C1 to C4 and 4 row control line C1 to C4, as troubleshooting control line after decoding scheme 2 decoding; Test cell 3 comprises the measured device U1 to U16 of the array format by 4*4.Specifically, the every bar line of row control line C1 to C4 is longitudinally parallel with 4 row transmission gates 6, the every bar line of row control line C1 to C4 is longitudinally parallel with 4 row transmission gates 5, each measured device is connected with a line transmission gate 6 and a row transmission gate 5 simultaneously, and be connected with row data line and column data line respectively with row transmission gate 5 by this row transmission gate 6, for measured device U1, it is connected with row data line P1.0 by the row transmission gate 6 on row control line C4, be connected with column data line P1.4 by the row transmission gate 5 on column data line C4, other measured devices are analogized simultaneously; Final realization, the data line P1.0 that is expert at is connected in parallel measured device U1, U2, U3, U4 by row transmission gate 6 and row control line C4 to C1, and other row data lines are analogized; Meanwhile, realize being connected in parallel measured device U1, U5, U9, U13 by row transmission gate 5 and row control line C4 to C1 on column data line P1.4, other column data lines are analogized.
Based on above-mentioned test circuit, the method for testing of its correspondence comprises the following steps:
Step one, master controller 1 sends test starting order to test cell 3, simultaneously send decoding order to decoding scheme 2, and control the capable control line address of N root that the control line address of master controller 1 second I/O port P2 produces by decoding scheme 2 after decoding and be set to low level;
Step 2, after test cell 3 receives the test starting order described in step one, each measured device in test cell 3 returns test data to master controller 1 in real time;
Step 3, if the arbitrary measured device described in step 2 breaks down, column data line in the first I/O port P1 that row transmission gate 5 then by being connected with this measured device connects contains the test data of failure message to master controller 1 output packet, and returns to the address of this column data line to master controller 1; If measured device does not break down, then return step 2;
Step 4, after master controller 1 receives the test data described in step 3, send decoding order to decoding scheme 2, and control the N root row control line address that the control line address of master controller 1 second I/O port P2 produces by decoding scheme 2 after decoding and be set to low level;
Step 5, master controller 1 scans the row transmission gate 6 of connecting with the transmission gate of row described in step 35 one by one, until after master controller 1 detects the measured device described in step 3, the address of the row data line in the first I/O port P1 connected by the row transmission gate 6 be connected with this measured device turns back to master controller 1;
Step 6, master controller 1 is according to the address of the column data line described in step 3 and step 5 and the address of row data line and the test data comprising failure message, generate, store and shown the statistical study information of the measured device of fault by display module, and this information comprises failure cause and the coordinate information of measured device.
The present embodiment, for the measured device U7 in test cell 3, illustrates the method for testing based on this test circuit.After test starts, master controller 1 sends test starting order by column data line P1.4 to P1.7 to test cell 3, the work of control and monitoring and test unit 3, simultaneously, decoding order is sent to decoding scheme 2, and the address controlling 4 row control line C1 to C4 that the control line address of master controller 1 second I/O port P2 produces by decoding scheme 2 after decoding is set to low level, namely the connection of the upper all row transmission gates 6 of row control line C1 to C4 and row data line P1.0 to P1.3 is disconnected, control gate again due to row transmission gate 6 and row transmission gate 5 is anti-phase each other, therefore, the upper all row transmission gates 5 of row control line C1 to C4 are unimpeded with the connection of column data line P1.4 to P1.7, after test cell 3 receives test starting order, the measured device U1 to U16 in test cell 3 returns test data to master controller 1 in real time, after measured device U7 breaks down, the column data line P1.6 then connected by the row transmission gate 5 be connected with measured device U7 is to the test data of master controller 1 output packet containing failure message, and the address of this column data line P1.6 is returned to master controller 1, namely the longitudinal coordinate P1.6 of fault measured device U7 is identified, then master controller 1 sends decoding order by column data line P1.4 to P1.7 to decoding scheme 2, and the address controlling 4 row control line C1 to C4 that the control line address of master controller 1 second I/O port P2 produces by decoding scheme 2 after decoding is set to low level, namely disconnect the connection of the upper all row transmission gates 5 of row control line C1 to C4 and column data line P1.4 to P1.7, the upper all row transmission gates 6 of row control line C1 to C4 are unimpeded with the connection of row data line P1.0 to P1.3, master controller 1 scans the row transmission gate 6 of connecting with the row transmission gate 5 be connected on column data line P1.6 one by one, and can confirm that the lateral coordinates of measured device U7 is P1.1, namely the coordinate of the measured device U7 of fault is finally asserted (P1.1, P1.6), finally, master controller 1, according to the test data comprising failure message obtained, resolves failure cause and the coordinate information of measured device U7, generates log file, storage shown the statistical study information of measured device U7 by display module 4.
In sum, just can be realized the location of defective device by the present invention, thus determine the identification number of defective device.After master controller confirms defective device, record its identification number, fault type, fault-time, show on display circuit simultaneously or upload superior control centre.Such as, function and the graphics test of 64 devices can be realized on traditional AT80C52 type master controller by the present invention.
Below embodiment is to invention has been detailed description by reference to the accompanying drawings, and those skilled in the art can make many variations example to the present invention according to the above description.Thus, some details in embodiment should not form limitation of the invention, the present invention by the scope that defines using appended claims as protection scope of the present invention.
Claims (1)
1. the method for testing of an EEPROM device detection circuit, described test circuit comprises a master controller, a test cell be connected with the data line of the first I/O port of this master controller and a decoding scheme be connected with the control line of the second I/O port of described master controller, it is characterized in that, described method of testing comprises the following steps
Step one, master controller sends test starting order to test cell, sends decoding order to decoding scheme simultaneously, and controls the capable control line address of N root that the control line address of master controller second I/O port produces by decoding scheme after decoding and be set to low level;
Step 2, after test cell receives the test starting order described in step one, each measured device in test cell returns test data to master controller in real time;
Step 3, if arbitrary measured device breaks down in step 2, column data line in the first I/O port P1 that row transmission gate then by being connected with this measured device connects contains the test data of failure message to master controller output packet, and returns to the address of this column data line to master controller; If measured device does not break down, then return step 2;
Step 4, after master controller receives the test data described in step 3, sends decoding order to decoding scheme, and controls the N root row control line address that the control line address of master controller second I/O port produces by decoding scheme after decoding and be set to low level;
Step 5, master controller scans the row transmission gate of connecting with the transmission gate of row described in step 3 one by one, until after master controller detects the measured device described in step 3, the address of the row data line in the first I/O port P1 connected by the row transmission gate be connected with this measured device turns back to master controller;
Step 6, master controller is according to the address of the column data line described in step 3 and step 5 and the address of row data line and the test data comprising failure message, generate, store and shown the statistical study information of the measured device of fault by display module, and this information comprises failure cause and the coordinate information of measured device;
Wherein, N is natural number.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200910199595.7A CN102081972B (en) | 2009-11-27 | 2009-11-27 | Test circuit for EEPROM device and test method thereof |
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| CN200910199595.7A CN102081972B (en) | 2009-11-27 | 2009-11-27 | Test circuit for EEPROM device and test method thereof |
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| CN102081972B true CN102081972B (en) | 2015-05-20 |
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| KR20130042334A (en) * | 2011-10-18 | 2013-04-26 | 에스케이하이닉스 주식회사 | Integrated circuit chip and semiconductor memory device |
| CN104658613A (en) * | 2014-12-30 | 2015-05-27 | 中国电子科技集团公司第四十七研究所 | EEPROM durability test method and EEPROM durability test device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1682314A (en) * | 2002-09-11 | 2005-10-12 | 因芬尼昂技术股份公司 | Circuit and method for testing embedded dram circuits |
| CN1832042A (en) * | 2004-12-30 | 2006-09-13 | 三星电子株式会社 | Program verification for non-volatile memory |
| CN101154459A (en) * | 2000-09-28 | 2008-04-02 | 株式会社东芝 | Nonvolatile semiconductor memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154459A (en) * | 2000-09-28 | 2008-04-02 | 株式会社东芝 | Nonvolatile semiconductor memory device |
| CN1682314A (en) * | 2002-09-11 | 2005-10-12 | 因芬尼昂技术股份公司 | Circuit and method for testing embedded dram circuits |
| CN1832042A (en) * | 2004-12-30 | 2006-09-13 | 三星电子株式会社 | Program verification for non-volatile memory |
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